ENTROPY_SRC Simulation Results

Monday August 05 2024 23:02:13 UTC

GitHub Revision: e4c5daa580

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 57478527486894479494471273459769404654835266620222125964939301612221385668501

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 8.000s 75.593us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 3.000s 112.265us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 3.000s 17.458us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 20.000s 3.815ms 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 6.000s 79.706us 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 4.000s 108.972us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 3.000s 17.458us 20 20 100.00
entropy_src_csr_aliasing 6.000s 79.706us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 8.000s 75.593us 50 50 100.00
entropy_src_rng 10.650m 20.023ms 300 300 100.00
entropy_src_fw_ov 9.550m 19.035ms 260 300 86.67
V2 firmware_mode entropy_src_fw_ov 9.550m 19.035ms 260 300 86.67
V2 rng_mode entropy_src_rng 10.650m 20.023ms 300 300 100.00
V2 rng_max_rate entropy_src_rng_max_rate 17.750m 20.030ms 398 400 99.50
V2 health_checks entropy_src_rng 10.650m 20.023ms 300 300 100.00
V2 conditioning entropy_src_rng 10.650m 20.023ms 300 300 100.00
V2 interrupts entropy_src_rng 10.650m 20.023ms 300 300 100.00
entropy_src_intr 23.000s 2.037ms 50 50 100.00
V2 alerts entropy_src_rng 10.650m 20.023ms 300 300 100.00
entropy_src_functional_alerts 14.000s 784.247us 50 50 100.00
V2 stress_all entropy_src_stress_all 9.233m 19.207ms 50 50 100.00
V2 functional_errors entropy_src_functional_errors 10.050m 10.012ms 966 1000 96.60
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 28.000s 1.310ms 50 50 100.00
V2 intr_test entropy_src_intr_test 7.000s 18.940us 50 50 100.00
V2 alert_test entropy_src_alert_test 13.000s 41.994us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 7.000s 173.073us 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 7.000s 173.073us 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 3.000s 112.265us 5 5 100.00
entropy_src_csr_rw 3.000s 17.458us 20 20 100.00
entropy_src_csr_aliasing 6.000s 79.706us 5 5 100.00
entropy_src_same_csr_outstanding 4.000s 170.859us 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 3.000s 112.265us 5 5 100.00
entropy_src_csr_rw 3.000s 17.458us 20 20 100.00
entropy_src_csr_aliasing 6.000s 79.706us 5 5 100.00
entropy_src_same_csr_outstanding 4.000s 170.859us 20 20 100.00
V2 TOTAL 2264 2340 96.75
V2S tl_intg_err entropy_src_sec_cm 11.000s 138.916us 5 5 100.00
entropy_src_tl_intg_err 11.000s 386.963us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 10.650m 20.023ms 300 300 100.00
entropy_src_cfg_regwen 7.000s 16.434us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 10.650m 20.023ms 300 300 100.00
V2S sec_cm_config_redun entropy_src_rng 10.650m 20.023ms 300 300 100.00
V2S sec_cm_intersig_mubi entropy_src_rng 10.650m 20.023ms 300 300 100.00
entropy_src_fw_ov 9.550m 19.035ms 260 300 86.67
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 10.050m 10.012ms 966 1000 96.60
entropy_src_sec_cm 11.000s 138.916us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 10.050m 10.012ms 966 1000 96.60
entropy_src_sec_cm 11.000s 138.916us 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 10.650m 20.023ms 300 300 100.00
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 10.050m 10.012ms 966 1000 96.60
entropy_src_sec_cm 11.000s 138.916us 5 5 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 10.050m 10.012ms 966 1000 96.60
entropy_src_sec_cm 11.000s 138.916us 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 10.050m 10.012ms 966 1000 96.60
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 14.000s 784.247us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 11.000s 386.963us 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 9.033m 18.021ms 50 50 100.00
V3 stress_all_with_rand_reset entropy_src_stress_all_with_rand_reset 0 0 --
V3 TOTAL 50 50 100.00
TOTAL 2494 2570 97.04

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 12 12 9 75.00
V2S 3 3 3 100.00
V3 2 1 1 50.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
97.18 98.15 95.32 98.36 95.79 96.71 96.88 90.48 96.16

Failure Buckets

Past Results