ENTROPY_SRC Simulation Results

Tuesday July 30 2024 23:02:08 UTC

GitHub Revision: fdfa12db04

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 101467584611478134588291649782725219255540557286164709436567235390830780957271

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 13.000s 85.710us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 3.000s 29.041us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 4.000s 46.009us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 16.000s 5.097ms 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 6.000s 84.665us 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 8.000s 31.911us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 4.000s 46.009us 20 20 100.00
entropy_src_csr_aliasing 6.000s 84.665us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 13.000s 85.710us 50 50 100.00
entropy_src_rng 5.533m 10.051ms 299 300 99.67
entropy_src_fw_ov 3.117m 5.019ms 283 300 94.33
V2 firmware_mode entropy_src_fw_ov 3.117m 5.019ms 283 300 94.33
V2 rng_mode entropy_src_rng 5.533m 10.051ms 299 300 99.67
V2 rng_max_rate entropy_src_rng_max_rate 9.567m 10.063ms 396 400 99.00
V2 health_checks entropy_src_rng 5.533m 10.051ms 299 300 99.67
V2 conditioning entropy_src_rng 5.533m 10.051ms 299 300 99.67
V2 interrupts entropy_src_rng 5.533m 10.051ms 299 300 99.67
entropy_src_intr 20.000s 346.233us 50 50 100.00
V2 alerts entropy_src_rng 5.533m 10.051ms 299 300 99.67
entropy_src_functional_alerts 14.000s 105.013us 50 50 100.00
V2 stress_all entropy_src_stress_all 16.000s 410.605us 50 50 100.00
V2 functional_errors entropy_src_functional_errors 9.683m 10.013ms 970 1000 97.00
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 24.000s 702.172us 50 50 100.00
V2 intr_test entropy_src_intr_test 4.000s 55.731us 50 50 100.00
V2 alert_test entropy_src_alert_test 9.000s 40.352us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 8.000s 541.276us 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 8.000s 541.276us 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 3.000s 29.041us 5 5 100.00
entropy_src_csr_rw 4.000s 46.009us 20 20 100.00
entropy_src_csr_aliasing 6.000s 84.665us 5 5 100.00
entropy_src_same_csr_outstanding 5.000s 635.184us 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 3.000s 29.041us 5 5 100.00
entropy_src_csr_rw 4.000s 46.009us 20 20 100.00
entropy_src_csr_aliasing 6.000s 84.665us 5 5 100.00
entropy_src_same_csr_outstanding 5.000s 635.184us 20 20 100.00
V2 TOTAL 2288 2340 97.78
V2S tl_intg_err entropy_src_sec_cm 9.000s 575.626us 5 5 100.00
entropy_src_tl_intg_err 6.000s 683.386us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 5.533m 10.051ms 299 300 99.67
entropy_src_cfg_regwen 18.000s 40.721us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 5.533m 10.051ms 299 300 99.67
V2S sec_cm_config_redun entropy_src_rng 5.533m 10.051ms 299 300 99.67
V2S sec_cm_intersig_mubi entropy_src_rng 5.533m 10.051ms 299 300 99.67
entropy_src_fw_ov 3.117m 5.019ms 283 300 94.33
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 9.683m 10.013ms 970 1000 97.00
entropy_src_sec_cm 9.000s 575.626us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 9.683m 10.013ms 970 1000 97.00
entropy_src_sec_cm 9.000s 575.626us 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 5.533m 10.051ms 299 300 99.67
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 9.683m 10.013ms 970 1000 97.00
entropy_src_sec_cm 9.000s 575.626us 5 5 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 9.683m 10.013ms 970 1000 97.00
entropy_src_sec_cm 9.000s 575.626us 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 9.683m 10.013ms 970 1000 97.00
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 14.000s 105.013us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 6.000s 683.386us 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 5.467m 10.013ms 50 50 100.00
V3 stress_all_with_rand_reset entropy_src_stress_all_with_rand_reset 0 0 --
V3 TOTAL 50 50 100.00
TOTAL 2518 2570 97.98

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 12 12 8 66.67
V2S 3 3 3 100.00
V3 2 1 1 50.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
97.13 98.19 95.43 98.36 95.79 96.53 96.88 90.48 95.77

Failure Buckets

Past Results