ENTROPY_SRC Simulation Results

Wednesday July 31 2024 23:02:38 UTC

GitHub Revision: e9b7e615a7

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 25204348267605859133056659113100703417171299070132656462514712657132693373848

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 12.000s 99.602us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 3.000s 19.254us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 5.000s 138.129us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 15.000s 1.036ms 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 8.000s 1.015ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 4.000s 30.063us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 5.000s 138.129us 20 20 100.00
entropy_src_csr_aliasing 8.000s 1.015ms 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 12.000s 99.602us 50 50 100.00
entropy_src_rng 5.733m 10.064ms 300 300 100.00
entropy_src_fw_ov 2.883m 5.050ms 285 300 95.00
V2 firmware_mode entropy_src_fw_ov 2.883m 5.050ms 285 300 95.00
V2 rng_mode entropy_src_rng 5.733m 10.064ms 300 300 100.00
V2 rng_max_rate entropy_src_rng_max_rate 9.683m 10.043ms 397 400 99.25
V2 health_checks entropy_src_rng 5.733m 10.064ms 300 300 100.00
V2 conditioning entropy_src_rng 5.733m 10.064ms 300 300 100.00
V2 interrupts entropy_src_rng 5.733m 10.064ms 300 300 100.00
entropy_src_intr 25.000s 1.082ms 50 50 100.00
V2 alerts entropy_src_rng 5.733m 10.064ms 300 300 100.00
entropy_src_functional_alerts 13.000s 297.111us 50 50 100.00
V2 stress_all entropy_src_stress_all 22.000s 705.857us 50 50 100.00
V2 functional_errors entropy_src_functional_errors 9.633m 10.013ms 969 1000 96.90
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 31.000s 380.134us 50 50 100.00
V2 intr_test entropy_src_intr_test 5.000s 51.372us 50 50 100.00
V2 alert_test entropy_src_alert_test 8.000s 75.688us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 8.000s 530.711us 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 8.000s 530.711us 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 3.000s 19.254us 5 5 100.00
entropy_src_csr_rw 5.000s 138.129us 20 20 100.00
entropy_src_csr_aliasing 8.000s 1.015ms 5 5 100.00
entropy_src_same_csr_outstanding 5.000s 206.545us 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 3.000s 19.254us 5 5 100.00
entropy_src_csr_rw 5.000s 138.129us 20 20 100.00
entropy_src_csr_aliasing 8.000s 1.015ms 5 5 100.00
entropy_src_same_csr_outstanding 5.000s 206.545us 20 20 100.00
V2 TOTAL 2291 2340 97.91
V2S tl_intg_err entropy_src_sec_cm 4.000s 94.833us 5 5 100.00
entropy_src_tl_intg_err 7.000s 754.019us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 5.733m 10.064ms 300 300 100.00
entropy_src_cfg_regwen 10.000s 57.715us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 5.733m 10.064ms 300 300 100.00
V2S sec_cm_config_redun entropy_src_rng 5.733m 10.064ms 300 300 100.00
V2S sec_cm_intersig_mubi entropy_src_rng 5.733m 10.064ms 300 300 100.00
entropy_src_fw_ov 2.883m 5.050ms 285 300 95.00
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 9.633m 10.013ms 969 1000 96.90
entropy_src_sec_cm 4.000s 94.833us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 9.633m 10.013ms 969 1000 96.90
entropy_src_sec_cm 4.000s 94.833us 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 5.733m 10.064ms 300 300 100.00
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 9.633m 10.013ms 969 1000 96.90
entropy_src_sec_cm 4.000s 94.833us 5 5 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 9.633m 10.013ms 969 1000 96.90
entropy_src_sec_cm 4.000s 94.833us 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 9.633m 10.013ms 969 1000 96.90
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 13.000s 297.111us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 7.000s 754.019us 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 5.283m 10.067ms 50 50 100.00
V3 stress_all_with_rand_reset entropy_src_stress_all_with_rand_reset 0 0 --
V3 TOTAL 50 50 100.00
TOTAL 2521 2570 98.09

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 12 12 9 75.00
V2S 3 3 3 100.00
V3 2 1 1 50.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
97.11 98.11 95.22 98.33 95.79 96.59 96.88 90.48 95.96

Failure Buckets

Past Results