FLASH_CTRL Simulation Results

Thursday May 18 2023 07:04:58 UTC

GitHub Revision: `ac0bef2ce`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 2907120974

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.631m	70.062us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	25.810s	15.596us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	45.330s	85.734us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	17.590s	138.059us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.357m	6.107ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	54.610s	550.865us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	19.740s	33.883us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	17.590s	138.059us	20	20	100.00
		flash_ctrl_csr_aliasing	54.610s	550.865us	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.370s	25.148us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	13.460s	17.885us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	26.680s	21.554us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	1.669m	88.815us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	31.559m	292.656ms	3	3	100.00
		flash_ctrl_hw_rma_reset	17.158m	350.288ms	20	20	100.00
		flash_ctrl_lcmgr_intg	14.880s	26.024us	19	20	95.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	47.076m	253.692ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	7.856m	7.646ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	3.862m	3.436ms	29	30	96.67
V2	full_memory_access	flash_ctrl_full_mem_access	52.154m	313.156ms	4	5	80.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	2.546m	705.685us	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	37.510s	453.582us	39	40	97.50
		flash_ctrl_rw_evict_all_en	38.440s	407.519us	39	40	97.50
		flash_ctrl_re_evict	40.280s	228.778us	19	20	95.00
V2	host_arb	flash_ctrl_phy_arb	8.750m	8.196ms	19	20	95.00
V2	host_interleave	flash_ctrl_phy_arb	8.750m	8.196ms	19	20	95.00
V2	memory_protection	flash_ctrl_mp_regions	16.230m	86.053ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	28.790s	1.694ms	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	20.212m	1.633ms	18	20	90.00
V2	error_mp	flash_ctrl_error_mp	45.756m	89.891ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	18.199m	6.669ms	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	47.650m	3.663ms	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	16.960s	32.992us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	6.523m	21.951ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	24.000s	12.814us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	18.990s	29.630us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	21.818m	365.182us	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.252m	6.080ms	50	50	100.00
		flash_ctrl_otp_reset	2.333m	82.777us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	31.559m	292.656ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	7.844m	20.206ms	40	40	100.00
		flash_ctrl_intr_wr	2.153m	9.526ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	11.262m	200.745ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	10.588m	356.852ms	8	10	80.00
V2	invalid_op	flash_ctrl_invalid_op	1.627m	2.153ms	17	20	85.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	37.930s	13.940ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	23.190s	150.107us	5	5	100.00
		flash_ctrl_ro_derr	7.825m	2.781ms	10	10	100.00
		flash_ctrl_rw_derr	31.309m	7.175ms	10	10	100.00
		flash_ctrl_derr_detect	2.169m	189.735us	5	5	100.00
		flash_ctrl_integrity	31.820m	13.629ms	5	5	100.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	22.680s	83.638us	5	5	100.00
		flash_ctrl_ro_serr	5.678m	2.148ms	10	10	100.00
		flash_ctrl_rw_serr	30.327m	27.187ms	10	10	100.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.420m	7.041ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.485m	1.738ms	5	5	100.00
V2	scramble	flash_ctrl_wo	4.075m	2.632ms	20	20	100.00
		flash_ctrl_write_word_sweep	17.550s	232.708us	1	1	100.00
		flash_ctrl_read_word_sweep	14.180s	46.857us	1	1	100.00
		flash_ctrl_ro	4.948m	14.461ms	20	20	100.00
		flash_ctrl_rw	23.698m	5.198ms	20	20	100.00
V2	filesystem_support	flash_ctrl_fs_sup	39.040s	406.558us	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	14.272m	55.982ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	4.215m	10.013ms	19	20	95.00
V2	alert_test	flash_ctrl_alert_test	15.700s	80.151us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	13.640s	106.781us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	20.370s	112.143us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	20.370s	112.143us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	45.330s	85.734us	5	5	100.00
		flash_ctrl_csr_rw	17.590s	138.059us	20	20	100.00
		flash_ctrl_csr_aliasing	54.610s	550.865us	5	5	100.00
		flash_ctrl_same_csr_outstanding	36.830s	1.951ms	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	45.330s	85.734us	5	5	100.00
		flash_ctrl_csr_rw	17.590s	138.059us	20	20	100.00
		flash_ctrl_csr_aliasing	54.610s	550.865us	5	5	100.00
		flash_ctrl_same_csr_outstanding	36.830s	1.951ms	20	20	100.00
V2		TOTAL			998	1013	98.52
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	2.012m	166.987us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	2.012m	166.987us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	2.012m	166.987us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	2.012m	166.987us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	1.616m	1.345ms	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.401h	964.291us	5	5	100.00
		flash_ctrl_tl_intg_err	14.872m	1.357ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	14.872m	1.357ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	14.872m	1.357ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	32.260s	216.332us	2	3	66.67
		flash_ctrl_wr_intg	15.020s	143.484us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.631m	70.062us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.333m	82.777us	80	80	100.00
		flash_ctrl_disable	24.000s	12.814us	50	50	100.00
		flash_ctrl_sec_info_access	1.423m	13.462ms	50	50	100.00
		flash_ctrl_connect	18.990s	29.630us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	14.220s	19.938us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	17.590s	138.059us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	2.012m	166.987us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	17.590s	138.059us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	2.012m	166.987us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	17.590s	138.059us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	2.012m	166.987us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	24.000s	12.814us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	32.260s	216.332us	2	3	66.67
		flash_ctrl_access_after_disable	13.870s	39.244us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	24.000s	12.814us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	28.790s	1.694ms	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	23.698m	5.198ms	20	20	100.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	30.327m	27.187ms	10	10	100.00
		flash_ctrl_rw_derr	31.309m	7.175ms	10	10	100.00
		flash_ctrl_integrity	31.820m	13.629ms	5	5	100.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	31.559m	292.656ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.401h	964.291us	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.401h	964.291us	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.401h	964.291us	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.401h	964.291us	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	14.650s	19.716us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.770s	18.189us	4	5	80.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	14.170s	28.783us	3	5	60.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.401h	964.291us	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.401h	964.291us	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.401h	964.291us	5	5	100.00
V2S		TOTAL			140	144	97.22
V3	asymmetric_read_path	flash_ctrl_rd_ooo	32.860s	54.392us	0	1	0.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	1	0.00
		TOTAL			1258	1278	98.44

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	44	80.00
V2S	12	12	9	75.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.52	95.49	94.39	98.95	92.52	97.32	98.30	98.68

Failure Buckets

UVM_ERROR (cip_base_scoreboard.sv:221) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 2 failures:

Test flash_ctrl_invalid_op has 2 failures.

4.flash_ctrl_invalid_op.803076084
Line 3748, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_invalid_op/latest/run.log

  UVM_ERROR @ 2123275.9 ns: (cip_base_scoreboard.sv:221) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 2123275.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.flash_ctrl_invalid_op.164027053
Line 3279, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_invalid_op/latest/run.log

  UVM_ERROR @ 2051574.4 ns: (cip_base_scoreboard.sv:221) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 2051574.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (flash_phy_prim_monitor.sv:44) [monitor] timeout waiting for mon_start has 2 failures:

Test flash_ctrl_intr_wr_slow_flash has 2 failures.

4.flash_ctrl_intr_wr_slow_flash.446712139
Line 261, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_intr_wr_slow_flash/latest/run.log

  UVM_FATAL @ 200000.0 ns: (flash_phy_prim_monitor.sv:44) [uvm_test_top.env.m_fpp_agent.monitor] timeout waiting for mon_start
  UVM_INFO @ 200000.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.flash_ctrl_intr_wr_slow_flash.3310392939
Line 261, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_intr_wr_slow_flash/latest/run.log

  UVM_FATAL @ 200000.0 ns: (flash_phy_prim_monitor.sv:44) [uvm_test_top.env.m_fpp_agent.monitor] timeout waiting for mon_start
  UVM_INFO @ 200000.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (flash_ctrl_scoreboard.sv:696) [scoreboard] Check failed exp_data_part[addr] == data (* [*] vs * [*]) read addr:* data: * has 2 failures:

Test flash_ctrl_rand_ops has 2 failures.

10.flash_ctrl_rand_ops.211223302
Line 1655, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/10.flash_ctrl_rand_ops/latest/run.log

  UVM_ERROR @ 321980.1 ns: (flash_ctrl_scoreboard.sv:696) [uvm_test_top.env.scoreboard] Check failed exp_data_part[addr] == data (752115481 [0x2cd45f19] vs 1340142615 [0x4fe0f417]) read addr:0x80780 data: 0x4fe0f417
  UVM_INFO @ 321980.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

11.flash_ctrl_rand_ops.2357351578
Line 276698, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/11.flash_ctrl_rand_ops/latest/run.log

  UVM_ERROR @ 11969724.9 ns: (flash_ctrl_scoreboard.sv:696) [uvm_test_top.env.scoreboard] Check failed exp_data_part[addr] == data (2455051512 [0x92551cf8] vs 3472597820 [0xcefba33c]) read addr:0x806c0 data: 0xcefba33c
  UVM_INFO @ 11969724.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (flash_ctrl_rd_path_intg_vseq.sv:59) [flash_ctrl_rd_path_intg_vseq] Check failed saw_err == * (* [*] vs * [*]) has 1 failures:
- Test flash_ctrl_rd_intg has 1 failures.
  - 0.flash_ctrl_rd_intg.2842473999
    Line 278, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rd_intg/latest/run.log
```
  UVM_ERROR @ 97100.9 ns: (flash_ctrl_rd_path_intg_vseq.sv:59) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rd_path_intg_vseq] Check failed saw_err == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 97100.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:221) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_std_err triggered unexpectedly has 1 failures:
- Test flash_ctrl_phy_ack_consistency has 1 failures.
  - 0.flash_ctrl_phy_ack_consistency.515167576
    Line 262, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_phy_ack_consistency/latest/run.log
```
  UVM_ERROR @ 19333.2 ns: (cip_base_scoreboard.sv:221) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_std_err triggered unexpectedly
  UVM_INFO @ 19333.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_env_cfg.sv:400) [cfg] Undefined initialization scheme - FlashMemInitCustom has 1 failures:
- Test flash_ctrl_rd_ooo has 1 failures.
  - 0.flash_ctrl_rd_ooo.1733122810
    Line 261, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rd_ooo/latest/run.log
```
  UVM_ERROR @ 54392.3 ns: (flash_ctrl_env_cfg.sv:400) [cfg] Undefined initialization scheme - FlashMemInitCustom
  UVM_INFO @ 54392.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test flash_ctrl_full_mem_access has 1 failures.
  - 1.flash_ctrl_full_mem_access.213887499
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_full_mem_access/latest/run.log
```
  Job ID: smart:98a697b8-6ade-4040-9489-a6e4dbdd5464
```
Offending '$past(clr_i)' has 1 failures:
- Test flash_ctrl_phy_ack_consistency has 1 failures.
  - 1.flash_ctrl_phy_ack_consistency.3851591047
    Line 263, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_phy_ack_consistency/latest/run.log
```
      Offending '$past(clr_i)'
  UVM_ERROR @ 46684.0 ns: (prim_count.sv:167) [ASSERT FAILED] ClrBkwd_A
  UVM_INFO @ 46684.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(!$isunknown(mem_tl_o.d_valid))' has 1 failures:
- Test flash_ctrl_phy_host_grant_err has 1 failures.
  - 3.flash_ctrl_phy_host_grant_err.1071231921
    Line 262, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_phy_host_grant_err/latest/run.log
```
      Offending '(!$isunknown(mem_tl_o.d_valid))'
  UVM_ERROR @ 5586.7 ns: (flash_ctrl.sv:1397) [ASSERT FAILED] MemTlDValidKnownO_A
  UVM_INFO @ 5586.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:373) [rdata_comp_bank0] *: obs:exp fe6311cb_ffffffff:97a30ef9_ffffffff mismatch!! has 1 failures:
- Test flash_ctrl_re_evict has 1 failures.
  - 4.flash_ctrl_re_evict.160837622
    Line 261, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_re_evict/latest/run.log
```
  UVM_ERROR @ 119079.3 ns: (flash_ctrl_otf_scoreboard.sv:373) [rdata_comp_bank0]    7: obs:exp    fe6311cb_ffffffff:97a30ef9_ffffffff  mismatch!!
  UVM_INFO @ 119079.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:221) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_err triggered unexpectedly has 1 failures:
- Test flash_ctrl_invalid_op has 1 failures.
  - 9.flash_ctrl_invalid_op.3128922685
    Line 760, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_invalid_op/latest/run.log
```
  UVM_ERROR @ 221672.2 ns: (cip_base_scoreboard.sv:221) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_err triggered unexpectedly
  UVM_INFO @ 221672.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:479) [lm_wdata_comp_bank0] Check failed rcv.mem_addr == exp.req.addr (* [*] vs * [*]) has 1 failures:
- Test flash_ctrl_hw_prog_rma_wipe_err has 1 failures.
  - 10.flash_ctrl_hw_prog_rma_wipe_err.1747712352
    Line 269, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/10.flash_ctrl_hw_prog_rma_wipe_err/latest/run.log
```
  UVM_ERROR @ 10016903.4 ns: (flash_ctrl_otf_scoreboard.sv:479) [lm_wdata_comp_bank0] Check failed rcv.mem_addr == exp.req.addr (0 [0x0] vs 30698 [0x77ea])
  UVM_INFO @ 10016903.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (flash_ctrl_scoreboard.sv:819) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@160989) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test flash_ctrl_rw_evict has 1 failures.

12.flash_ctrl_rw_evict.2382805578
Line 261, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/12.flash_ctrl_rw_evict/latest/run.log

  UVM_ERROR @ 68565.6 ns: (flash_ctrl_scoreboard.sv:819) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@160989) { a_addr: 'h169a0  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h50  a_opcode: 'h4  a_user: 'h252aa  d_param: 'h0  d_source: 'h50  d_data: 'h4175ce5d  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd7e  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 68565.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.std_fault_status.lcmgr_intg_err reset value: * has 1 failures:
- Test flash_ctrl_lcmgr_intg has 1 failures.
  - 16.flash_ctrl_lcmgr_intg.2345605217
    Line 264, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/16.flash_ctrl_lcmgr_intg/latest/run.log
```
  UVM_ERROR @ 94861.0 ns: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.std_fault_status.lcmgr_intg_err reset value: 0x0
  UVM_INFO @ 94861.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:190) [scoreboard] Check failed exp_data[*] == trans.d_data (* [*] vs * [*]) has 1 failures:
- Test flash_ctrl_phy_arb has 1 failures.
  - 17.flash_ctrl_phy_arb.3823555143
    Line 325, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/17.flash_ctrl_phy_arb/latest/run.log
```
  UVM_ERROR @ 2342884.0 ns: (flash_ctrl_scoreboard.sv:190) [uvm_test_top.env.scoreboard] Check failed exp_data[0] == trans.d_data (690643589 [0x292a6285] vs 1832426858 [0x6d389d6a])
  UVM_INFO @ 2342884.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (flash_ctrl_prog_reset_vseq.sv:76) [flash_ctrl_prog_reset_vseq] Timed out waiting for DVStPrePack has 1 failures:
- Test flash_ctrl_prog_reset has 1 failures.
  - 21.flash_ctrl_prog_reset.1420672054
    Line 261, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/21.flash_ctrl_prog_reset/latest/run.log
```
  UVM_FATAL @ 10017778.3 ns: (flash_ctrl_prog_reset_vseq.sv:76) [uvm_test_top.env.virtual_sequencer.flash_ctrl_prog_reset_vseq] Timed out waiting for DVStPrePack
  UVM_INFO @ 10017778.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 1 failures:
- Test flash_ctrl_rw_evict_all_en has 1 failures.
  - 34.flash_ctrl_rw_evict_all_en.3587464071
    Line 261, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/34.flash_ctrl_rw_evict_all_en/latest/run.log
```
  UVM_ERROR @ 24502.7 ns: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 24502.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```