FLASH_CTRL Simulation Results

Sunday December 31 2023 20:02:18 UTC

GitHub Revision: `a9c19f09f3`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 36521940887861431083267591129785326983863798057293121812910170439117479843669

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	4.470m	709.025us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.230s	43.529us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	45.250s	69.198us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	17.460s	1.396ms	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.338m	3.223ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.071m	1.587ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	19.630s	34.572us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	17.460s	1.396ms	20	20	100.00
		flash_ctrl_csr_aliasing	1.071m	1.587ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.690s	69.091us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	13.560s	18.645us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	26.910s	84.338us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	1.679m	278.009us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	35.807m	746.157ms	3	3	100.00
		flash_ctrl_hw_rma_reset	14.514m	160.185ms	20	20	100.00
		flash_ctrl_lcmgr_intg	13.660s	15.160us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	45.636m	263.620ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	7.955m	5.507ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	20.240s	207.548us	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	42.520m	81.111ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	2.556m	8.760ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	37.370s	117.241us	40	40	100.00
		flash_ctrl_rw_evict_all_en	38.830s	169.178us	40	40	100.00
		flash_ctrl_re_evict	39.970s	157.627us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	10.362m	8.510ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	10.362m	8.510ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	22.073m	69.311ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	28.740s	4.338ms	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	15.402m	1.675ms	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	44.494m	63.199ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	15.524m	1.547ms	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	47.191m	2.082ms	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	13.630s	14.822us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	3.203m	3.159ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	1.081m	10.126ms	47	50	94.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.230s	149.526us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	18.449m	562.464us	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.050m	58.515ms	50	50	100.00
		flash_ctrl_otp_reset	2.261m	152.583us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	35.807m	746.157ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	3.292m	23.134ms	40	40	100.00
		flash_ctrl_intr_wr	1.974m	9.484ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	4.439m	68.177ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	8.149m	211.543ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.491m	5.737ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.392m	16.465ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	22.470s	18.407us	5	5	100.00
		flash_ctrl_ro_derr	2.496m	2.798ms	10	10	100.00
		flash_ctrl_rw_derr	9.746m	9.548ms	10	10	100.00
		flash_ctrl_derr_detect	1.776m	117.180us	5	5	100.00
		flash_ctrl_integrity	10.195m	16.525ms	5	5	100.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	22.690s	92.481us	5	5	100.00
		flash_ctrl_ro_serr	2.229m	6.096ms	10	10	100.00
		flash_ctrl_rw_serr	10.228m	21.989ms	10	10	100.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.365m	3.340ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.419m	891.955us	5	5	100.00
V2	scramble	flash_ctrl_wo	3.537m	4.425ms	20	20	100.00
		flash_ctrl_write_word_sweep	17.280s	433.228us	1	1	100.00
		flash_ctrl_read_word_sweep	13.250s	16.283us	1	1	100.00
		flash_ctrl_ro	1.915m	465.450us	20	20	100.00
		flash_ctrl_rw	11.543m	4.375ms	20	20	100.00
V2	filesystem_support	flash_ctrl_fs_sup	36.910s	3.172ms	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	14.908m	109.863ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	3.085m	10.019ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	14.540s	131.144us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	13.990s	84.305us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	20.130s	206.301us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	20.130s	206.301us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	45.250s	69.198us	5	5	100.00
		flash_ctrl_csr_rw	17.460s	1.396ms	20	20	100.00
		flash_ctrl_csr_aliasing	1.071m	1.587ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	35.240s	325.008us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	45.250s	69.198us	5	5	100.00
		flash_ctrl_csr_rw	17.460s	1.396ms	20	20	100.00
		flash_ctrl_csr_aliasing	1.071m	1.587ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	35.240s	325.008us	20	20	100.00
V2		TOTAL			1010	1013	99.70
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	15.930s	58.925us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	15.930s	58.925us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	15.930s	58.925us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	15.930s	58.925us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	15.820s	24.370us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.313h	5.163ms	5	5	100.00
		flash_ctrl_tl_intg_err	15.113m	10.878ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.113m	10.878ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.113m	10.878ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	31.930s	118.701us	3	3	100.00
		flash_ctrl_wr_intg	14.900s	51.762us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	4.470m	709.025us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.261m	152.583us	80	80	100.00
		flash_ctrl_disable	1.081m	10.126ms	47	50	94.00
		flash_ctrl_sec_info_access	1.504m	13.082ms	50	50	100.00
		flash_ctrl_connect	16.230s	149.526us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	13.920s	66.821us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	17.460s	1.396ms	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	15.930s	58.925us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	17.460s	1.396ms	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	15.930s	58.925us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	17.460s	1.396ms	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	15.930s	58.925us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	1.081m	10.126ms	47	50	94.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	31.930s	118.701us	3	3	100.00
		flash_ctrl_access_after_disable	13.740s	23.352us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	1.081m	10.126ms	47	50	94.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	28.740s	4.338ms	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	11.543m	4.375ms	20	20	100.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	10.228m	21.989ms	10	10	100.00
		flash_ctrl_rw_derr	9.746m	9.548ms	10	10	100.00
		flash_ctrl_integrity	10.195m	16.525ms	5	5	100.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	35.807m	746.157ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.313h	5.163ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.313h	5.163ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.313h	5.163ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.313h	5.163ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	17.810s	125.905us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	13.860s	30.540us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	14.050s	25.083us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.313h	5.163ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.313h	5.163ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.313h	5.163ms	5	5	100.00
V2S		TOTAL			144	144	100.00
V3	asymmetric_read_path	flash_ctrl_rd_ooo	45.440s	114.825us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1275	1278	99.77

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	54	98.18
V2S	12	12	12	100.00
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.69	95.81	94.23	98.95	92.52	98.38	98.30	98.65

Failure Buckets

UVM_FATAL (csr_utils_pkg.sv:566) [csr_utils::csr_spinwait] timeout flash_ctrl_core_reg_block.status.rd_empty (addr=*) == * has 1 failures:
- Test flash_ctrl_disable has 1 failures.
  - 2.flash_ctrl_disable.55547013708961524467067087275061251284866810503091495444387242052462167260116
    Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_disable/latest/run.log
```
  UVM_FATAL @ 10125852.5 ns: (csr_utils_pkg.sv:566) [csr_utils::csr_spinwait] timeout flash_ctrl_core_reg_block.status.rd_empty (addr=0x76d52774) == 0x1
  UVM_INFO @ 10125852.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_scoreboard.sv:455) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_core_reg_block, TL item: req: (cip_tl_seq_item@79472) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test flash_ctrl_disable has 1 failures.

27.flash_ctrl_disable.7974915628825754792680871011739370956436042037585979975850013098733656844181
Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/27.flash_ctrl_disable/latest/run.log

  UVM_ERROR @ 10456.6 ns: (cip_base_scoreboard.sv:455) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_core_reg_block, TL item: req: (cip_tl_seq_item@79472) { a_addr: 'h568915b0  a_data: 'h19578d32  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h8a  a_opcode: 'h0  a_user: 'h265f7  d_param: 'h0  d_source: 'h8a  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 10456.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_scoreboard.sv:455) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_core_reg_block, TL item: req: (cip_tl_seq_item@80132) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test flash_ctrl_disable has 1 failures.

40.flash_ctrl_disable.105267692671055416997770679808969233036707714044721150931912397984506953156869
Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/40.flash_ctrl_disable/latest/run.log

  UVM_ERROR @ 75852.2 ns: (cip_base_scoreboard.sv:455) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_core_reg_block, TL item: req: (cip_tl_seq_item@80132) { a_addr: 'h63781b0  a_data: 'h545f32ab  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h8b  a_opcode: 'h0  a_user: 'h26d8f  d_param: 'h0  d_source: 'h8b  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 75852.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---