Module Definition
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Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.u_rsp_intg_gen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.33 66.67 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.33 66.67 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.91 100.00 95.65 100.00 100.00 u_reg_if


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg_core.u_reg_if.u_rsp_intg_gen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.00 80.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.43 92.86 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.96 100.00 91.84 100.00 100.00 u_reg_if


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_data_intg.u_tlul_data_integ_enc 100.00 100.00



Module Instance : tb.dut.u_to_prog_fifo.u_rsp_gen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.67 83.33 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.67 83.33 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
84.25 100.00 66.67 84.62 85.71 u_to_prog_fifo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_to_rd_fifo.u_rsp_gen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.67 83.33 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.67 83.33 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.86 100.00 79.13 96.30 100.00 u_to_rd_fifo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg_core.u_rsp_intg_gen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.86 100.00 99.43 100.00 100.00 u_reg_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_rsp_intg.u_rsp_gen 100.00 100.00



Module Instance : tb.dut.u_reg_core.u_socket.gen_err_resp.err_resp.u_intg_gen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
57.80 76.92 40.91 55.56 gen_err_resp.err_resp


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_data_intg.u_tlul_data_integ_enc 100.00 100.00
gen_rsp_intg.u_rsp_gen 100.00 100.00



Module Instance : tb.dut.u_prog_tl_gate.u_tlul_err_resp.u_intg_gen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.48 100.00 95.45 100.00 u_tlul_err_resp


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_data_intg.u_tlul_data_integ_enc 100.00 100.00
gen_rsp_intg.u_rsp_gen 100.00 100.00



Module Instance : tb.dut.u_tl_gate.u_tlul_err_resp.u_intg_gen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
87.21 100.00 72.73 88.89 u_tlul_err_resp


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_data_intg.u_tlul_data_integ_enc 100.00 100.00
gen_rsp_intg.u_rsp_gen 100.00 100.00



Module Instance : tb.dut.u_tl_adapter_eflash.u_rsp_gen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.98 100.00 83.62 96.30 100.00 u_tl_adapter_eflash


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_rsp_intg.u_rsp_gen 100.00 100.00



Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_rsp_intg_gen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg_top


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_data_intg.u_tlul_data_integ_enc 100.00 100.00
gen_rsp_intg.u_rsp_gen 100.00 100.00

Line Coverage for Module : tlul_rsp_intg_gen ( parameter EnableRspIntgGen=1,EnableDataIntgGen=0 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_rsp_intg_gen

SCORELINE
100.00 100.00
tb.dut.u_tl_adapter_eflash.u_rsp_gen

Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN2511100.00
CONT_ASSIGN4311100.00
ALWAYS4733100.00
CONT_ASSIGN5311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
43 1 1
47 1 1
48 1 1
49 1 1
53 1 1


Line Coverage for Module : tlul_rsp_intg_gen ( parameter EnableRspIntgGen=0,EnableDataIntgGen=1 )
Line Coverage for Module self-instances :
SCORELINE
90.00 80.00
tb.dut.u_reg_core.u_reg_if.u_rsp_intg_gen

Line No.TotalCoveredPercent
TOTAL5480.00
CONT_ASSIGN32100.00
ALWAYS4733100.00
CONT_ASSIGN5311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
32 0 1
47 1 1
48 1 1
49 1 1
53 1 1


Line Coverage for Module : tlul_rsp_intg_gen ( parameter EnableRspIntgGen=1,EnableDataIntgGen=1 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_socket.gen_err_resp.err_resp.u_intg_gen

SCORELINE
100.00 100.00
tb.dut.u_prog_tl_gate.u_tlul_err_resp.u_intg_gen

SCORELINE
100.00 100.00
tb.dut.u_tl_gate.u_tlul_err_resp.u_intg_gen

SCORELINE
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_rsp_intg_gen

Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2511100.00
ALWAYS4733100.00
CONT_ASSIGN5311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
47 1 1
48 1 1
49 1 1
53 1 1


Line Coverage for Module : tlul_rsp_intg_gen ( parameter EnableRspIntgGen=0,EnableDataIntgGen=0 )
Line Coverage for Module self-instances :
SCORELINE
91.67 83.33
tb.dut.u_to_prog_fifo.u_rsp_gen

SCORELINE
91.67 83.33
tb.dut.u_to_rd_fifo.u_rsp_gen

SCORELINE
83.33 66.67
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.u_rsp_intg_gen

Line No.TotalCoveredPercent
TOTAL6583.33
CONT_ASSIGN32100.00
CONT_ASSIGN4311100.00
ALWAYS4733100.00
CONT_ASSIGN5311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
32 0 1
43 1 1
47 1 1
48 1 1
49 1 1
53 1 1


Assert Coverage for Module : tlul_rsp_intg_gen
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataWidthCheck_A 11555 11555 0 0
PayLoadWidthCheck 11555 11555 0 0


DataWidthCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11555 11555 0 0
T1 5 5 0 0
T2 5 5 0 0
T3 5 5 0 0
T4 5 5 0 0
T5 5 5 0 0
T6 5 5 0 0
T8 5 5 0 0
T10 5 5 0 0
T16 5 5 0 0
T20 5 5 0 0
T21 5 5 0 0
T48 5 5 0 0
T49 5 5 0 0
T51 5 5 0 0
T52 5 5 0 0
T53 5 5 0 0
T54 5 5 0 0
T55 5 5 0 0
T56 5 5 0 0
T57 5 5 0 0

PayLoadWidthCheck
NameAttemptsReal SuccessesFailuresIncomplete
Total 11555 11555 0 0
T1 5 5 0 0
T2 5 5 0 0
T3 5 5 0 0
T4 5 5 0 0
T5 5 5 0 0
T6 5 5 0 0
T8 5 5 0 0
T10 5 5 0 0
T16 5 5 0 0
T20 5 5 0 0
T21 5 5 0 0
T48 5 5 0 0
T49 5 5 0 0
T51 5 5 0 0
T52 5 5 0 0
T53 5 5 0 0
T54 5 5 0 0
T55 5 5 0 0
T56 5 5 0 0
T57 5 5 0 0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.u_rsp_intg_gen
Line No.TotalCoveredPercent
TOTAL6466.67
CONT_ASSIGN32100.00
CONT_ASSIGN43100.00
ALWAYS4733100.00
CONT_ASSIGN5311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
32 0 1
43 0 1
47 1 1
48 1 1
49 1 1
53 1 1


Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.u_rsp_intg_gen
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataWidthCheck_A 1259 1259 0 0
PayLoadWidthCheck 1259 1259 0 0


DataWidthCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1259 1259 0 0
T16 1 1 0 0
T48 1 1 0 0
T49 1 1 0 0
T51 1 1 0 0
T52 1 1 0 0
T53 1 1 0 0
T54 1 1 0 0
T55 1 1 0 0
T56 1 1 0 0
T57 1 1 0 0

PayLoadWidthCheck
NameAttemptsReal SuccessesFailuresIncomplete
Total 1259 1259 0 0
T16 1 1 0 0
T48 1 1 0 0
T49 1 1 0 0
T51 1 1 0 0
T52 1 1 0 0
T53 1 1 0 0
T54 1 1 0 0
T55 1 1 0 0
T56 1 1 0 0
T57 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_reg_if.u_rsp_intg_gen
Line No.TotalCoveredPercent
TOTAL5480.00
CONT_ASSIGN32100.00
ALWAYS4733100.00
CONT_ASSIGN5311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
32 0 1
47 1 1
48 1 1
49 1 1
53 1 1


Assert Coverage for Instance : tb.dut.u_reg_core.u_reg_if.u_rsp_intg_gen
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataWidthCheck_A 1259 1259 0 0
PayLoadWidthCheck 1259 1259 0 0


DataWidthCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1259 1259 0 0
T16 1 1 0 0
T48 1 1 0 0
T49 1 1 0 0
T51 1 1 0 0
T52 1 1 0 0
T53 1 1 0 0
T54 1 1 0 0
T55 1 1 0 0
T56 1 1 0 0
T57 1 1 0 0

PayLoadWidthCheck
NameAttemptsReal SuccessesFailuresIncomplete
Total 1259 1259 0 0
T16 1 1 0 0
T48 1 1 0 0
T49 1 1 0 0
T51 1 1 0 0
T52 1 1 0 0
T53 1 1 0 0
T54 1 1 0 0
T55 1 1 0 0
T56 1 1 0 0
T57 1 1 0 0

Line Coverage for Instance : tb.dut.u_to_prog_fifo.u_rsp_gen
Line No.TotalCoveredPercent
TOTAL6583.33
CONT_ASSIGN32100.00
CONT_ASSIGN4311100.00
ALWAYS4733100.00
CONT_ASSIGN5311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
32 0 1
43 1 1
47 1 1
48 1 1
49 1 1
53 1 1


Assert Coverage for Instance : tb.dut.u_to_prog_fifo.u_rsp_gen
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataWidthCheck_A 1052 1052 0 0
PayLoadWidthCheck 1052 1052 0 0


DataWidthCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1052 1052 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T10 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0

PayLoadWidthCheck
NameAttemptsReal SuccessesFailuresIncomplete
Total 1052 1052 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T10 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0

Line Coverage for Instance : tb.dut.u_to_rd_fifo.u_rsp_gen
Line No.TotalCoveredPercent
TOTAL6583.33
CONT_ASSIGN32100.00
CONT_ASSIGN4311100.00
ALWAYS4733100.00
CONT_ASSIGN5311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
32 0 1
43 1 1
47 1 1
48 1 1
49 1 1
53 1 1


Assert Coverage for Instance : tb.dut.u_to_rd_fifo.u_rsp_gen
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataWidthCheck_A 1052 1052 0 0
PayLoadWidthCheck 1052 1052 0 0


DataWidthCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1052 1052 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T10 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0

PayLoadWidthCheck
NameAttemptsReal SuccessesFailuresIncomplete
Total 1052 1052 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T10 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_rsp_intg_gen
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN2511100.00
CONT_ASSIGN4311100.00
ALWAYS4733100.00
CONT_ASSIGN5311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
43 1 1
47 1 1
48 1 1
49 1 1
53 1 1


Assert Coverage for Instance : tb.dut.u_reg_core.u_rsp_intg_gen
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataWidthCheck_A 1259 1259 0 0
PayLoadWidthCheck 1259 1259 0 0


DataWidthCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1259 1259 0 0
T16 1 1 0 0
T48 1 1 0 0
T49 1 1 0 0
T51 1 1 0 0
T52 1 1 0 0
T53 1 1 0 0
T54 1 1 0 0
T55 1 1 0 0
T56 1 1 0 0
T57 1 1 0 0

PayLoadWidthCheck
NameAttemptsReal SuccessesFailuresIncomplete
Total 1259 1259 0 0
T16 1 1 0 0
T48 1 1 0 0
T49 1 1 0 0
T51 1 1 0 0
T52 1 1 0 0
T53 1 1 0 0
T54 1 1 0 0
T55 1 1 0 0
T56 1 1 0 0
T57 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_err_resp.err_resp.u_intg_gen
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2511100.00
ALWAYS4733100.00
CONT_ASSIGN5311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
47 1 1
48 1 1
49 1 1
53 1 1


Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_err_resp.err_resp.u_intg_gen
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataWidthCheck_A 1259 1259 0 0
PayLoadWidthCheck 1259 1259 0 0


DataWidthCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1259 1259 0 0
T16 1 1 0 0
T48 1 1 0 0
T49 1 1 0 0
T51 1 1 0 0
T52 1 1 0 0
T53 1 1 0 0
T54 1 1 0 0
T55 1 1 0 0
T56 1 1 0 0
T57 1 1 0 0

PayLoadWidthCheck
NameAttemptsReal SuccessesFailuresIncomplete
Total 1259 1259 0 0
T16 1 1 0 0
T48 1 1 0 0
T49 1 1 0 0
T51 1 1 0 0
T52 1 1 0 0
T53 1 1 0 0
T54 1 1 0 0
T55 1 1 0 0
T56 1 1 0 0
T57 1 1 0 0

Line Coverage for Instance : tb.dut.u_prog_tl_gate.u_tlul_err_resp.u_intg_gen
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2511100.00
ALWAYS4733100.00
CONT_ASSIGN5311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
47 1 1
48 1 1
49 1 1
53 1 1


Assert Coverage for Instance : tb.dut.u_prog_tl_gate.u_tlul_err_resp.u_intg_gen
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataWidthCheck_A 1052 1052 0 0
PayLoadWidthCheck 1052 1052 0 0


DataWidthCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1052 1052 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T10 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0

PayLoadWidthCheck
NameAttemptsReal SuccessesFailuresIncomplete
Total 1052 1052 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T10 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0

Line Coverage for Instance : tb.dut.u_tl_gate.u_tlul_err_resp.u_intg_gen
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2511100.00
ALWAYS4733100.00
CONT_ASSIGN5311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
47 1 1
48 1 1
49 1 1
53 1 1


Assert Coverage for Instance : tb.dut.u_tl_gate.u_tlul_err_resp.u_intg_gen
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataWidthCheck_A 1052 1052 0 0
PayLoadWidthCheck 1052 1052 0 0


DataWidthCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1052 1052 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T10 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0

PayLoadWidthCheck
NameAttemptsReal SuccessesFailuresIncomplete
Total 1052 1052 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T10 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0

Line Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_rsp_gen
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN2511100.00
CONT_ASSIGN4311100.00
ALWAYS4733100.00
CONT_ASSIGN5311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
43 1 1
47 1 1
48 1 1
49 1 1
53 1 1


Assert Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_rsp_gen
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataWidthCheck_A 1052 1052 0 0
PayLoadWidthCheck 1052 1052 0 0


DataWidthCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1052 1052 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T10 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0

PayLoadWidthCheck
NameAttemptsReal SuccessesFailuresIncomplete
Total 1052 1052 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T10 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_rsp_intg_gen
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2511100.00
ALWAYS4733100.00
CONT_ASSIGN5311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
47 1 1
48 1 1
49 1 1
53 1 1


Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_rsp_intg_gen
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataWidthCheck_A 1259 1259 0 0
PayLoadWidthCheck 1259 1259 0 0


DataWidthCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1259 1259 0 0
T16 1 1 0 0
T48 1 1 0 0
T49 1 1 0 0
T51 1 1 0 0
T52 1 1 0 0
T53 1 1 0 0
T54 1 1 0 0
T55 1 1 0 0
T56 1 1 0 0
T57 1 1 0 0

PayLoadWidthCheck
NameAttemptsReal SuccessesFailuresIncomplete
Total 1259 1259 0 0
T16 1 1 0 0
T48 1 1 0 0
T49 1 1 0 0
T51 1 1 0 0
T52 1 1 0 0
T53 1 1 0 0
T54 1 1 0 0
T55 1 1 0 0
T56 1 1 0 0
T57 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%