Unified Coverage Report :: Module :: tlul_err_resp

Module : tlul_err_resp

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.48	100.00	95.45			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg_core.u_socket.gen_err_resp.err_resp	57.80	76.92	40.91			55.56
tb.dut.u_tl_gate.u_tlul_err_resp	87.21	100.00	72.73			88.89
tb.dut.u_prog_tl_gate.u_tlul_err_resp	98.48	100.00	95.45			100.00

---

Module Instance : tb.dut.u_reg_core.u_socket.gen_err_resp.err_resp

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
57.80	76.92	40.91			55.56

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
71.05	87.76	40.91			55.56	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.33	100.00	93.33			100.00	100.00	u_socket

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_intg_gen	100.00	100.00					100.00

---

Module Instance : tb.dut.u_tl_gate.u_tlul_err_resp

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.21	100.00	72.73			88.89

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.40	100.00	72.73			88.89	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
80.60	100.00	100.00		57.14	95.83	50.00	u_tl_gate

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_intg_gen	100.00	100.00					100.00

---

Module Instance : tb.dut.u_prog_tl_gate.u_tlul_err_resp

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.48	100.00	95.45			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.86	100.00	95.45			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
78.37	100.00	88.89		57.14	95.83	50.00	u_prog_tl_gate

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_intg_gen	100.00	100.00					100.00

Line Coverage for Module : tlul_err_resp

	Line No.	Total	Covered	Percent
TOTAL		26	26	100.00
ALWAYS	34	14	14	100.00
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	53	1	1	100.00
CONT_ASSIGN	55	1	1	100.00
CONT_ASSIGN	58	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
ALWAYS	64	5	5	100.00
CONT_ASSIGN	75	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv' or '../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
35	1	1
36	1	1
37	1	1
38	1	1
39	1	1
40	1	1
41	1	1
42	1	1
43	1	1
44	1	1
45	1	1
46	1	1
47	1	1
			MISSING_ELSE
51	1	1
52	1	1
53	1	1
55	1	1
58	1	1
59	1	1
64	1	1
65	1	1
66	1	1
67	1	1
69	1	1
75	1	1

---

Cond Coverage for Module : tlul_err_resp

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       40
 EXPRESSION (tl_h_i.a_valid && tl_h_o_int.a_ready)
             -------1------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T16,T48,T49
1	0	Not Covered
1	1	Covered	T6,T17,T18

 LINE       51
 EXPRESSION (((~err_rsp_pending)) & ( ~ (err_req_pending & ((~tl_h_i.d_ready))) ))
             ----------1---------   ----------------------2----------------------

-1-	-2-	Status	Tests
0	1	Covered	T18,T19
1	0	Covered	T17,T18,T19
1	1	Covered	T16,T48,T49

 LINE       51
 SUB-EXPRESSION (err_req_pending & ((~tl_h_i.d_ready)))
                 -------1-------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T16,T48,T49
1	0	Covered	T6,T17,T18
1	1	Covered	T17,T18,T19

 LINE       52
 EXPRESSION (err_req_pending | err_rsp_pending)
             -------1-------   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T16,T48,T49
0	1	Covered	T18,T19
1	0	Covered	T6,T17,T18

 LINE       59
 EXPRESSION ((err_opcode == Get) ? AccessAckData : AccessAck)
             ---------1---------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T16,T48,T49

 LINE       59
 SUB-EXPRESSION (err_opcode == Get)
                ---------1---------

-1-	Status	Tests
0	Covered	T16,T48,T49
1	Covered	T16,T48,T49

 LINE       66
 EXPRESSION ((err_req_pending || err_rsp_pending) && ((!tl_h_i.d_ready)))
             ------------------1-----------------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T16,T48,T49
1	0	Covered	T6,T17,T18
1	1	Covered	T18,T19

 LINE       66
 SUB-EXPRESSION (err_req_pending || err_rsp_pending)
                 -------1-------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T16,T48,T49
0	1	Covered	T18,T19
1	0	Covered	T6,T17,T18

---

Branch Coverage for Module : tlul_err_resp

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	59	2	2	100.00
IF	34	4	4	100.00
IF	64	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv' or '../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	59	((err_opcode == Get)) ? 

Branches:

-1-	Status	Tests
1	Covered	T16,T48,T49
0	Covered	T17,T18,T19

	LineNo.	Expression
-1-:	34	if ((!rst_ni))
-2-:	40	if ((tl_h_i.a_valid && tl_h_o_int.a_ready))
-3-:	46	if ((!err_rsp_pending))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T16,T48,T49
0	1	-	Covered	T6,T17,T18
0	0	1	Covered	T16,T48,T49
0	0	0	Covered	T18,T19,T14

	LineNo.	Expression
-1-:	64	if ((!rst_ni))
-2-:	66	if (((err_req_pending || err_rsp_pending) && (!tl_h_i.d_ready)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T16,T48,T49
0	1	Covered	T18,T19,T14
0	0	Covered	T16,T48,T49

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_err_resp.err_resp

	Line No.	Total	Covered	Percent
TOTAL		26	20	76.92
ALWAYS	34	14	9	64.29
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	53	1	1	100.00
CONT_ASSIGN	55	1	1	100.00
CONT_ASSIGN	58	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
ALWAYS	64	5	4	80.00
CONT_ASSIGN	75	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv' or '../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
35	1	1
36	1	1
37	1	1
38	1	1
39	1	1
40	1	1
41	0	1
42	0	1
43	0	1
44	0	1
45	0	1
46	1	1
47	1	1
			==> MISSING_ELSE
51	1	1
52	1	1
53	1	1
55	1	1
58	1	1
59	1	1
64	1	1
65	1	1
66	1	1
67	0	1
69	1	1
75	1	1

---

Cond Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_err_resp.err_resp

	Total	Covered	Percent
Conditions	22	9	40.91
Logical	22	9	40.91
Non-Logical	0	0
Event	0	0

 LINE       40
 EXPRESSION (tl_h_i.a_valid && tl_h_o_int.a_ready)
             -------1------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T16,T48,T49
1	0	Not Covered
1	1	Not Covered

 LINE       51
 EXPRESSION (((~err_rsp_pending)) & ( ~ (err_req_pending & ((~tl_h_i.d_ready))) ))
             ----------1---------   ----------------------2----------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T16,T48,T49

 LINE       51
 SUB-EXPRESSION (err_req_pending & ((~tl_h_i.d_ready)))
                 -------1-------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T16,T48,T49
1	0	Not Covered
1	1	Not Covered

 LINE       52
 EXPRESSION (err_req_pending | err_rsp_pending)
             -------1-------   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T16,T48,T49
0	1	Not Covered
1	0	Not Covered

 LINE       59
 EXPRESSION ((err_opcode == Get) ? AccessAckData : AccessAck)
             ---------1---------

-1-	Status	Tests
0	Not Covered
1	Covered	T16,T48,T49

 LINE       59
 SUB-EXPRESSION (err_opcode == Get)
                ---------1---------

-1-	Status	Tests
0	Covered	T16,T48,T49
1	Covered	T16,T48,T49

 LINE       66
 EXPRESSION ((err_req_pending || err_rsp_pending) && ((!tl_h_i.d_ready)))
             ------------------1-----------------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T16,T48,T49
1	0	Not Covered
1	1	Not Covered

 LINE       66
 SUB-EXPRESSION (err_req_pending || err_rsp_pending)
                 -------1-------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T16,T48,T49
0	1	Not Covered
1	0	Not Covered

---

Branch Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_err_resp.err_resp

	Line No.	Total	Covered	Percent
Branches		9	5	55.56
TERNARY	59	2	1	50.00
IF	34	4	2	50.00
IF	64	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv' or '../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	59	((err_opcode == Get)) ? 

Branches:

-1-	Status	Tests
1	Covered	T16,T48,T49
0	Not Covered

	LineNo.	Expression
-1-:	34	if ((!rst_ni))
-2-:	40	if ((tl_h_i.a_valid && tl_h_o_int.a_ready))
-3-:	46	if ((!err_rsp_pending))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T16,T48,T49
0	1	-	Not Covered
0	0	1	Covered	T16,T48,T49
0	0	0	Not Covered

	LineNo.	Expression
-1-:	64	if ((!rst_ni))
-2-:	66	if (((err_req_pending || err_rsp_pending) && (!tl_h_i.d_ready)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T16,T48,T49
0	1	Not Covered
0	0	Covered	T16,T48,T49

Line Coverage for Instance : tb.dut.u_tl_gate.u_tlul_err_resp

	Line No.	Total	Covered	Percent
TOTAL		26	26	100.00
ALWAYS	34	14	14	100.00
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	53	1	1	100.00
CONT_ASSIGN	55	1	1	100.00
CONT_ASSIGN	58	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
ALWAYS	64	5	5	100.00
CONT_ASSIGN	75	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv' or '../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
35	1	1
36	1	1
37	1	1
38	1	1
39	1	1
40	1	1
41	1	1
42	1	1
43	1	1
44	1	1
45	1	1
46	1	1
47	1	1
			MISSING_ELSE
51	1	1
52	1	1
53	1	1
55	1	1
58	1	1
59	1	1
64	1	1
65	1	1
66	1	1
67	1	1
69	1	1
75	1	1

---

Cond Coverage for Instance : tb.dut.u_tl_gate.u_tlul_err_resp

	Total	Covered	Percent
Conditions	22	16	72.73
Logical	22	16	72.73
Non-Logical	0	0
Event	0	0

 LINE       40
 EXPRESSION (tl_h_i.a_valid && tl_h_o_int.a_ready)
             -------1------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T6,T174,T175

 LINE       51
 EXPRESSION (((~err_rsp_pending)) & ( ~ (err_req_pending & ((~tl_h_i.d_ready))) ))
             ----------1---------   ----------------------2----------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T80,T238,T239
1	1	Covered	T1,T2,T3

 LINE       51
 SUB-EXPRESSION (err_req_pending & ((~tl_h_i.d_ready)))
                 -------1-------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T174,T175
1	1	Covered	T80,T238,T239

 LINE       52
 EXPRESSION (err_req_pending | err_rsp_pending)
             -------1-------   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T6,T174,T175

 LINE       59
 EXPRESSION ((err_opcode == Get) ? AccessAckData : AccessAck)
             ---------1---------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       59
 SUB-EXPRESSION (err_opcode == Get)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION ((err_req_pending || err_rsp_pending) && ((!tl_h_i.d_ready)))
             ------------------1-----------------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T174,T175
1	1	Not Covered

 LINE       66
 SUB-EXPRESSION (err_req_pending || err_rsp_pending)
                 -------1-------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T6,T174,T175

---

Branch Coverage for Instance : tb.dut.u_tl_gate.u_tlul_err_resp

	Line No.	Total	Covered	Percent
Branches		9	8	88.89
TERNARY	59	2	1	50.00
IF	34	4	4	100.00
IF	64	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv' or '../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	59	((err_opcode == Get)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	34	if ((!rst_ni))
-2-:	40	if ((tl_h_i.a_valid && tl_h_o_int.a_ready))
-3-:	46	if ((!err_rsp_pending))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T6,T174,T175
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T14,T15

	LineNo.	Expression
-1-:	64	if ((!rst_ni))
-2-:	66	if (((err_req_pending || err_rsp_pending) && (!tl_h_i.d_ready)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T14,T15
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_prog_tl_gate.u_tlul_err_resp

	Line No.	Total	Covered	Percent
TOTAL		26	26	100.00
ALWAYS	34	14	14	100.00
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	53	1	1	100.00
CONT_ASSIGN	55	1	1	100.00
CONT_ASSIGN	58	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
ALWAYS	64	5	5	100.00
CONT_ASSIGN	75	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv' or '../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
35	1	1
36	1	1
37	1	1
38	1	1
39	1	1
40	1	1
41	1	1
42	1	1
43	1	1
44	1	1
45	1	1
46	1	1
47	1	1
			MISSING_ELSE
51	1	1
52	1	1
53	1	1
55	1	1
58	1	1
59	1	1
64	1	1
65	1	1
66	1	1
67	1	1
69	1	1
75	1	1

---

Cond Coverage for Instance : tb.dut.u_prog_tl_gate.u_tlul_err_resp

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       40
 EXPRESSION (tl_h_i.a_valid && tl_h_o_int.a_ready)
             -------1------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T17,T18,T19

 LINE       51
 EXPRESSION (((~err_rsp_pending)) & ( ~ (err_req_pending & ((~tl_h_i.d_ready))) ))
             ----------1---------   ----------------------2----------------------

-1-	-2-	Status	Tests
0	1	Covered	T18,T19
1	0	Covered	T17,T18,T19
1	1	Covered	T1,T2,T3

 LINE       51
 SUB-EXPRESSION (err_req_pending & ((~tl_h_i.d_ready)))
                 -------1-------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T17,T18,T19
1	1	Covered	T17,T18,T19

 LINE       52
 EXPRESSION (err_req_pending | err_rsp_pending)
             -------1-------   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T18,T19
1	0	Covered	T17,T18,T19

 LINE       59
 EXPRESSION ((err_opcode == Get) ? AccessAckData : AccessAck)
             ---------1---------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T1,T2,T3

 LINE       59
 SUB-EXPRESSION (err_opcode == Get)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION ((err_req_pending || err_rsp_pending) && ((!tl_h_i.d_ready)))
             ------------------1-----------------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T17,T18,T19
1	1	Covered	T18,T19

 LINE       66
 SUB-EXPRESSION (err_req_pending || err_rsp_pending)
                 -------1-------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T18,T19
1	0	Covered	T17,T18,T19

---

Branch Coverage for Instance : tb.dut.u_prog_tl_gate.u_tlul_err_resp

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	59	2	2	100.00
IF	34	4	4	100.00
IF	64	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv' or '../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	59	((err_opcode == Get)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T17,T18,T19

	LineNo.	Expression
-1-:	34	if ((!rst_ni))
-2-:	40	if ((tl_h_i.a_valid && tl_h_o_int.a_ready))
-3-:	46	if ((!err_rsp_pending))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T17,T18,T19
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T18,T19,T14

	LineNo.	Expression
-1-:	64	if ((!rst_ni))
-2-:	66	if (((err_req_pending || err_rsp_pending) && (!tl_h_i.d_ready)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T18,T19,T14
0	0	Covered	T1,T2,T3