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Module Instance : tb.dut.u_to_rd_fifo.u_reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.77 100.00 73.08 90.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.88 100.00 73.08 94.44 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.86 100.00 79.13 96.30 100.00 u_to_rd_fifo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00


Module Instance : tb.dut.u_to_rd_fifo.u_sramreqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.81 100.00 69.23 90.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.92 100.00 69.23 94.44 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.86 100.00 79.13 96.30 100.00 u_to_rd_fifo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00


Module Instance : tb.dut.u_to_rd_fifo.u_rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.06 100.00 88.24 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.84 100.00 89.19 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.86 100.00 79.13 96.30 100.00 u_to_rd_fifo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_sw_rd_fifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.32 100.00 85.29 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.86 95.24 85.29 90.91 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.36 97.14 92.91 98.44 100.00 98.33 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 85.00 90.00 80.00

Go back
Module Instances:
tb.dut.u_to_rd_fifo.u_reqfifo
tb.dut.u_to_rd_fifo.u_sramreqfifo
tb.dut.u_to_rd_fifo.u_rspfifo
tb.dut.u_sw_rd_fifo
Line Coverage for Instance : tb.dut.u_to_rd_fifo.u_reqfifo
Line No.TotalCoveredPercent
TOTAL2222100.00
ALWAYS7044100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9811100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN15411100.00
ALWAYS15722100.00
CONT_ASSIGN17511100.00
CONT_ASSIGN17611100.00
CONT_ASSIGN18011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
70 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
92 1 1
93 1 1
98 1 1
99 1 1
100 1 1
145 1 1
146 1 1
154 1 1
157 1 1
158 1 1
MISSING_ELSE
175 1 1
176 1 1
180 1 1


Cond Coverage for Instance : tb.dut.u_to_rd_fifo.u_reqfifo
TotalCoveredPercent
Conditions261973.08
Logical261973.08
Non-Logical00
Event00

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (1'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T6

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value))))
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T4,T6

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT4,T23,T24
110Not Covered
111CoveredT1,T4,T6

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T4,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T4,T6

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T6

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T4,T6
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_to_rd_fifo.u_reqfifo
Line No.TotalCoveredPercent
Branches 10 9 90.00
TERNARY 88 3 2 66.67
TERNARY 180 2 2 100.00
IF 70 3 3 100.00
IF 157 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 88 (gen_normal_fifo.full) ? -2-: 88 ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T6
0 1 Covered T1,T2,T3
0 0 Not Covered


LineNo. Expression -1-: 180 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T4,T6


LineNo. Expression -1-: 70 if ((!rst_ni)) -2-: 72 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 157 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T4,T6
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_to_rd_fifo.u_reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 412561653 4141198 0 0
DepthKnown_A 412561653 411800696 0 0
RvalidKnown_A 412561653 411800696 0 0
WreadyKnown_A 412561653 411800696 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 412561653 4141198 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 4141198 0 0
T1 335387 7444 0 0
T2 400434 0 0 0
T3 3393 0 0 0
T4 48538 6144 0 0
T5 72914 1963 0 0
T6 1053 14 0 0
T7 0 265 0 0
T8 45438 5326 0 0
T9 0 93 0 0
T10 14232 236 0 0
T20 1100 0 0 0
T21 944 0 0 0
T23 0 16879 0 0
T25 0 4608 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 411800696 0 0
T1 335387 335288 0 0
T2 400434 400418 0 0
T3 3393 2800 0 0
T4 48538 48470 0 0
T5 72914 72815 0 0
T6 1053 986 0 0
T8 45438 45375 0 0
T10 14232 14125 0 0
T20 1100 1017 0 0
T21 944 894 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 411800696 0 0
T1 335387 335288 0 0
T2 400434 400418 0 0
T3 3393 2800 0 0
T4 48538 48470 0 0
T5 72914 72815 0 0
T6 1053 986 0 0
T8 45438 45375 0 0
T10 14232 14125 0 0
T20 1100 1017 0 0
T21 944 894 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 411800696 0 0
T1 335387 335288 0 0
T2 400434 400418 0 0
T3 3393 2800 0 0
T4 48538 48470 0 0
T5 72914 72815 0 0
T6 1053 986 0 0
T8 45438 45375 0 0
T10 14232 14125 0 0
T20 1100 1017 0 0
T21 944 894 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 4141198 0 0
T1 335387 7444 0 0
T2 400434 0 0 0
T3 3393 0 0 0
T4 48538 6144 0 0
T5 72914 1963 0 0
T6 1053 14 0 0
T7 0 265 0 0
T8 45438 5326 0 0
T9 0 93 0 0
T10 14232 236 0 0
T20 1100 0 0 0
T21 944 0 0 0
T23 0 16879 0 0
T25 0 4608 0 0

Line Coverage for Instance : tb.dut.u_to_rd_fifo.u_sramreqfifo
Line No.TotalCoveredPercent
TOTAL2222100.00
ALWAYS7044100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9811100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN15411100.00
ALWAYS15722100.00
CONT_ASSIGN17511100.00
CONT_ASSIGN17611100.00
CONT_ASSIGN18011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
70 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
92 1 1
93 1 1
98 1 1
99 1 1
100 1 1
145 1 1
146 1 1
154 1 1
157 1 1
158 1 1
MISSING_ELSE
175 1 1
176 1 1
180 1 1


Cond Coverage for Instance : tb.dut.u_to_rd_fifo.u_sramreqfifo
TotalCoveredPercent
Conditions261869.23
Logical261869.23
Non-Logical00
Event00

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (1'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T6

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value))))
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T4,T6

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111CoveredT1,T4,T6

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T4,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T4,T6

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T6

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T4,T6
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_to_rd_fifo.u_sramreqfifo
Line No.TotalCoveredPercent
Branches 10 9 90.00
TERNARY 88 3 2 66.67
TERNARY 180 2 2 100.00
IF 70 3 3 100.00
IF 157 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 88 (gen_normal_fifo.full) ? -2-: 88 ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T6
0 1 Covered T1,T2,T3
0 0 Not Covered


LineNo. Expression -1-: 180 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T4,T6


LineNo. Expression -1-: 70 if ((!rst_ni)) -2-: 72 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 157 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T4,T6
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_to_rd_fifo.u_sramreqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 412561653 2826141 0 0
DepthKnown_A 412561653 411800696 0 0
RvalidKnown_A 412561653 411800696 0 0
WreadyKnown_A 412561653 411800696 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 412561653 2826141 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 2826141 0 0
T1 335387 7444 0 0
T2 400434 0 0 0
T3 3393 0 0 0
T4 48538 6144 0 0
T5 72914 1963 0 0
T6 1053 14 0 0
T7 0 265 0 0
T8 45438 5326 0 0
T9 0 93 0 0
T10 14232 236 0 0
T20 1100 0 0 0
T21 944 0 0 0
T23 0 3752 0 0
T25 0 4608 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 411800696 0 0
T1 335387 335288 0 0
T2 400434 400418 0 0
T3 3393 2800 0 0
T4 48538 48470 0 0
T5 72914 72815 0 0
T6 1053 986 0 0
T8 45438 45375 0 0
T10 14232 14125 0 0
T20 1100 1017 0 0
T21 944 894 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 411800696 0 0
T1 335387 335288 0 0
T2 400434 400418 0 0
T3 3393 2800 0 0
T4 48538 48470 0 0
T5 72914 72815 0 0
T6 1053 986 0 0
T8 45438 45375 0 0
T10 14232 14125 0 0
T20 1100 1017 0 0
T21 944 894 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 411800696 0 0
T1 335387 335288 0 0
T2 400434 400418 0 0
T3 3393 2800 0 0
T4 48538 48470 0 0
T5 72914 72815 0 0
T6 1053 986 0 0
T8 45438 45375 0 0
T10 14232 14125 0 0
T20 1100 1017 0 0
T21 944 894 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 2826141 0 0
T1 335387 7444 0 0
T2 400434 0 0 0
T3 3393 0 0 0
T4 48538 6144 0 0
T5 72914 1963 0 0
T6 1053 14 0 0
T7 0 265 0 0
T8 45438 5326 0 0
T9 0 93 0 0
T10 14232 236 0 0
T20 1100 0 0 0
T21 944 0 0 0
T23 0 3752 0 0
T25 0 4608 0 0

Line Coverage for Instance : tb.dut.u_to_rd_fifo.u_rspfifo
Line No.TotalCoveredPercent
TOTAL2222100.00
ALWAYS7044100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9811100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN15411100.00
ALWAYS15722100.00
CONT_ASSIGN17211100.00
CONT_ASSIGN17311100.00
CONT_ASSIGN18011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
70 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
92 1 1
93 1 1
98 1 1
99 1 1
100 1 1
145 1 1
146 1 1
154 1 1
157 1 1
158 1 1
MISSING_ELSE
172 1 1
173 1 1
180 1 1


Cond Coverage for Instance : tb.dut.u_to_rd_fifo.u_rspfifo
TotalCoveredPercent
Conditions343088.24
Logical343088.24
Non-Logical00
Event00

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (1'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT23,T29,T30

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value))))
-1-StatusTests
0CoveredT17,T18
1CoveredT1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------
-1-StatusTests
0CoveredT17,T18
1CoveredT1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT17,T18
110Not Covered
111CoveredT1,T4,T6

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT4,T23,T24
110Not Covered
111CoveredT1,T4,T6

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT23,T29,T30
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T4,T6

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT23,T29,T30

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       172
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T6

 LINE       172
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01CoveredT17,T18
10CoveredT1,T2,T3
11CoveredT1,T4,T6

 LINE       173
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT23,T29,T30
10CoveredT1,T4,T6
11CoveredT1,T2,T3

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T4,T6
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_to_rd_fifo.u_rspfifo
Line No.TotalCoveredPercent
Branches 12 12 100.00
TERNARY 88 3 3 100.00
TERNARY 172 2 2 100.00
TERNARY 180 2 2 100.00
IF 70 3 3 100.00
IF 157 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 88 (gen_normal_fifo.full) ? -2-: 88 ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?

Branches:
-1--2-StatusTests
1 - Covered T23,T29,T30
0 1 Covered T1,T2,T3
0 0 Covered T17,T18


LineNo. Expression -1-: 172 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 180 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T4,T6


LineNo. Expression -1-: 70 if ((!rst_ni)) -2-: 72 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 157 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T4,T6
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_to_rd_fifo.u_rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 412353993 4130507 0 0
DepthKnown_A 412561653 411800696 0 0
RvalidKnown_A 412561653 411800696 0 0
WreadyKnown_A 412561653 411800696 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 412561653 4145720 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412353993 4130507 0 0
T1 335387 7444 0 0
T2 400434 0 0 0
T3 3393 0 0 0
T4 48538 6144 0 0
T5 72914 1963 0 0
T6 1053 14 0 0
T7 0 265 0 0
T8 45438 5326 0 0
T9 0 93 0 0
T10 14232 236 0 0
T20 1100 0 0 0
T21 944 0 0 0
T23 0 16879 0 0
T25 0 4608 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 411800696 0 0
T1 335387 335288 0 0
T2 400434 400418 0 0
T3 3393 2800 0 0
T4 48538 48470 0 0
T5 72914 72815 0 0
T6 1053 986 0 0
T8 45438 45375 0 0
T10 14232 14125 0 0
T20 1100 1017 0 0
T21 944 894 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 411800696 0 0
T1 335387 335288 0 0
T2 400434 400418 0 0
T3 3393 2800 0 0
T4 48538 48470 0 0
T5 72914 72815 0 0
T6 1053 986 0 0
T8 45438 45375 0 0
T10 14232 14125 0 0
T20 1100 1017 0 0
T21 944 894 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 411800696 0 0
T1 335387 335288 0 0
T2 400434 400418 0 0
T3 3393 2800 0 0
T4 48538 48470 0 0
T5 72914 72815 0 0
T6 1053 986 0 0
T8 45438 45375 0 0
T10 14232 14125 0 0
T20 1100 1017 0 0
T21 944 894 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 4145720 0 0
T1 335387 7444 0 0
T2 400434 0 0 0
T3 3393 0 0 0
T4 48538 6144 0 0
T5 72914 1963 0 0
T6 1053 14 0 0
T7 0 265 0 0
T8 45438 5326 0 0
T9 0 93 0 0
T10 14232 236 0 0
T20 1100 0 0 0
T21 944 0 0 0
T23 0 16879 0 0
T25 0 4608 0 0

Line Coverage for Instance : tb.dut.u_sw_rd_fifo
Line No.TotalCoveredPercent
TOTAL2222100.00
ALWAYS7044100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9811100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN16211100.00
ALWAYS16522100.00
CONT_ASSIGN17211100.00
CONT_ASSIGN17311100.00
CONT_ASSIGN18011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
70 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
92 1 1
93 1 1
98 1 1
99 1 1
100 1 1
145 1 1
146 1 1
162 1 1
165 1 1
166 1 1
MISSING_ELSE
172 1 1
173 1 1
180 1 1


Cond Coverage for Instance : tb.dut.u_sw_rd_fifo
TotalCoveredPercent
Conditions342985.29
Logical342985.29
Non-Logical00
Event00

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (5'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((5'(gen_normal_fifo.wptr_value) - 5'(gen_normal_fifo.rptr_value))) : (((5'(Depth) - 5'(gen_normal_fifo.rptr_value)) + 5'(gen_normal_fifo.wptr_value)))))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T25,T44

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((5'(gen_normal_fifo.wptr_value) - 5'(gen_normal_fifo.rptr_value))) : (((5'(Depth) - 5'(gen_normal_fifo.rptr_value)) + 5'(gen_normal_fifo.wptr_value))))
-1-StatusTests
0CoveredT1,T4,T10
1CoveredT1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------
-1-StatusTests
0CoveredT1,T4,T10
1CoveredT1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T4,T6

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T4,T6
110Not Covered
111CoveredT1,T4,T6

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT4,T25,T44
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T4,T6

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T25,T44

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       172
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T6

 LINE       172
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01CoveredT1,T4,T6
10CoveredT1,T2,T3
11CoveredT1,T4,T6

 LINE       173
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT1,T4,T6
10CoveredT1,T4,T6
11CoveredT1,T2,T3

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T4,T6
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_sw_rd_fifo
Line No.TotalCoveredPercent
Branches 12 12 100.00
TERNARY 88 3 3 100.00
TERNARY 172 2 2 100.00
TERNARY 180 2 2 100.00
IF 70 3 3 100.00
IF 157 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 88 (gen_normal_fifo.full) ? -2-: 88 ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?

Branches:
-1--2-StatusTests
1 - Covered T4,T25,T44
0 1 Covered T1,T2,T3
0 0 Covered T1,T4,T10


LineNo. Expression -1-: 172 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 180 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T4,T6


LineNo. Expression -1-: 70 if ((!rst_ni)) -2-: 72 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 157 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T4,T6
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_sw_rd_fifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 412561653 47073906 0 0
DepthKnown_A 412561653 411800696 0 0
RvalidKnown_A 412561653 411800696 0 0
WreadyKnown_A 412561653 411800696 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 412561653 47073906 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 47073906 0 0
T1 335387 27323 0 0
T2 400434 0 0 0
T3 3393 0 0 0
T4 48538 24589 0 0
T5 72914 8267 0 0
T6 1053 58 0 0
T7 0 1105 0 0
T8 45438 19102 0 0
T9 0 194 0 0
T10 14232 1005 0 0
T20 1100 0 0 0
T21 944 0 0 0
T23 0 77196 0 0
T25 0 64243 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 411800696 0 0
T1 335387 335288 0 0
T2 400434 400418 0 0
T3 3393 2800 0 0
T4 48538 48470 0 0
T5 72914 72815 0 0
T6 1053 986 0 0
T8 45438 45375 0 0
T10 14232 14125 0 0
T20 1100 1017 0 0
T21 944 894 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 411800696 0 0
T1 335387 335288 0 0
T2 400434 400418 0 0
T3 3393 2800 0 0
T4 48538 48470 0 0
T5 72914 72815 0 0
T6 1053 986 0 0
T8 45438 45375 0 0
T10 14232 14125 0 0
T20 1100 1017 0 0
T21 944 894 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 411800696 0 0
T1 335387 335288 0 0
T2 400434 400418 0 0
T3 3393 2800 0 0
T4 48538 48470 0 0
T5 72914 72815 0 0
T6 1053 986 0 0
T8 45438 45375 0 0
T10 14232 14125 0 0
T20 1100 1017 0 0
T21 944 894 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 412561653 47073906 0 0
T1 335387 27323 0 0
T2 400434 0 0 0
T3 3393 0 0 0
T4 48538 24589 0 0
T5 72914 8267 0 0
T6 1053 58 0 0
T7 0 1105 0 0
T8 45438 19102 0 0
T9 0 194 0 0
T10 14232 1005 0 0
T20 1100 0 0 0
T21 944 0 0 0
T23 0 77196 0 0
T25 0 64243 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%