SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_seed_hw_rd_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_flash_hw_if.u_sync_rma_req | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_prog_tl_gate.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_escalation_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tl_gate.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_eflash.u_lc_nvm_debug_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
52.96 | 52.96 | u_region_cfg |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
52.96 | 52.96 | u_region_cfg |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
52.96 | 52.96 | u_region_cfg |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
52.96 | 52.96 | u_region_cfg |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
97.36 | 97.14 | 92.91 | 98.44 | 100.00 | 98.33 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.75 | 100.00 | 92.71 | 92.11 | 98.94 | 100.00 | u_flash_hw_if |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
78.37 | 100.00 | 88.89 | 57.14 | 95.83 | 50.00 | u_prog_tl_gate |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
97.36 | 97.14 | 92.91 | 98.44 | 100.00 | 98.33 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
80.60 | 100.00 | 100.00 | 57.14 | 95.83 | 50.00 | u_tl_gate |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
94.26 | 97.67 | 85.11 | 100.00 | u_eflash |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 10520 | 10520 | 0 | 0 |
OutputsKnown_A | 2147483647 | 2147483647 | 0 | 0 |
gen_flops.OutputDelay_A | 2147483647 | 2147483647 | 0 | 21849 |
gen_no_flops.OutputDelay_A | 812478224 | 810956310 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10520 | 10520 | 0 | 0 |
T1 | 10 | 10 | 0 | 0 |
T2 | 10 | 10 | 0 | 0 |
T3 | 10 | 10 | 0 | 0 |
T4 | 10 | 10 | 0 | 0 |
T5 | 10 | 10 | 0 | 0 |
T6 | 10 | 10 | 0 | 0 |
T8 | 10 | 10 | 0 | 0 |
T10 | 10 | 10 | 0 | 0 |
T20 | 10 | 10 | 0 | 0 |
T21 | 10 | 10 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2147483647 | 2147483647 | 0 | 0 |
T1 | 3353870 | 3352880 | 0 | 0 |
T2 | 4004340 | 4004180 | 0 | 0 |
T3 | 33930 | 28000 | 0 | 0 |
T4 | 3150 | 2470 | 0 | 0 |
T5 | 729140 | 728150 | 0 | 0 |
T6 | 9935 | 9265 | 0 | 0 |
T8 | 454380 | 453750 | 0 | 0 |
T10 | 142320 | 141250 | 0 | 0 |
T20 | 3960 | 3130 | 0 | 0 |
T21 | 3540 | 3040 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2147483647 | 2147483647 | 0 | 21849 |
T1 | 2683096 | 2682280 | 0 | 24 |
T2 | 3203472 | 3203336 | 0 | 24 |
T3 | 27144 | 22184 | 0 | 24 |
T4 | 2520 | 1976 | 0 | 0 |
T5 | 583312 | 582496 | 0 | 24 |
T6 | 7829 | 7272 | 0 | 21 |
T7 | 0 | 0 | 0 | 24 |
T8 | 363504 | 362976 | 0 | 24 |
T10 | 113856 | 112952 | 0 | 24 |
T20 | 3168 | 2504 | 0 | 0 |
T21 | 2832 | 2432 | 0 | 0 |
T34 | 0 | 0 | 0 | 24 |
T35 | 0 | 0 | 0 | 24 |
T84 | 0 | 0 | 0 | 3 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 812478224 | 810956310 | 0 | 0 |
T1 | 670774 | 670576 | 0 | 0 |
T2 | 800868 | 800836 | 0 | 0 |
T3 | 6786 | 5600 | 0 | 0 |
T4 | 630 | 494 | 0 | 0 |
T5 | 145828 | 145630 | 0 | 0 |
T6 | 2106 | 1972 | 0 | 0 |
T8 | 90876 | 90750 | 0 | 0 |
T10 | 28464 | 28250 | 0 | 0 |
T20 | 792 | 626 | 0 | 0 |
T21 | 708 | 608 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1052 | 1052 | 0 | 0 |
OutputsKnown_A | 406239188 | 405478231 | 0 | 0 |
gen_flops.OutputDelay_A | 406239188 | 405448288 | 0 | 2748 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1052 | 1052 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 406239188 | 405478231 | 0 | 0 |
T1 | 335387 | 335288 | 0 | 0 |
T2 | 400434 | 400418 | 0 | 0 |
T3 | 3393 | 2800 | 0 | 0 |
T4 | 315 | 247 | 0 | 0 |
T5 | 72914 | 72815 | 0 | 0 |
T6 | 1053 | 986 | 0 | 0 |
T8 | 45438 | 45375 | 0 | 0 |
T10 | 14232 | 14125 | 0 | 0 |
T20 | 396 | 313 | 0 | 0 |
T21 | 354 | 304 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 406239188 | 405448288 | 0 | 2748 |
T1 | 335387 | 335285 | 0 | 3 |
T2 | 400434 | 400417 | 0 | 3 |
T3 | 3393 | 2773 | 0 | 3 |
T4 | 315 | 247 | 0 | 0 |
T5 | 72914 | 72812 | 0 | 3 |
T6 | 1053 | 983 | 0 | 3 |
T7 | 0 | 0 | 0 | 3 |
T8 | 45438 | 45372 | 0 | 3 |
T10 | 14232 | 14119 | 0 | 3 |
T20 | 396 | 313 | 0 | 0 |
T21 | 354 | 304 | 0 | 0 |
T34 | 0 | 0 | 0 | 3 |
T35 | 0 | 0 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1052 | 1052 | 0 | 0 |
OutputsKnown_A | 406239188 | 405478231 | 0 | 0 |
gen_flops.OutputDelay_A | 406239188 | 405448288 | 0 | 2748 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1052 | 1052 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 406239188 | 405478231 | 0 | 0 |
T1 | 335387 | 335288 | 0 | 0 |
T2 | 400434 | 400418 | 0 | 0 |
T3 | 3393 | 2800 | 0 | 0 |
T4 | 315 | 247 | 0 | 0 |
T5 | 72914 | 72815 | 0 | 0 |
T6 | 1053 | 986 | 0 | 0 |
T8 | 45438 | 45375 | 0 | 0 |
T10 | 14232 | 14125 | 0 | 0 |
T20 | 396 | 313 | 0 | 0 |
T21 | 354 | 304 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 406239188 | 405448288 | 0 | 2748 |
T1 | 335387 | 335285 | 0 | 3 |
T2 | 400434 | 400417 | 0 | 3 |
T3 | 3393 | 2773 | 0 | 3 |
T4 | 315 | 247 | 0 | 0 |
T5 | 72914 | 72812 | 0 | 3 |
T6 | 1053 | 983 | 0 | 3 |
T7 | 0 | 0 | 0 | 3 |
T8 | 45438 | 45372 | 0 | 3 |
T10 | 14232 | 14119 | 0 | 3 |
T20 | 396 | 313 | 0 | 0 |
T21 | 354 | 304 | 0 | 0 |
T34 | 0 | 0 | 0 | 3 |
T35 | 0 | 0 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1052 | 1052 | 0 | 0 |
OutputsKnown_A | 406239188 | 405478231 | 0 | 0 |
gen_flops.OutputDelay_A | 406239188 | 405448288 | 0 | 2748 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1052 | 1052 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 406239188 | 405478231 | 0 | 0 |
T1 | 335387 | 335288 | 0 | 0 |
T2 | 400434 | 400418 | 0 | 0 |
T3 | 3393 | 2800 | 0 | 0 |
T4 | 315 | 247 | 0 | 0 |
T5 | 72914 | 72815 | 0 | 0 |
T6 | 1053 | 986 | 0 | 0 |
T8 | 45438 | 45375 | 0 | 0 |
T10 | 14232 | 14125 | 0 | 0 |
T20 | 396 | 313 | 0 | 0 |
T21 | 354 | 304 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 406239188 | 405448288 | 0 | 2748 |
T1 | 335387 | 335285 | 0 | 3 |
T2 | 400434 | 400417 | 0 | 3 |
T3 | 3393 | 2773 | 0 | 3 |
T4 | 315 | 247 | 0 | 0 |
T5 | 72914 | 72812 | 0 | 3 |
T6 | 1053 | 983 | 0 | 3 |
T7 | 0 | 0 | 0 | 3 |
T8 | 45438 | 45372 | 0 | 3 |
T10 | 14232 | 14119 | 0 | 3 |
T20 | 396 | 313 | 0 | 0 |
T21 | 354 | 304 | 0 | 0 |
T34 | 0 | 0 | 0 | 3 |
T35 | 0 | 0 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1052 | 1052 | 0 | 0 |
OutputsKnown_A | 406239188 | 405478231 | 0 | 0 |
gen_flops.OutputDelay_A | 406239188 | 405448288 | 0 | 2748 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1052 | 1052 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 406239188 | 405478231 | 0 | 0 |
T1 | 335387 | 335288 | 0 | 0 |
T2 | 400434 | 400418 | 0 | 0 |
T3 | 3393 | 2800 | 0 | 0 |
T4 | 315 | 247 | 0 | 0 |
T5 | 72914 | 72815 | 0 | 0 |
T6 | 1053 | 986 | 0 | 0 |
T8 | 45438 | 45375 | 0 | 0 |
T10 | 14232 | 14125 | 0 | 0 |
T20 | 396 | 313 | 0 | 0 |
T21 | 354 | 304 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 406239188 | 405448288 | 0 | 2748 |
T1 | 335387 | 335285 | 0 | 3 |
T2 | 400434 | 400417 | 0 | 3 |
T3 | 3393 | 2773 | 0 | 3 |
T4 | 315 | 247 | 0 | 0 |
T5 | 72914 | 72812 | 0 | 3 |
T6 | 1053 | 983 | 0 | 3 |
T7 | 0 | 0 | 0 | 3 |
T8 | 45438 | 45372 | 0 | 3 |
T10 | 14232 | 14119 | 0 | 3 |
T20 | 396 | 313 | 0 | 0 |
T21 | 354 | 304 | 0 | 0 |
T34 | 0 | 0 | 0 | 3 |
T35 | 0 | 0 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1052 | 1052 | 0 | 0 |
OutputsKnown_A | 406239188 | 405478231 | 0 | 0 |
gen_flops.OutputDelay_A | 406239188 | 405448288 | 0 | 2748 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1052 | 1052 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 406239188 | 405478231 | 0 | 0 |
T1 | 335387 | 335288 | 0 | 0 |
T2 | 400434 | 400418 | 0 | 0 |
T3 | 3393 | 2800 | 0 | 0 |
T4 | 315 | 247 | 0 | 0 |
T5 | 72914 | 72815 | 0 | 0 |
T6 | 1053 | 986 | 0 | 0 |
T8 | 45438 | 45375 | 0 | 0 |
T10 | 14232 | 14125 | 0 | 0 |
T20 | 396 | 313 | 0 | 0 |
T21 | 354 | 304 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 406239188 | 405448288 | 0 | 2748 |
T1 | 335387 | 335285 | 0 | 3 |
T2 | 400434 | 400417 | 0 | 3 |
T3 | 3393 | 2773 | 0 | 3 |
T4 | 315 | 247 | 0 | 0 |
T5 | 72914 | 72812 | 0 | 3 |
T6 | 1053 | 983 | 0 | 3 |
T7 | 0 | 0 | 0 | 3 |
T8 | 45438 | 45372 | 0 | 3 |
T10 | 14232 | 14119 | 0 | 3 |
T20 | 396 | 313 | 0 | 0 |
T21 | 354 | 304 | 0 | 0 |
T34 | 0 | 0 | 0 | 3 |
T35 | 0 | 0 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1052 | 1052 | 0 | 0 |
OutputsKnown_A | 406239188 | 405478231 | 0 | 0 |
gen_flops.OutputDelay_A | 406239188 | 405448288 | 0 | 2748 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1052 | 1052 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 406239188 | 405478231 | 0 | 0 |
T1 | 335387 | 335288 | 0 | 0 |
T2 | 400434 | 400418 | 0 | 0 |
T3 | 3393 | 2800 | 0 | 0 |
T4 | 315 | 247 | 0 | 0 |
T5 | 72914 | 72815 | 0 | 0 |
T6 | 1053 | 986 | 0 | 0 |
T8 | 45438 | 45375 | 0 | 0 |
T10 | 14232 | 14125 | 0 | 0 |
T20 | 396 | 313 | 0 | 0 |
T21 | 354 | 304 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 406239188 | 405448288 | 0 | 2748 |
T1 | 335387 | 335285 | 0 | 3 |
T2 | 400434 | 400417 | 0 | 3 |
T3 | 3393 | 2773 | 0 | 3 |
T4 | 315 | 247 | 0 | 0 |
T5 | 72914 | 72812 | 0 | 3 |
T6 | 1053 | 983 | 0 | 3 |
T7 | 0 | 0 | 0 | 3 |
T8 | 45438 | 45372 | 0 | 3 |
T10 | 14232 | 14119 | 0 | 3 |
T20 | 396 | 313 | 0 | 0 |
T21 | 354 | 304 | 0 | 0 |
T34 | 0 | 0 | 0 | 3 |
T35 | 0 | 0 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1052 | 1052 | 0 | 0 |
OutputsKnown_A | 406239112 | 405478155 | 0 | 0 |
gen_no_flops.OutputDelay_A | 406239112 | 405478155 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1052 | 1052 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 406239112 | 405478155 | 0 | 0 |
T1 | 335387 | 335288 | 0 | 0 |
T2 | 400434 | 400418 | 0 | 0 |
T3 | 3393 | 2800 | 0 | 0 |
T4 | 315 | 247 | 0 | 0 |
T5 | 72914 | 72815 | 0 | 0 |
T6 | 1053 | 986 | 0 | 0 |
T8 | 45438 | 45375 | 0 | 0 |
T10 | 14232 | 14125 | 0 | 0 |
T20 | 396 | 313 | 0 | 0 |
T21 | 354 | 304 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 406239112 | 405478155 | 0 | 0 |
T1 | 335387 | 335288 | 0 | 0 |
T2 | 400434 | 400418 | 0 | 0 |
T3 | 3393 | 2800 | 0 | 0 |
T4 | 315 | 247 | 0 | 0 |
T5 | 72914 | 72815 | 0 | 0 |
T6 | 1053 | 986 | 0 | 0 |
T8 | 45438 | 45375 | 0 | 0 |
T10 | 14232 | 14125 | 0 | 0 |
T20 | 396 | 313 | 0 | 0 |
T21 | 354 | 304 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1052 | 1052 | 0 | 0 |
OutputsKnown_A | 406219665 | 405458708 | 0 | 0 |
gen_flops.OutputDelay_A | 406219665 | 405428900 | 0 | 2613 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1052 | 1052 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 406219665 | 405458708 | 0 | 0 |
T1 | 335387 | 335288 | 0 | 0 |
T2 | 400434 | 400418 | 0 | 0 |
T3 | 3393 | 2800 | 0 | 0 |
T4 | 315 | 247 | 0 | 0 |
T5 | 72914 | 72815 | 0 | 0 |
T6 | 458 | 391 | 0 | 0 |
T8 | 45438 | 45375 | 0 | 0 |
T10 | 14232 | 14125 | 0 | 0 |
T20 | 396 | 313 | 0 | 0 |
T21 | 354 | 304 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 406219665 | 405428900 | 0 | 2613 |
T1 | 335387 | 335285 | 0 | 3 |
T2 | 400434 | 400417 | 0 | 3 |
T3 | 3393 | 2773 | 0 | 3 |
T4 | 315 | 247 | 0 | 0 |
T5 | 72914 | 72812 | 0 | 3 |
T6 | 458 | 391 | 0 | 0 |
T7 | 0 | 0 | 0 | 3 |
T8 | 45438 | 45372 | 0 | 3 |
T10 | 14232 | 14119 | 0 | 3 |
T20 | 396 | 313 | 0 | 0 |
T21 | 354 | 304 | 0 | 0 |
T34 | 0 | 0 | 0 | 3 |
T35 | 0 | 0 | 0 | 3 |
T84 | 0 | 0 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1052 | 1052 | 0 | 0 |
OutputsKnown_A | 406239112 | 405478155 | 0 | 0 |
gen_no_flops.OutputDelay_A | 406239112 | 405478155 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1052 | 1052 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 406239112 | 405478155 | 0 | 0 |
T1 | 335387 | 335288 | 0 | 0 |
T2 | 400434 | 400418 | 0 | 0 |
T3 | 3393 | 2800 | 0 | 0 |
T4 | 315 | 247 | 0 | 0 |
T5 | 72914 | 72815 | 0 | 0 |
T6 | 1053 | 986 | 0 | 0 |
T8 | 45438 | 45375 | 0 | 0 |
T10 | 14232 | 14125 | 0 | 0 |
T20 | 396 | 313 | 0 | 0 |
T21 | 354 | 304 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 406239112 | 405478155 | 0 | 0 |
T1 | 335387 | 335288 | 0 | 0 |
T2 | 400434 | 400418 | 0 | 0 |
T3 | 3393 | 2800 | 0 | 0 |
T4 | 315 | 247 | 0 | 0 |
T5 | 72914 | 72815 | 0 | 0 |
T6 | 1053 | 986 | 0 | 0 |
T8 | 45438 | 45375 | 0 | 0 |
T10 | 14232 | 14125 | 0 | 0 |
T20 | 396 | 313 | 0 | 0 |
T21 | 354 | 304 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1052 | 1052 | 0 | 0 |
OutputsKnown_A | 406239112 | 405478155 | 0 | 0 |
gen_flops.OutputDelay_A | 406239112 | 405448227 | 0 | 2748 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1052 | 1052 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 406239112 | 405478155 | 0 | 0 |
T1 | 335387 | 335288 | 0 | 0 |
T2 | 400434 | 400418 | 0 | 0 |
T3 | 3393 | 2800 | 0 | 0 |
T4 | 315 | 247 | 0 | 0 |
T5 | 72914 | 72815 | 0 | 0 |
T6 | 1053 | 986 | 0 | 0 |
T8 | 45438 | 45375 | 0 | 0 |
T10 | 14232 | 14125 | 0 | 0 |
T20 | 396 | 313 | 0 | 0 |
T21 | 354 | 304 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 406239112 | 405448227 | 0 | 2748 |
T1 | 335387 | 335285 | 0 | 3 |
T2 | 400434 | 400417 | 0 | 3 |
T3 | 3393 | 2773 | 0 | 3 |
T4 | 315 | 247 | 0 | 0 |
T5 | 72914 | 72812 | 0 | 3 |
T6 | 1053 | 983 | 0 | 3 |
T7 | 0 | 0 | 0 | 3 |
T8 | 45438 | 45372 | 0 | 3 |
T10 | 14232 | 14119 | 0 | 3 |
T20 | 396 | 313 | 0 | 0 |
T21 | 354 | 304 | 0 | 0 |
T34 | 0 | 0 | 0 | 3 |
T35 | 0 | 0 | 0 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |