Line Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
ALWAYS | 70 | 4 | 4 | 100.00 |
CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
CONT_ASSIGN | 87 | 1 | 1 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
ALWAYS | 165 | 2 | 2 | 100.00 |
CONT_ASSIGN | 175 | 1 | 1 | 100.00 |
CONT_ASSIGN | 176 | 1 | 1 | 100.00 |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
|
|
|
MISSING_ELSE |
84 |
1 |
1 |
85 |
1 |
1 |
86 |
1 |
1 |
87 |
1 |
1 |
88 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
98 |
1 |
1 |
99 |
1 |
1 |
100 |
1 |
1 |
145 |
1 |
1 |
146 |
1 |
1 |
162 |
1 |
1 |
165 |
1 |
1 |
166 |
1 |
1 |
|
|
|
MISSING_ELSE |
175 |
1 |
1 |
176 |
1 |
1 |
180 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_reqfifo
| Total | Covered | Percent |
Conditions | 26 | 21 | 80.77 |
Logical | 26 | 21 | 80.77 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 88
EXPRESSION
Number Term
1 gen_normal_fifo.full ? (2'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value)))))
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T4,T7,T8 |
LINE 88
SUB-EXPRESSION
Number Term
1 (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value))))
-1- | Status | Tests |
0 | Covered | T1,T4,T19 |
1 | Covered | T1,T2,T3 |
LINE 88
SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
---------------------------1--------------------------
-1- | Status | Tests |
0 | Covered | T1,T4,T19 |
1 | Covered | T1,T2,T3 |
LINE 92
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T4,T19 |
LINE 93
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T4,T19 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T4,T19 |
LINE 98
EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T7,T8 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T4,T19 |
LINE 145
EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
------------------------------------------------------1------------------------------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T4,T7,T8 |
LINE 146
EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
----------------------------1---------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 180
EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T4,T19 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_reqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
10 |
10 |
100.00 |
TERNARY |
88 |
3 |
3 |
100.00 |
TERNARY |
180 |
2 |
2 |
100.00 |
IF |
70 |
3 |
3 |
100.00 |
IF |
157 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 88 (gen_normal_fifo.full) ?
-2-: 88 ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T4,T7,T8 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T4,T19 |
LineNo. Expression
-1-: 180 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T4,T19 |
LineNo. Expression
-1-: 70 if ((!rst_ni))
-2-: 72 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 157 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T19 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
327083568 |
28426995 |
0 |
0 |
T1 |
9195 |
33 |
0 |
0 |
T2 |
3842 |
0 |
0 |
0 |
T3 |
163740 |
0 |
0 |
0 |
T4 |
317018 |
152368 |
0 |
0 |
T5 |
175018 |
0 |
0 |
0 |
T6 |
131369 |
0 |
0 |
0 |
T7 |
0 |
28591 |
0 |
0 |
T8 |
0 |
601349 |
0 |
0 |
T11 |
4051 |
0 |
0 |
0 |
T15 |
4471 |
0 |
0 |
0 |
T16 |
996 |
0 |
0 |
0 |
T17 |
45527 |
0 |
0 |
0 |
T18 |
0 |
2 |
0 |
0 |
T19 |
0 |
24 |
0 |
0 |
T44 |
0 |
29 |
0 |
0 |
T49 |
0 |
16 |
0 |
0 |
T50 |
0 |
16 |
0 |
0 |
T51 |
0 |
16 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
327083568 |
326368725 |
0 |
0 |
T1 |
9195 |
9038 |
0 |
0 |
T2 |
3842 |
3192 |
0 |
0 |
T3 |
163740 |
163662 |
0 |
0 |
T4 |
317018 |
316947 |
0 |
0 |
T5 |
175018 |
174954 |
0 |
0 |
T6 |
131369 |
106175 |
0 |
0 |
T11 |
4051 |
3349 |
0 |
0 |
T15 |
4471 |
4376 |
0 |
0 |
T16 |
996 |
912 |
0 |
0 |
T17 |
45527 |
45356 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
327083568 |
326368725 |
0 |
0 |
T1 |
9195 |
9038 |
0 |
0 |
T2 |
3842 |
3192 |
0 |
0 |
T3 |
163740 |
163662 |
0 |
0 |
T4 |
317018 |
316947 |
0 |
0 |
T5 |
175018 |
174954 |
0 |
0 |
T6 |
131369 |
106175 |
0 |
0 |
T11 |
4051 |
3349 |
0 |
0 |
T15 |
4471 |
4376 |
0 |
0 |
T16 |
996 |
912 |
0 |
0 |
T17 |
45527 |
45356 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
327083568 |
326368725 |
0 |
0 |
T1 |
9195 |
9038 |
0 |
0 |
T2 |
3842 |
3192 |
0 |
0 |
T3 |
163740 |
163662 |
0 |
0 |
T4 |
317018 |
316947 |
0 |
0 |
T5 |
175018 |
174954 |
0 |
0 |
T6 |
131369 |
106175 |
0 |
0 |
T11 |
4051 |
3349 |
0 |
0 |
T15 |
4471 |
4376 |
0 |
0 |
T16 |
996 |
912 |
0 |
0 |
T17 |
45527 |
45356 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
327083568 |
28426995 |
0 |
0 |
T1 |
9195 |
33 |
0 |
0 |
T2 |
3842 |
0 |
0 |
0 |
T3 |
163740 |
0 |
0 |
0 |
T4 |
317018 |
152368 |
0 |
0 |
T5 |
175018 |
0 |
0 |
0 |
T6 |
131369 |
0 |
0 |
0 |
T7 |
0 |
28591 |
0 |
0 |
T8 |
0 |
601349 |
0 |
0 |
T11 |
4051 |
0 |
0 |
0 |
T15 |
4471 |
0 |
0 |
0 |
T16 |
996 |
0 |
0 |
0 |
T17 |
45527 |
0 |
0 |
0 |
T18 |
0 |
2 |
0 |
0 |
T19 |
0 |
24 |
0 |
0 |
T44 |
0 |
29 |
0 |
0 |
T49 |
0 |
16 |
0 |
0 |
T50 |
0 |
16 |
0 |
0 |
T51 |
0 |
16 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_sramreqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
ALWAYS | 70 | 4 | 4 | 100.00 |
CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
CONT_ASSIGN | 87 | 1 | 1 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
ALWAYS | 165 | 2 | 2 | 100.00 |
CONT_ASSIGN | 175 | 1 | 1 | 100.00 |
CONT_ASSIGN | 176 | 1 | 1 | 100.00 |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
|
|
|
MISSING_ELSE |
84 |
1 |
1 |
85 |
1 |
1 |
86 |
1 |
1 |
87 |
1 |
1 |
88 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
98 |
1 |
1 |
99 |
1 |
1 |
100 |
1 |
1 |
145 |
1 |
1 |
146 |
1 |
1 |
162 |
1 |
1 |
165 |
1 |
1 |
166 |
1 |
1 |
|
|
|
MISSING_ELSE |
175 |
1 |
1 |
176 |
1 |
1 |
180 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_sramreqfifo
| Total | Covered | Percent |
Conditions | 26 | 21 | 80.77 |
Logical | 26 | 21 | 80.77 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 88
EXPRESSION
Number Term
1 gen_normal_fifo.full ? (2'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value)))))
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T4,T7,T8 |
LINE 88
SUB-EXPRESSION
Number Term
1 (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value))))
-1- | Status | Tests |
0 | Covered | T1,T4,T19 |
1 | Covered | T1,T2,T3 |
LINE 88
SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
---------------------------1--------------------------
-1- | Status | Tests |
0 | Covered | T1,T4,T19 |
1 | Covered | T1,T2,T3 |
LINE 92
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T4,T19 |
LINE 93
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T4,T19 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T4,T19 |
LINE 98
EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T7,T8 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T4,T19 |
LINE 145
EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
------------------------------------------------------1------------------------------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T4,T7,T8 |
LINE 146
EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
----------------------------1---------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 180
EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T4,T19 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_sramreqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
10 |
10 |
100.00 |
TERNARY |
88 |
3 |
3 |
100.00 |
TERNARY |
180 |
2 |
2 |
100.00 |
IF |
70 |
3 |
3 |
100.00 |
IF |
157 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 88 (gen_normal_fifo.full) ?
-2-: 88 ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T4,T7,T8 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T4,T19 |
LineNo. Expression
-1-: 180 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T4,T19 |
LineNo. Expression
-1-: 70 if ((!rst_ni))
-2-: 72 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 157 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T19 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_sramreqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
327083568 |
27638633 |
0 |
0 |
T1 |
9195 |
33 |
0 |
0 |
T2 |
3842 |
0 |
0 |
0 |
T3 |
163740 |
0 |
0 |
0 |
T4 |
317018 |
152368 |
0 |
0 |
T5 |
175018 |
0 |
0 |
0 |
T6 |
131369 |
0 |
0 |
0 |
T7 |
0 |
28591 |
0 |
0 |
T8 |
0 |
601349 |
0 |
0 |
T11 |
4051 |
0 |
0 |
0 |
T15 |
4471 |
0 |
0 |
0 |
T16 |
996 |
0 |
0 |
0 |
T17 |
45527 |
0 |
0 |
0 |
T18 |
0 |
2 |
0 |
0 |
T19 |
0 |
24 |
0 |
0 |
T44 |
0 |
29 |
0 |
0 |
T49 |
0 |
16 |
0 |
0 |
T50 |
0 |
16 |
0 |
0 |
T51 |
0 |
16 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
327083568 |
326368725 |
0 |
0 |
T1 |
9195 |
9038 |
0 |
0 |
T2 |
3842 |
3192 |
0 |
0 |
T3 |
163740 |
163662 |
0 |
0 |
T4 |
317018 |
316947 |
0 |
0 |
T5 |
175018 |
174954 |
0 |
0 |
T6 |
131369 |
106175 |
0 |
0 |
T11 |
4051 |
3349 |
0 |
0 |
T15 |
4471 |
4376 |
0 |
0 |
T16 |
996 |
912 |
0 |
0 |
T17 |
45527 |
45356 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
327083568 |
326368725 |
0 |
0 |
T1 |
9195 |
9038 |
0 |
0 |
T2 |
3842 |
3192 |
0 |
0 |
T3 |
163740 |
163662 |
0 |
0 |
T4 |
317018 |
316947 |
0 |
0 |
T5 |
175018 |
174954 |
0 |
0 |
T6 |
131369 |
106175 |
0 |
0 |
T11 |
4051 |
3349 |
0 |
0 |
T15 |
4471 |
4376 |
0 |
0 |
T16 |
996 |
912 |
0 |
0 |
T17 |
45527 |
45356 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
327083568 |
326368725 |
0 |
0 |
T1 |
9195 |
9038 |
0 |
0 |
T2 |
3842 |
3192 |
0 |
0 |
T3 |
163740 |
163662 |
0 |
0 |
T4 |
317018 |
316947 |
0 |
0 |
T5 |
175018 |
174954 |
0 |
0 |
T6 |
131369 |
106175 |
0 |
0 |
T11 |
4051 |
3349 |
0 |
0 |
T15 |
4471 |
4376 |
0 |
0 |
T16 |
996 |
912 |
0 |
0 |
T17 |
45527 |
45356 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
327083568 |
27638633 |
0 |
0 |
T1 |
9195 |
33 |
0 |
0 |
T2 |
3842 |
0 |
0 |
0 |
T3 |
163740 |
0 |
0 |
0 |
T4 |
317018 |
152368 |
0 |
0 |
T5 |
175018 |
0 |
0 |
0 |
T6 |
131369 |
0 |
0 |
0 |
T7 |
0 |
28591 |
0 |
0 |
T8 |
0 |
601349 |
0 |
0 |
T11 |
4051 |
0 |
0 |
0 |
T15 |
4471 |
0 |
0 |
0 |
T16 |
996 |
0 |
0 |
0 |
T17 |
45527 |
0 |
0 |
0 |
T18 |
0 |
2 |
0 |
0 |
T19 |
0 |
24 |
0 |
0 |
T44 |
0 |
29 |
0 |
0 |
T49 |
0 |
16 |
0 |
0 |
T50 |
0 |
16 |
0 |
0 |
T51 |
0 |
16 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
ALWAYS | 70 | 4 | 4 | 100.00 |
CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
CONT_ASSIGN | 87 | 1 | 1 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
ALWAYS | 165 | 2 | 2 | 100.00 |
CONT_ASSIGN | 172 | 1 | 1 | 100.00 |
CONT_ASSIGN | 173 | 1 | 1 | 100.00 |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
|
|
|
MISSING_ELSE |
84 |
1 |
1 |
85 |
1 |
1 |
86 |
1 |
1 |
87 |
1 |
1 |
88 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
98 |
1 |
1 |
99 |
1 |
1 |
100 |
1 |
1 |
145 |
1 |
1 |
146 |
1 |
1 |
162 |
1 |
1 |
165 |
1 |
1 |
166 |
1 |
1 |
|
|
|
MISSING_ELSE |
172 |
1 |
1 |
173 |
1 |
1 |
180 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_rspfifo
| Total | Covered | Percent |
Conditions | 34 | 29 | 85.29 |
Logical | 34 | 29 | 85.29 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 88
EXPRESSION
Number Term
1 gen_normal_fifo.full ? (2'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value)))))
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T42,T45 |
LINE 88
SUB-EXPRESSION
Number Term
1 (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value))))
-1- | Status | Tests |
0 | Covered | T54,T140,T42 |
1 | Covered | T1,T2,T3 |
LINE 88
SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
---------------------------1--------------------------
-1- | Status | Tests |
0 | Covered | T54,T140,T42 |
1 | Covered | T1,T2,T3 |
LINE 92
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T4,T19 |
LINE 93
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T8,T20,T21 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T4,T19 |
LINE 98
EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T42,T45 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T4,T19 |
LINE 145
EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
------------------------------------------------------1------------------------------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T42,T45 |
LINE 146
EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
----------------------------1---------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 172
EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
--------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T19 |
LINE 172
SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
-------------1------------ ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T42,T45 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T4,T19 |
LINE 173
EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
-------------1------------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T141,T54,T142 |
1 | 0 | Covered | T1,T4,T19 |
1 | 1 | Covered | T1,T2,T3 |
LINE 180
EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T4,T19 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_rspfifo
| Line No. | Total | Covered | Percent |
Branches |
|
12 |
12 |
100.00 |
TERNARY |
88 |
3 |
3 |
100.00 |
TERNARY |
172 |
2 |
2 |
100.00 |
TERNARY |
180 |
2 |
2 |
100.00 |
IF |
70 |
3 |
3 |
100.00 |
IF |
157 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 88 (gen_normal_fifo.full) ?
-2-: 88 ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T42,T45 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T54,T140,T42 |
LineNo. Expression
-1-: 172 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T19 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 180 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T4,T19 |
LineNo. Expression
-1-: 70 if ((!rst_ni))
-2-: 72 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 157 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T19 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
327083568 |
4293170 |
0 |
0 |
T1 |
9195 |
9 |
0 |
0 |
T2 |
3842 |
0 |
0 |
0 |
T3 |
163740 |
0 |
0 |
0 |
T4 |
317018 |
41291 |
0 |
0 |
T5 |
175018 |
0 |
0 |
0 |
T6 |
131369 |
0 |
0 |
0 |
T7 |
0 |
16709 |
0 |
0 |
T8 |
0 |
16749 |
0 |
0 |
T11 |
4051 |
0 |
0 |
0 |
T15 |
4471 |
0 |
0 |
0 |
T16 |
996 |
0 |
0 |
0 |
T17 |
45527 |
0 |
0 |
0 |
T18 |
0 |
1 |
0 |
0 |
T19 |
0 |
6 |
0 |
0 |
T44 |
0 |
8 |
0 |
0 |
T49 |
0 |
4 |
0 |
0 |
T50 |
0 |
8 |
0 |
0 |
T51 |
0 |
4 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
327083568 |
326368725 |
0 |
0 |
T1 |
9195 |
9038 |
0 |
0 |
T2 |
3842 |
3192 |
0 |
0 |
T3 |
163740 |
163662 |
0 |
0 |
T4 |
317018 |
316947 |
0 |
0 |
T5 |
175018 |
174954 |
0 |
0 |
T6 |
131369 |
106175 |
0 |
0 |
T11 |
4051 |
3349 |
0 |
0 |
T15 |
4471 |
4376 |
0 |
0 |
T16 |
996 |
912 |
0 |
0 |
T17 |
45527 |
45356 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
327083568 |
326368725 |
0 |
0 |
T1 |
9195 |
9038 |
0 |
0 |
T2 |
3842 |
3192 |
0 |
0 |
T3 |
163740 |
163662 |
0 |
0 |
T4 |
317018 |
316947 |
0 |
0 |
T5 |
175018 |
174954 |
0 |
0 |
T6 |
131369 |
106175 |
0 |
0 |
T11 |
4051 |
3349 |
0 |
0 |
T15 |
4471 |
4376 |
0 |
0 |
T16 |
996 |
912 |
0 |
0 |
T17 |
45527 |
45356 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
327083568 |
326368725 |
0 |
0 |
T1 |
9195 |
9038 |
0 |
0 |
T2 |
3842 |
3192 |
0 |
0 |
T3 |
163740 |
163662 |
0 |
0 |
T4 |
317018 |
316947 |
0 |
0 |
T5 |
175018 |
174954 |
0 |
0 |
T6 |
131369 |
106175 |
0 |
0 |
T11 |
4051 |
3349 |
0 |
0 |
T15 |
4471 |
4376 |
0 |
0 |
T16 |
996 |
912 |
0 |
0 |
T17 |
45527 |
45356 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
327083568 |
4293170 |
0 |
0 |
T1 |
9195 |
9 |
0 |
0 |
T2 |
3842 |
0 |
0 |
0 |
T3 |
163740 |
0 |
0 |
0 |
T4 |
317018 |
41291 |
0 |
0 |
T5 |
175018 |
0 |
0 |
0 |
T6 |
131369 |
0 |
0 |
0 |
T7 |
0 |
16709 |
0 |
0 |
T8 |
0 |
16749 |
0 |
0 |
T11 |
4051 |
0 |
0 |
0 |
T15 |
4471 |
0 |
0 |
0 |
T16 |
996 |
0 |
0 |
0 |
T17 |
45527 |
0 |
0 |
0 |
T18 |
0 |
1 |
0 |
0 |
T19 |
0 |
6 |
0 |
0 |
T44 |
0 |
8 |
0 |
0 |
T49 |
0 |
4 |
0 |
0 |
T50 |
0 |
8 |
0 |
0 |
T51 |
0 |
4 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.u_bank_sequence_fifo
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
ALWAYS | 70 | 4 | 4 | 100.00 |
CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
CONT_ASSIGN | 87 | 1 | 1 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
ALWAYS | 165 | 2 | 2 | 100.00 |
CONT_ASSIGN | 175 | 1 | 1 | 100.00 |
CONT_ASSIGN | 176 | 1 | 1 | 100.00 |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
|
|
|
MISSING_ELSE |
84 |
1 |
1 |
85 |
1 |
1 |
86 |
1 |
1 |
87 |
1 |
1 |
88 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
98 |
1 |
1 |
99 |
1 |
1 |
100 |
1 |
1 |
145 |
1 |
1 |
146 |
1 |
1 |
162 |
1 |
1 |
165 |
1 |
1 |
166 |
1 |
1 |
|
|
|
MISSING_ELSE |
175 |
1 |
1 |
176 |
1 |
1 |
180 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_eflash.u_bank_sequence_fifo
| Total | Covered | Percent |
Conditions | 26 | 21 | 80.77 |
Logical | 26 | 21 | 80.77 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 88
EXPRESSION
Number Term
1 gen_normal_fifo.full ? (2'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value)))))
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T4,T7,T8 |
LINE 88
SUB-EXPRESSION
Number Term
1 (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value))))
-1- | Status | Tests |
0 | Covered | T1,T4,T19 |
1 | Covered | T1,T2,T3 |
LINE 88
SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
---------------------------1--------------------------
-1- | Status | Tests |
0 | Covered | T1,T4,T19 |
1 | Covered | T1,T2,T3 |
LINE 92
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T4,T19 |
LINE 93
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T4,T19 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T4,T19 |
LINE 98
EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T7,T8 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T4,T19 |
LINE 145
EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
------------------------------------------------------1------------------------------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T4,T7,T8 |
LINE 146
EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
----------------------------1---------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 180
EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T4,T19 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_eflash.u_bank_sequence_fifo
| Line No. | Total | Covered | Percent |
Branches |
|
10 |
10 |
100.00 |
TERNARY |
88 |
3 |
3 |
100.00 |
TERNARY |
180 |
2 |
2 |
100.00 |
IF |
70 |
3 |
3 |
100.00 |
IF |
157 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 88 (gen_normal_fifo.full) ?
-2-: 88 ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T4,T7,T8 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T4,T19 |
LineNo. Expression
-1-: 180 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T4,T19 |
LineNo. Expression
-1-: 70 if ((!rst_ni))
-2-: 72 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 157 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T19 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.u_bank_sequence_fifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
327083568 |
27638633 |
0 |
0 |
T1 |
9195 |
33 |
0 |
0 |
T2 |
3842 |
0 |
0 |
0 |
T3 |
163740 |
0 |
0 |
0 |
T4 |
317018 |
152368 |
0 |
0 |
T5 |
175018 |
0 |
0 |
0 |
T6 |
131369 |
0 |
0 |
0 |
T7 |
0 |
28591 |
0 |
0 |
T8 |
0 |
601349 |
0 |
0 |
T11 |
4051 |
0 |
0 |
0 |
T15 |
4471 |
0 |
0 |
0 |
T16 |
996 |
0 |
0 |
0 |
T17 |
45527 |
0 |
0 |
0 |
T18 |
0 |
2 |
0 |
0 |
T19 |
0 |
24 |
0 |
0 |
T44 |
0 |
29 |
0 |
0 |
T49 |
0 |
16 |
0 |
0 |
T50 |
0 |
16 |
0 |
0 |
T51 |
0 |
16 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
327083568 |
326368725 |
0 |
0 |
T1 |
9195 |
9038 |
0 |
0 |
T2 |
3842 |
3192 |
0 |
0 |
T3 |
163740 |
163662 |
0 |
0 |
T4 |
317018 |
316947 |
0 |
0 |
T5 |
175018 |
174954 |
0 |
0 |
T6 |
131369 |
106175 |
0 |
0 |
T11 |
4051 |
3349 |
0 |
0 |
T15 |
4471 |
4376 |
0 |
0 |
T16 |
996 |
912 |
0 |
0 |
T17 |
45527 |
45356 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
327083568 |
326368725 |
0 |
0 |
T1 |
9195 |
9038 |
0 |
0 |
T2 |
3842 |
3192 |
0 |
0 |
T3 |
163740 |
163662 |
0 |
0 |
T4 |
317018 |
316947 |
0 |
0 |
T5 |
175018 |
174954 |
0 |
0 |
T6 |
131369 |
106175 |
0 |
0 |
T11 |
4051 |
3349 |
0 |
0 |
T15 |
4471 |
4376 |
0 |
0 |
T16 |
996 |
912 |
0 |
0 |
T17 |
45527 |
45356 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
327083568 |
326368725 |
0 |
0 |
T1 |
9195 |
9038 |
0 |
0 |
T2 |
3842 |
3192 |
0 |
0 |
T3 |
163740 |
163662 |
0 |
0 |
T4 |
317018 |
316947 |
0 |
0 |
T5 |
175018 |
174954 |
0 |
0 |
T6 |
131369 |
106175 |
0 |
0 |
T11 |
4051 |
3349 |
0 |
0 |
T15 |
4471 |
4376 |
0 |
0 |
T16 |
996 |
912 |
0 |
0 |
T17 |
45527 |
45356 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
327083568 |
27638633 |
0 |
0 |
T1 |
9195 |
33 |
0 |
0 |
T2 |
3842 |
0 |
0 |
0 |
T3 |
163740 |
0 |
0 |
0 |
T4 |
317018 |
152368 |
0 |
0 |
T5 |
175018 |
0 |
0 |
0 |
T6 |
131369 |
0 |
0 |
0 |
T7 |
0 |
28591 |
0 |
0 |
T8 |
0 |
601349 |
0 |
0 |
T11 |
4051 |
0 |
0 |
0 |
T15 |
4471 |
0 |
0 |
0 |
T16 |
996 |
0 |
0 |
0 |
T17 |
45527 |
0 |
0 |
0 |
T18 |
0 |
2 |
0 |
0 |
T19 |
0 |
24 |
0 |
0 |
T44 |
0 |
29 |
0 |
0 |
T49 |
0 |
16 |
0 |
0 |
T50 |
0 |
16 |
0 |
0 |
T51 |
0 |
16 |
0 |
0 |