Unified Coverage Report :: Module :: flash_phy_core

Module : flash_phy_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.37	98.73	95.28		100.00	97.83	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[1].u_core	94.29	96.20	83.96		100.00	91.30	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core	98.37	98.73	95.28		100.00	97.83	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.29	96.20	83.96		100.00	91.30	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.36	97.65	92.66	98.97	100.00	96.91	97.98

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.26	97.67	85.11			100.00		u_eflash

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prog_data.u_prog	97.50	100.00	93.65	95.00	100.00	96.36	100.00
u_disable_buf	100.00	100.00					100.00
u_erase	92.22	100.00	88.89		100.00	80.00
u_host_arb	91.95	75.93	91.89			100.00	100.00
u_host_outstanding_cnt	100.00			100.00
u_rd	97.64	99.15	93.57	100.00		99.25	96.23
u_scramble	98.18	100.00	90.91	100.00		100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.37	98.73	95.28		100.00	97.83	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	97.89	93.73	100.00	100.00	97.94	97.98

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.26	97.67	85.11			100.00		u_eflash

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prog_data.u_prog	98.60	100.00	95.24	100.00	100.00	96.36	100.00
u_disable_buf	100.00	100.00					100.00
u_erase	92.22	100.00	88.89		100.00	80.00
u_host_arb	93.98	75.93	100.00			100.00	100.00
u_host_outstanding_cnt	100.00			100.00
u_rd	97.62	99.15	93.49	100.00		99.25	96.23
u_scramble	98.18	100.00	90.91	100.00		100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : flash_phy_core

	Line No.	Total	Covered	Percent
TOTAL		79	78	98.73
ALWAYS	154	6	6	100.00
ALWAYS	167	3	3	100.00
CONT_ASSIGN	199	1	1	100.00
CONT_ASSIGN	203	1	1	100.00
ALWAYS	206	4	4	100.00
ALWAYS	218	6	6	100.00
ALWAYS	232	6	5	83.33
CONT_ASSIGN	280	1	1	100.00
CONT_ASSIGN	283	1	1	100.00
CONT_ASSIGN	284	1	1	100.00
CONT_ASSIGN	285	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	320	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
ALWAYS	328	29	29	100.00
CONT_ASSIGN	391	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
CONT_ASSIGN	397	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	399	1	1	100.00
CONT_ASSIGN	400	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	551	1	1	100.00
CONT_ASSIGN	579	1	1	100.00
CONT_ASSIGN	586	1	1	100.00
CONT_ASSIGN	603	1	1	100.00
CONT_ASSIGN	604	1	1	100.00
CONT_ASSIGN	605	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
154	1	1
155	1	1
156	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
167	3	3
199	1	1
203	1	1
206	1	1
207	1	1
208	1	1
209	1	1
			MISSING_ELSE
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
			MISSING_ELSE
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	0	1
			MISSING_ELSE
280	1	1
283	1	1
284	1	1
285	1	1
290	1	1
320	1	1
324	1	1
328	1	1
329	1	1
330	1	1
331	1	1
332	1	1
334	1	1
336	1	1
337	1	1
338	1	1
339	1	1
340	1	1
341	1	1
342	1	1
343	1	1
344	1	1
			MISSING_ELSE
350	1	1
351	1	1
352	1	1
			MISSING_ELSE
359	1	1
360	1	1
361	1	1
362	1	1
			MISSING_ELSE
368	1	1
369	1	1
370	1	1
371	1	1
372	1	1
			MISSING_ELSE
377	1	1
378	1	1
391	1	1
395	1	1
396	1	1
397	1	1
398	1	1
399	1	1
400	1	1
401	1	1
418	1	1
431	1	1
551	1	1
579	1	1
586	1	1
603	1	1
604	1	1
605	1	1

---

Cond Coverage for Module : flash_phy_core

	Total	Covered	Percent
Conditions	106	101	95.28
Logical	106	101	95.28
Non-Logical	0	0
Event	0	0

 LINE       199
 EXPRESSION (host_gnt && (muxed_part != FlashPartData))
             ----1---    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T19
1	1	Covered	T194,T183,T181

 LINE       199
 SUB-EXPRESSION (muxed_part != FlashPartData)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       203
 EXPRESSION (((|host_outstanding)) & ((!ctrl_fsm_idle)))
             ----------1----------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T19
1	1	Not Covered

 LINE       208
 EXPRESSION (host_gnt_err_event | host_outstanding_err_event)
             ---------1--------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T194,T183,T181

 LINE       220
 EXPRESSION (host_outstanding == '0)
            ------------1-----------

-1-	Status	Tests
0	Covered	T1,T5,T19
1	Covered	T1,T2,T3

 LINE       234
 EXPRESSION ((host_outstanding == '0) && ctrl_fsm_idle)
             ------------1-----------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       234
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T5,T19
1	Covered	T1,T2,T3

 LINE       245
 EXPRESSION (host_gnt && ((!host_req_done_o)) && (host_outstanding <= flash_phy_pkg::RspOrderDepth))
             ----1---    ----------2---------    -------------------------3------------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T19,T7
1	1	0	Not Covered
1	1	1	Covered	T1,T5,T19

 LINE       245
 EXPRESSION (((!host_gnt)) && host_req_done_o && ((|host_outstanding)))
             ------1------    -------2-------    ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T19,T7
1	0	1	Covered	T1,T5,T19
1	1	0	Covered	T132,T133,T158
1	1	1	Covered	T1,T5,T19

 LINE       284
 EXPRESSION (host_req & host_req_rdy_o)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T7,T8
1	1	Covered	T1,T5,T19

 LINE       285
 EXPRESSION (((|host_outstanding)) & rd_stage_data_valid)
             ----------1----------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T19
1	1	Covered	T1,T5,T19

 LINE       320
 EXPRESSION ((phy_req & host_req) ? rd_stage_rdy : rd_stage_idle)
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T19

 LINE       320
 SUB-EXPRESSION (phy_req & host_req)
                 ---1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T68,T66,T69
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T5,T19

 LINE       324
 EXPRESSION (req_i & host_gnt)
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T7,T8

 LINE       339
 EXPRESSION (ctrl_gnt && rd_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       341
 EXPRESSION (ctrl_gnt && prog_i)
             ----1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T2,T12,T13
1	1	Covered	T1,T2,T4

 LINE       391
 EXPRESSION ((ctrl_fsm_idle & ctrl_rsp_vld) | ((host_outstanding == '0) & host_req_done_o))
             ---------------1--------------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T132,T133,T158
1	0	Covered	T197,T198

 LINE       391
 SUB-EXPRESSION (ctrl_fsm_idle & ctrl_rsp_vld)
                 ------1------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T197,T198

 LINE       391
 SUB-EXPRESSION ((host_outstanding == '0) & host_req_done_o)
                 ------------1-----------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T132,T133,T158

 LINE       391
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (host_sel ? host_addr_i : addr_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T19

 LINE       396
 EXPRESSION (host_sel ? FlashPartData : part_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T19

 LINE       397
 EXPRESSION (host_sel ? host_scramble_en_i : scramble_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T19

 LINE       398
 EXPRESSION (host_sel ? host_ecc_en_i : ecc_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T19

 LINE       399
 EXPRESSION (ctrl_rsp_vld & rd_i)
             ------1-----   --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       400
 EXPRESSION (ctrl_rsp_vld & prog_i)
             ------1-----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       401
 EXPRESSION (ctrl_rsp_vld & (pg_erase_i | bk_erase_i))
             ------1-----   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T12,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T13,T47

 LINE       401
 SUB-EXPRESSION (pg_erase_i | bk_erase_i)
                 -----1----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T23,T24
1	0	Covered	T2,T12,T13

 LINE       431
 EXPRESSION ((host_gnt_rd_err & (host_outstanding == 1'b1)) | host_outstanding_rd_err)
             -----------------------1----------------------   -----------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T183,T184

 LINE       431
 SUB-EXPRESSION (host_gnt_rd_err & (host_outstanding == 1'b1))
                 -------1-------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T19
1	0	Covered	T183,T184
1	1	Covered	T183,T184

 LINE       431
 SUB-EXPRESSION (host_outstanding == 1'b1)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T19

 LINE       434
 EXPRESSION (phy_req & (rd_i | host_req))
             ---1---   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       434
 SUB-EXPRESSION (rd_i | host_req)
                 --1-   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T5,T19
1	0	Covered	T1,T2,T3

 LINE       434
 EXPRESSION (arb_host_gnt_err ? ({flash_phy_pkg::FullDataWidth {1'b1}}) : flash_rdata)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T183,T184

 LINE       551
 EXPRESSION (prog_calc_req ? muxed_addr[(flash_phy_pkg::BusBankAddrW - 1):flash_phy_pkg::LsbAddrBit] : rd_calc_addr)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T13,T9

 LINE       557
 EXPRESSION (prog_calc_req | rd_calc_req)
             ------1------   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T13,T9

 LINE       557
 EXPRESSION (prog_op_req | rd_op_req)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T13,T9

 LINE       557
 EXPRESSION (prog_op_req ? ScrambleOp : DeScrambleOp)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T13,T9

 LINE       579
 EXPRESSION (fsm_err | prog_fsm_err)
             ---1---   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T15,T16,T17
1	0	Covered	T15,T16,T17

---

FSM Coverage for Module : flash_phy_core

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCtrl	344	Covered	T2,T12,T13
StCtrlProg	342	Covered	T1,T2,T4
StCtrlRead	340	Covered	T1,T2,T3
StDisable	338	Covered	T12,T13,T9
StIdle	352	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
StCtrl->StIdle	372	Covered	T2,T12,T13
StCtrlProg->StIdle	362	Covered	T1,T2,T4
StCtrlRead->StIdle	352	Covered	T1,T2,T3
StIdle->StCtrl	344	Covered	T2,T12,T13
StIdle->StCtrlProg	342	Covered	T1,T2,T4
StIdle->StCtrlRead	340	Covered	T1,T2,T3
StIdle->StDisable	338	Covered	T12,T13,T9

---

Branch Coverage for Module : flash_phy_core

	Line No.	Total	Covered	Percent
Branches		46	45	97.83
TERNARY	320	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	396	2	2	100.00
TERNARY	397	2	2	100.00
TERNARY	398	2	2	100.00
TERNARY	551	2	2	100.00
TERNARY	434	2	2	100.00
TERNARY	557	2	2	100.00
IF	154	4	4	100.00
IF	167	2	2	100.00
IF	206	3	3	100.00
IF	218	4	4	100.00
IF	232	4	3	75.00
CASE	334	13	13	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	320	((phy_req & host_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T19
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T19
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	396	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T19
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	397	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T19
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	398	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T19
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	551	(prog_calc_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T13,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	434	(arb_host_gnt_err) ? 

Branches:

-1-	Status	Tests
1	Covered	T183,T184
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	557	(prog_op_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T13,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	154	if ((!rst_ni))
-2-:	156	if (ctrl_rsp_vld)
-3-:	158	if (inc_arb_cnt)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T5,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	167	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	206	if ((!rst_ni))
-2-:	208	if ((host_gnt_err_event | host_outstanding_err_event))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T194,T183,T181
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	218	if ((!rst_ni))
-2-:	220	if ((host_outstanding == '0))
-3-:	222	if (host_gnt_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T183,T184
0	0	0	Covered	T1,T5,T19

	LineNo.	Expression
-1-:	232	if ((!rst_ni))
-2-:	234	if (((host_outstanding == '0) && ctrl_fsm_idle))
-3-:	236	if (host_outstanding_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Not Covered
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	334	case (state_q)
-2-:	337	if (prim_mubi_pkg::mubi4_test_true_loose(flash_disable[FsmDisableIdx]))
-3-:	339	if ((ctrl_gnt && rd_i))
-4-:	341	if ((ctrl_gnt && prog_i))
-5-:	343	if (ctrl_gnt)
-6-:	350	if (rd_stage_data_valid)
-7-:	360	if (prog_ack)
-8-:	370	if (erase_ack)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
StIdle	1	-	-	-	-	-	-	Covered	T12,T13,T9
StIdle	0	1	-	-	-	-	-	Covered	T1,T2,T3
StIdle	0	0	1	-	-	-	-	Covered	T1,T2,T4
StIdle	0	0	0	1	-	-	-	Covered	T2,T12,T13
StIdle	0	0	0	0	-	-	-	Covered	T1,T2,T3
StCtrlRead	-	-	-	-	1	-	-	Covered	T1,T2,T3
StCtrlRead	-	-	-	-	0	-	-	Covered	T1,T2,T3
StCtrlProg	-	-	-	-	-	1	-	Covered	T1,T2,T4
StCtrlProg	-	-	-	-	-	0	-	Covered	T1,T2,T4
StCtrl	-	-	-	-	-	-	1	Covered	T2,T13,T47
StCtrl	-	-	-	-	-	-	0	Covered	T2,T12,T13
StDisable	-	-	-	-	-	-	-	Covered	T12,T13,T9
default	-	-	-	-	-	-	-	Covered	T15,T16,T17

---

Assert Coverage for Module : flash_phy_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ArbCntMax_A	725977760	4377159	0	0
CtrlPrio_A	725977760	4377159	0	0
HostTransIdleChk_A	725977760	45314295	0	0
NoRemainder_A	1982	1982	0	0
OneHotReqs_A	725977760	724282096	0	0
Pow2Multiple_A	1982	1982	0	0
RdTxnCheck_A	725534436	723838772	0	0
u_state_regs_A	725977760	724282096	0	0

ArbCntMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	725977760	4377159	0	0
T5	96474	2790	0	0
T6	422540	0	0	0
T7	237406	6012	0	0
T8	103902	4650	0	0
T9	9258	0	0	0
T14	3036	0	0	0
T19	55696	0	0	0
T20	0	5670	0	0
T22	652162	18615	0	0
T30	0	5751	0	0
T45	0	2469	0	0
T46	0	9716	0	0
T47	20300	0	0	0
T48	342836	0	0	0
T59	0	86211	0	0
T154	0	6663	0	0

CtrlPrio_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	725977760	4377159	0	0
T5	96474	2790	0	0
T6	422540	0	0	0
T7	237406	6012	0	0
T8	103902	4650	0	0
T9	9258	0	0	0
T14	3036	0	0	0
T19	55696	0	0	0
T20	0	5670	0	0
T22	652162	18615	0	0
T30	0	5751	0	0
T45	0	2469	0	0
T46	0	9716	0	0
T47	20300	0	0	0
T48	342836	0	0	0
T59	0	86211	0	0
T154	0	6663	0	0

HostTransIdleChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	725977760	45314295	0	0
T1	3195	28	0	0
T2	107248	0	0	0
T3	2343	0	0	0
T4	260719	0	0	0
T5	96474	31813	0	0
T6	211270	0	0	0
T7	118703	53660	0	0
T8	51951	53118	0	0
T9	9258	0	0	0
T12	3575	0	0	0
T13	393400	0	0	0
T14	1518	0	0	0
T18	1295	0	0	0
T19	55696	531	0	0
T20	0	26991	0	0
T22	326081	212554	0	0
T30	0	56466	0	0
T45	0	33857	0	0
T46	0	52138	0	0
T47	10150	26	0	0
T48	171418	0	0	0
T49	0	23	0	0
T73	0	16	0	0

NoRemainder_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1982	1982	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T9	2	2	0	0
T12	2	2	0	0
T13	2	2	0	0
T18	2	2	0	0
T19	2	2	0	0

OneHotReqs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	725977760	724282096	0	0
T1	6390	6092	0	0
T2	214496	214486	0	0
T3	4686	4578	0	0
T4	521438	521292	0	0
T5	96474	96306	0	0
T9	9258	8256	0	0
T12	7150	5940	0	0
T13	786800	786776	0	0
T18	2590	2452	0	0
T19	55696	55586	0	0

Pow2Multiple_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1982	1982	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T9	2	2	0	0
T12	2	2	0	0
T13	2	2	0	0
T18	2	2	0	0
T19	2	2	0	0

RdTxnCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	725534436	723838772	0	0
T1	6390	6092	0	0
T2	214496	214486	0	0
T3	4686	4578	0	0
T4	521438	521292	0	0
T5	96474	96306	0	0
T9	9258	8256	0	0
T12	7150	5940	0	0
T13	786800	786776	0	0
T18	2590	2452	0	0
T19	55696	55586	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	725977760	724282096	0	0
T1	6390	6092	0	0
T2	214496	214486	0	0
T3	4686	4578	0	0
T4	521438	521292	0	0
T5	96474	96306	0	0
T9	9258	8256	0	0
T12	7150	5940	0	0
T13	786800	786776	0	0
T18	2590	2452	0	0
T19	55696	55586	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

	Line No.	Total	Covered	Percent
TOTAL		79	76	96.20
ALWAYS	154	6	6	100.00
ALWAYS	167	3	3	100.00
CONT_ASSIGN	199	1	1	100.00
CONT_ASSIGN	203	1	1	100.00
ALWAYS	206	4	3	75.00
ALWAYS	218	6	5	83.33
ALWAYS	232	6	5	83.33
CONT_ASSIGN	280	1	1	100.00
CONT_ASSIGN	283	1	1	100.00
CONT_ASSIGN	284	1	1	100.00
CONT_ASSIGN	285	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	320	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
ALWAYS	328	29	29	100.00
CONT_ASSIGN	391	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
CONT_ASSIGN	397	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	399	1	1	100.00
CONT_ASSIGN	400	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	551	1	1	100.00
CONT_ASSIGN	579	1	1	100.00
CONT_ASSIGN	586	1	1	100.00
CONT_ASSIGN	603	1	1	100.00
CONT_ASSIGN	604	1	1	100.00
CONT_ASSIGN	605	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
154	1	1
155	1	1
156	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
167	3	3
199	1	1
203	1	1
206	1	1
207	1	1
208	1	1
209	0	1
			MISSING_ELSE
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	0	1
			MISSING_ELSE
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	0	1
			MISSING_ELSE
280	1	1
283	1	1
284	1	1
285	1	1
290	1	1
320	1	1
324	1	1
328	1	1
329	1	1
330	1	1
331	1	1
332	1	1
334	1	1
336	1	1
337	1	1
338	1	1
339	1	1
340	1	1
341	1	1
342	1	1
343	1	1
344	1	1
			MISSING_ELSE
350	1	1
351	1	1
352	1	1
			MISSING_ELSE
359	1	1
360	1	1
361	1	1
362	1	1
			MISSING_ELSE
368	1	1
369	1	1
370	1	1
371	1	1
372	1	1
			MISSING_ELSE
377	1	1
378	1	1
391	1	1
395	1	1
396	1	1
397	1	1
398	1	1
399	1	1
400	1	1
401	1	1
418	1	1
431	1	1
551	1	1
579	1	1
586	1	1
603	1	1
604	1	1
605	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

	Total	Covered	Percent
Conditions	106	89	83.96
Logical	106	89	83.96
Non-Logical	0	0
Event	0	0

 LINE       199
 EXPRESSION (host_gnt && (muxed_part != FlashPartData))
             ----1---    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T19,T7
1	1	Not Covered

 LINE       199
 SUB-EXPRESSION (muxed_part != FlashPartData)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       203
 EXPRESSION (((|host_outstanding)) & ((!ctrl_fsm_idle)))
             ----------1----------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T13
1	0	Covered	T5,T19,T7
1	1	Not Covered

 LINE       208
 EXPRESSION (host_gnt_err_event | host_outstanding_err_event)
             ---------1--------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       220
 EXPRESSION (host_outstanding == '0)
            ------------1-----------

-1-	Status	Tests
0	Covered	T5,T19,T7
1	Covered	T1,T2,T3

 LINE       234
 EXPRESSION ((host_outstanding == '0) && ctrl_fsm_idle)
             ------------1-----------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T5,T19,T7
1	0	Covered	T2,T4,T13
1	1	Covered	T1,T2,T3

 LINE       234
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T5,T19,T7
1	Covered	T1,T2,T3

 LINE       245
 EXPRESSION (host_gnt && ((!host_req_done_o)) && (host_outstanding <= flash_phy_pkg::RspOrderDepth))
             ----1---    ----------2---------    -------------------------3------------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T19,T7
1	1	0	Not Covered
1	1	1	Covered	T5,T19,T7

 LINE       245
 EXPRESSION (((!host_gnt)) && host_req_done_o && ((|host_outstanding)))
             ------1------    -------2-------    ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T19,T7
1	0	1	Covered	T5,T19,T7
1	1	0	Not Covered
1	1	1	Covered	T5,T19,T7

 LINE       284
 EXPRESSION (host_req & host_req_rdy_o)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T7,T8
1	1	Covered	T5,T19,T7

 LINE       285
 EXPRESSION (((|host_outstanding)) & rd_stage_data_valid)
             ----------1----------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T2,T13,T5
1	0	Covered	T5,T19,T7
1	1	Covered	T5,T19,T7

 LINE       320
 EXPRESSION ((phy_req & host_req) ? rd_stage_rdy : rd_stage_idle)
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T19,T7

 LINE       320
 SUB-EXPRESSION (phy_req & host_req)
                 ---1---   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T4,T13
1	1	Covered	T5,T19,T7

 LINE       324
 EXPRESSION (req_i & host_gnt)
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T19,T7
1	0	Covered	T2,T4,T13
1	1	Covered	T5,T7,T8

 LINE       339
 EXPRESSION (ctrl_gnt && rd_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T13
1	1	Covered	T2,T13,T5

 LINE       341
 EXPRESSION (ctrl_gnt && prog_i)
             ----1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T2,T13,T27
1	1	Covered	T2,T4,T13

 LINE       391
 EXPRESSION ((ctrl_fsm_idle & ctrl_rsp_vld) | ((host_outstanding == '0) & host_req_done_o))
             ---------------1--------------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       391
 SUB-EXPRESSION (ctrl_fsm_idle & ctrl_rsp_vld)
                 ------1------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T13
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       391
 SUB-EXPRESSION ((host_outstanding == '0) & host_req_done_o)
                 ------------1-----------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T5,T19,T7
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       391
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (host_sel ? host_addr_i : addr_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T19,T7

 LINE       396
 EXPRESSION (host_sel ? FlashPartData : part_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T19,T7

 LINE       397
 EXPRESSION (host_sel ? host_scramble_en_i : scramble_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T19,T7

 LINE       398
 EXPRESSION (host_sel ? host_ecc_en_i : ecc_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T19,T7

 LINE       399
 EXPRESSION (ctrl_rsp_vld & rd_i)
             ------1-----   --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T13
1	1	Covered	T2,T13,T5

 LINE       400
 EXPRESSION (ctrl_rsp_vld & prog_i)
             ------1-----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T2,T13,T5
1	1	Covered	T2,T4,T13

 LINE       401
 EXPRESSION (ctrl_rsp_vld & (pg_erase_i | bk_erase_i))
             ------1-----   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T12,T13
1	0	Covered	T2,T4,T13
1	1	Covered	T2,T13,T27

 LINE       401
 SUB-EXPRESSION (pg_erase_i | bk_erase_i)
                 -----1----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T23,T24
1	0	Covered	T2,T12,T13

 LINE       431
 EXPRESSION ((host_gnt_rd_err & (host_outstanding == 1'b1)) | host_outstanding_rd_err)
             -----------------------1----------------------   -----------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       431
 SUB-EXPRESSION (host_gnt_rd_err & (host_outstanding == 1'b1))
                 -------1-------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T19,T7
1	0	Not Covered
1	1	Not Covered

 LINE       431
 SUB-EXPRESSION (host_outstanding == 1'b1)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T19,T7

 LINE       434
 EXPRESSION (phy_req & (rd_i | host_req))
             ---1---   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T13
1	1	Covered	T2,T13,T5

 LINE       434
 SUB-EXPRESSION (rd_i | host_req)
                 --1-   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T19,T7
1	0	Covered	T1,T2,T3

 LINE       434
 EXPRESSION (arb_host_gnt_err ? ({flash_phy_pkg::FullDataWidth {1'b1}}) : flash_rdata)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       551
 EXPRESSION (prog_calc_req ? muxed_addr[(flash_phy_pkg::BusBankAddrW - 1):flash_phy_pkg::LsbAddrBit] : rd_calc_addr)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T9,T22

 LINE       557
 EXPRESSION (prog_calc_req | rd_calc_req)
             ------1------   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T7,T8
1	0	Covered	T13,T9,T22

 LINE       557
 EXPRESSION (prog_op_req | rd_op_req)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T7,T8
1	0	Covered	T13,T9,T22

 LINE       557
 EXPRESSION (prog_op_req ? ScrambleOp : DeScrambleOp)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T9,T22

 LINE       579
 EXPRESSION (fsm_err | prog_fsm_err)
             ---1---   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T15,T16,T17
1	0	Covered	T15,T16,T17

---

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCtrl	344	Covered	T2,T13,T27
StCtrlProg	342	Covered	T2,T4,T9
StCtrlRead	340	Covered	T2,T5,T19
StDisable	338	Covered	T12,T13,T9
StIdle	352	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
StCtrl->StIdle	372	Covered	T2,T13,T27
StCtrlProg->StIdle	362	Covered	T2,T4,T9
StCtrlRead->StIdle	352	Covered	T2,T5,T19
StIdle->StCtrl	344	Covered	T2,T13,T27
StIdle->StCtrlProg	342	Covered	T2,T4,T9
StIdle->StCtrlRead	340	Covered	T2,T5,T19
StIdle->StDisable	338	Covered	T12,T13,T9

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

	Line No.	Total	Covered	Percent
Branches		46	42	91.30
TERNARY	320	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	396	2	2	100.00
TERNARY	397	2	2	100.00
TERNARY	398	2	2	100.00
TERNARY	551	2	2	100.00
TERNARY	434	2	1	50.00
TERNARY	557	2	2	100.00
IF	154	4	4	100.00
IF	167	2	2	100.00
IF	206	3	2	66.67
IF	218	4	3	75.00
IF	232	4	3	75.00
CASE	334	13	13	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	320	((phy_req & host_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T19,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T19,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	396	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T19,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	397	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T19,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	398	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T19,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	551	(prog_calc_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T9,T22
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	434	(arb_host_gnt_err) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	557	(prog_op_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T9,T22
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	154	if ((!rst_ni))
-2-:	156	if (ctrl_rsp_vld)
-3-:	158	if (inc_arb_cnt)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T4,T13
0	0	1	Covered	T5,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	167	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	206	if ((!rst_ni))
-2-:	208	if ((host_gnt_err_event | host_outstanding_err_event))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	218	if ((!rst_ni))
-2-:	220	if ((host_outstanding == '0))
-3-:	222	if (host_gnt_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Not Covered
0	0	0	Covered	T5,T19,T7

	LineNo.	Expression
-1-:	232	if ((!rst_ni))
-2-:	234	if (((host_outstanding == '0) && ctrl_fsm_idle))
-3-:	236	if (host_outstanding_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Not Covered
0	0	0	Covered	T2,T4,T13

	LineNo.	Expression
-1-:	334	case (state_q)
-2-:	337	if (prim_mubi_pkg::mubi4_test_true_loose(flash_disable[FsmDisableIdx]))
-3-:	339	if ((ctrl_gnt && rd_i))
-4-:	341	if ((ctrl_gnt && prog_i))
-5-:	343	if (ctrl_gnt)
-6-:	350	if (rd_stage_data_valid)
-7-:	360	if (prog_ack)
-8-:	370	if (erase_ack)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
StIdle	1	-	-	-	-	-	-	Covered	T12,T13,T9
StIdle	0	1	-	-	-	-	-	Covered	T2,T13,T5
StIdle	0	0	1	-	-	-	-	Covered	T2,T4,T13
StIdle	0	0	0	1	-	-	-	Covered	T2,T13,T27
StIdle	0	0	0	0	-	-	-	Covered	T1,T2,T3
StCtrlRead	-	-	-	-	1	-	-	Covered	T2,T13,T5
StCtrlRead	-	-	-	-	0	-	-	Covered	T2,T13,T5
StCtrlProg	-	-	-	-	-	1	-	Covered	T2,T4,T13
StCtrlProg	-	-	-	-	-	0	-	Covered	T2,T4,T13
StCtrl	-	-	-	-	-	-	1	Covered	T2,T13,T27
StCtrl	-	-	-	-	-	-	0	Covered	T2,T13,T27
StDisable	-	-	-	-	-	-	-	Covered	T12,T13,T9
default	-	-	-	-	-	-	-	Covered	T15,T16,T17

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ArbCntMax_A	362988880	1994529	0	0
CtrlPrio_A	362988880	1994529	0	0
HostTransIdleChk_A	362988880	22222692	0	0
NoRemainder_A	991	991	0	0
OneHotReqs_A	362988880	362141048	0	0
Pow2Multiple_A	991	991	0	0
RdTxnCheck_A	362767218	361919386	0	0
u_state_regs_A	362988880	362141048	0	0

ArbCntMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	1994529	0	0
T5	48237	1365	0	0
T6	211270	0	0	0
T7	118703	1746	0	0
T8	51951	1107	0	0
T9	4629	0	0	0
T14	1518	0	0	0
T19	27848	0	0	0
T20	0	1386	0	0
T22	326081	7990	0	0
T30	0	2502	0	0
T45	0	1399	0	0
T46	0	1661	0	0
T47	10150	0	0	0
T48	171418	0	0	0
T59	0	37595	0	0
T154	0	954	0	0

CtrlPrio_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	1994529	0	0
T5	48237	1365	0	0
T6	211270	0	0	0
T7	118703	1746	0	0
T8	51951	1107	0	0
T9	4629	0	0	0
T14	1518	0	0	0
T19	27848	0	0	0
T20	0	1386	0	0
T22	326081	7990	0	0
T30	0	2502	0	0
T45	0	1399	0	0
T46	0	1661	0	0
T47	10150	0	0	0
T48	171418	0	0	0
T59	0	37595	0	0
T154	0	954	0	0

HostTransIdleChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	22222692	0	0
T5	48237	15378	0	0
T6	211270	0	0	0
T7	118703	26916	0	0
T8	51951	25102	0	0
T9	4629	0	0	0
T14	1518	0	0	0
T19	27848	324	0	0
T20	0	26991	0	0
T22	326081	94444	0	0
T30	0	28939	0	0
T45	0	16736	0	0
T46	0	52138	0	0
T47	10150	0	0	0
T48	171418	0	0	0
T73	0	16	0	0

NoRemainder_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	991	991	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

OneHotReqs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	362141048	0	0
T1	3195	3046	0	0
T2	107248	107243	0	0
T3	2343	2289	0	0
T4	260719	260646	0	0
T5	48237	48153	0	0
T9	4629	4128	0	0
T12	3575	2970	0	0
T13	393400	393388	0	0
T18	1295	1226	0	0
T19	27848	27793	0	0

Pow2Multiple_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	991	991	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

RdTxnCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362767218	361919386	0	0
T1	3195	3046	0	0
T2	107248	107243	0	0
T3	2343	2289	0	0
T4	260719	260646	0	0
T5	48237	48153	0	0
T9	4629	4128	0	0
T12	3575	2970	0	0
T13	393400	393388	0	0
T18	1295	1226	0	0
T19	27848	27793	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	362141048	0	0
T1	3195	3046	0	0
T2	107248	107243	0	0
T3	2343	2289	0	0
T4	260719	260646	0	0
T5	48237	48153	0	0
T9	4629	4128	0	0
T12	3575	2970	0	0
T13	393400	393388	0	0
T18	1295	1226	0	0
T19	27848	27793	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

	Line No.	Total	Covered	Percent
TOTAL		79	78	98.73
ALWAYS	154	6	6	100.00
ALWAYS	167	3	3	100.00
CONT_ASSIGN	199	1	1	100.00
CONT_ASSIGN	203	1	1	100.00
ALWAYS	206	4	4	100.00
ALWAYS	218	6	6	100.00
ALWAYS	232	6	5	83.33
CONT_ASSIGN	280	1	1	100.00
CONT_ASSIGN	283	1	1	100.00
CONT_ASSIGN	284	1	1	100.00
CONT_ASSIGN	285	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	320	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
ALWAYS	328	29	29	100.00
CONT_ASSIGN	391	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
CONT_ASSIGN	397	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	399	1	1	100.00
CONT_ASSIGN	400	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	551	1	1	100.00
CONT_ASSIGN	579	1	1	100.00
CONT_ASSIGN	586	1	1	100.00
CONT_ASSIGN	603	1	1	100.00
CONT_ASSIGN	604	1	1	100.00
CONT_ASSIGN	605	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
154	1	1
155	1	1
156	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
167	3	3
199	1	1
203	1	1
206	1	1
207	1	1
208	1	1
209	1	1
			MISSING_ELSE
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
			MISSING_ELSE
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	0	1
			MISSING_ELSE
280	1	1
283	1	1
284	1	1
285	1	1
290	1	1
320	1	1
324	1	1
328	1	1
329	1	1
330	1	1
331	1	1
332	1	1
334	1	1
336	1	1
337	1	1
338	1	1
339	1	1
340	1	1
341	1	1
342	1	1
343	1	1
344	1	1
			MISSING_ELSE
350	1	1
351	1	1
352	1	1
			MISSING_ELSE
359	1	1
360	1	1
361	1	1
362	1	1
			MISSING_ELSE
368	1	1
369	1	1
370	1	1
371	1	1
372	1	1
			MISSING_ELSE
377	1	1
378	1	1
391	1	1
395	1	1
396	1	1
397	1	1
398	1	1
399	1	1
400	1	1
401	1	1
418	1	1
431	1	1
551	1	1
579	1	1
586	1	1
603	1	1
604	1	1
605	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

	Total	Covered	Percent
Conditions	106	101	95.28
Logical	106	101	95.28
Non-Logical	0	0
Event	0	0

 LINE       199
 EXPRESSION (host_gnt && (muxed_part != FlashPartData))
             ----1---    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T19
1	1	Covered	T194,T183,T181

 LINE       199
 SUB-EXPRESSION (muxed_part != FlashPartData)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       203
 EXPRESSION (((|host_outstanding)) & ((!ctrl_fsm_idle)))
             ----------1----------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T19
1	1	Not Covered

 LINE       208
 EXPRESSION (host_gnt_err_event | host_outstanding_err_event)
             ---------1--------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T194,T183,T181

 LINE       220
 EXPRESSION (host_outstanding == '0)
            ------------1-----------

-1-	Status	Tests
0	Covered	T1,T5,T19
1	Covered	T1,T2,T3

 LINE       234
 EXPRESSION ((host_outstanding == '0) && ctrl_fsm_idle)
             ------------1-----------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       234
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T5,T19
1	Covered	T1,T2,T3

 LINE       245
 EXPRESSION (host_gnt && ((!host_req_done_o)) && (host_outstanding <= flash_phy_pkg::RspOrderDepth))
             ----1---    ----------2---------    -------------------------3------------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T19,T7
1	1	0	Not Covered
1	1	1	Covered	T1,T5,T19

 LINE       245
 EXPRESSION (((!host_gnt)) && host_req_done_o && ((|host_outstanding)))
             ------1------    -------2-------    ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T19,T7
1	0	1	Covered	T1,T5,T19
1	1	0	Covered	T132,T133,T158
1	1	1	Covered	T1,T5,T19

 LINE       284
 EXPRESSION (host_req & host_req_rdy_o)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T7,T8
1	1	Covered	T1,T5,T19

 LINE       285
 EXPRESSION (((|host_outstanding)) & rd_stage_data_valid)
             ----------1----------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T19
1	1	Covered	T1,T5,T19

 LINE       320
 EXPRESSION ((phy_req & host_req) ? rd_stage_rdy : rd_stage_idle)
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T19

 LINE       320
 SUB-EXPRESSION (phy_req & host_req)
                 ---1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T68,T66,T69
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T5,T19

 LINE       324
 EXPRESSION (req_i & host_gnt)
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T7,T8

 LINE       339
 EXPRESSION (ctrl_gnt && rd_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T2,T13,T5
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       341
 EXPRESSION (ctrl_gnt && prog_i)
             ----1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T13
1	0	Covered	T2,T12,T13
1	1	Covered	T1,T2,T4

 LINE       391
 EXPRESSION ((ctrl_fsm_idle & ctrl_rsp_vld) | ((host_outstanding == '0) & host_req_done_o))
             ---------------1--------------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T132,T133,T158
1	0	Covered	T197,T198

 LINE       391
 SUB-EXPRESSION (ctrl_fsm_idle & ctrl_rsp_vld)
                 ------1------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T197,T198

 LINE       391
 SUB-EXPRESSION ((host_outstanding == '0) & host_req_done_o)
                 ------------1-----------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T132,T133,T158

 LINE       391
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (host_sel ? host_addr_i : addr_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T19

 LINE       396
 EXPRESSION (host_sel ? FlashPartData : part_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T19

 LINE       397
 EXPRESSION (host_sel ? host_scramble_en_i : scramble_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T19

 LINE       398
 EXPRESSION (host_sel ? host_ecc_en_i : ecc_en_i)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T19

 LINE       399
 EXPRESSION (ctrl_rsp_vld & rd_i)
             ------1-----   --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       400
 EXPRESSION (ctrl_rsp_vld & prog_i)
             ------1-----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       401
 EXPRESSION (ctrl_rsp_vld & (pg_erase_i | bk_erase_i))
             ------1-----   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T12,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T13,T47

 LINE       401
 SUB-EXPRESSION (pg_erase_i | bk_erase_i)
                 -----1----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T23,T24
1	0	Covered	T2,T12,T13

 LINE       431
 EXPRESSION ((host_gnt_rd_err & (host_outstanding == 1'b1)) | host_outstanding_rd_err)
             -----------------------1----------------------   -----------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T183,T184

 LINE       431
 SUB-EXPRESSION (host_gnt_rd_err & (host_outstanding == 1'b1))
                 -------1-------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T19
1	0	Covered	T183,T184
1	1	Covered	T183,T184

 LINE       431
 SUB-EXPRESSION (host_outstanding == 1'b1)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T19

 LINE       434
 EXPRESSION (phy_req & (rd_i | host_req))
             ---1---   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       434
 SUB-EXPRESSION (rd_i | host_req)
                 --1-   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T5,T19
1	0	Covered	T1,T2,T3

 LINE       434
 EXPRESSION (arb_host_gnt_err ? ({flash_phy_pkg::FullDataWidth {1'b1}}) : flash_rdata)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T183,T184

 LINE       551
 EXPRESSION (prog_calc_req ? muxed_addr[(flash_phy_pkg::BusBankAddrW - 1):flash_phy_pkg::LsbAddrBit] : rd_calc_addr)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T13,T9

 LINE       557
 EXPRESSION (prog_calc_req | rd_calc_req)
             ------1------   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T13,T9

 LINE       557
 EXPRESSION (prog_op_req | rd_op_req)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T13,T9

 LINE       557
 EXPRESSION (prog_op_req ? ScrambleOp : DeScrambleOp)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T13,T9

 LINE       579
 EXPRESSION (fsm_err | prog_fsm_err)
             ---1---   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T15,T16,T17
1	0	Covered	T15,T16,T17

---

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCtrl	344	Covered	T2,T12,T13
StCtrlProg	342	Covered	T1,T2,T4
StCtrlRead	340	Covered	T1,T2,T3
StDisable	338	Covered	T12,T13,T9
StIdle	352	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
StCtrl->StIdle	372	Covered	T2,T12,T13
StCtrlProg->StIdle	362	Covered	T1,T2,T4
StCtrlRead->StIdle	352	Covered	T1,T2,T3
StIdle->StCtrl	344	Covered	T2,T12,T13
StIdle->StCtrlProg	342	Covered	T1,T2,T4
StIdle->StCtrlRead	340	Covered	T1,T2,T3
StIdle->StDisable	338	Covered	T12,T13,T9

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

	Line No.	Total	Covered	Percent
Branches		46	45	97.83
TERNARY	320	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	396	2	2	100.00
TERNARY	397	2	2	100.00
TERNARY	398	2	2	100.00
TERNARY	551	2	2	100.00
TERNARY	434	2	2	100.00
TERNARY	557	2	2	100.00
IF	154	4	4	100.00
IF	167	2	2	100.00
IF	206	3	3	100.00
IF	218	4	4	100.00
IF	232	4	3	75.00
CASE	334	13	13	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	320	((phy_req & host_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T19
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T19
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	396	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T19
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	397	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T19
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	398	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T19
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	551	(prog_calc_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T13,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	434	(arb_host_gnt_err) ? 

Branches:

-1-	Status	Tests
1	Covered	T183,T184
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	557	(prog_op_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T13,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	154	if ((!rst_ni))
-2-:	156	if (ctrl_rsp_vld)
-3-:	158	if (inc_arb_cnt)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T5,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	167	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	206	if ((!rst_ni))
-2-:	208	if ((host_gnt_err_event | host_outstanding_err_event))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T194,T183,T181
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	218	if ((!rst_ni))
-2-:	220	if ((host_outstanding == '0))
-3-:	222	if (host_gnt_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T183,T184
0	0	0	Covered	T1,T5,T19

	LineNo.	Expression
-1-:	232	if ((!rst_ni))
-2-:	234	if (((host_outstanding == '0) && ctrl_fsm_idle))
-3-:	236	if (host_outstanding_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Not Covered
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	334	case (state_q)
-2-:	337	if (prim_mubi_pkg::mubi4_test_true_loose(flash_disable[FsmDisableIdx]))
-3-:	339	if ((ctrl_gnt && rd_i))
-4-:	341	if ((ctrl_gnt && prog_i))
-5-:	343	if (ctrl_gnt)
-6-:	350	if (rd_stage_data_valid)
-7-:	360	if (prog_ack)
-8-:	370	if (erase_ack)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
StIdle	1	-	-	-	-	-	-	Covered	T12,T13,T9
StIdle	0	1	-	-	-	-	-	Covered	T1,T2,T3
StIdle	0	0	1	-	-	-	-	Covered	T1,T2,T4
StIdle	0	0	0	1	-	-	-	Covered	T2,T12,T13
StIdle	0	0	0	0	-	-	-	Covered	T1,T2,T3
StCtrlRead	-	-	-	-	1	-	-	Covered	T1,T2,T3
StCtrlRead	-	-	-	-	0	-	-	Covered	T1,T2,T3
StCtrlProg	-	-	-	-	-	1	-	Covered	T1,T2,T4
StCtrlProg	-	-	-	-	-	0	-	Covered	T1,T2,T4
StCtrl	-	-	-	-	-	-	1	Covered	T2,T13,T47
StCtrl	-	-	-	-	-	-	0	Covered	T2,T12,T13
StDisable	-	-	-	-	-	-	-	Covered	T12,T13,T9
default	-	-	-	-	-	-	-	Covered	T15,T16,T17

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ArbCntMax_A	362988880	2382630	0	0
CtrlPrio_A	362988880	2382630	0	0
HostTransIdleChk_A	362988880	23091603	0	0
NoRemainder_A	991	991	0	0
OneHotReqs_A	362988880	362141048	0	0
Pow2Multiple_A	991	991	0	0
RdTxnCheck_A	362767218	361919386	0	0
u_state_regs_A	362988880	362141048	0	0

ArbCntMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	2382630	0	0
T5	48237	1425	0	0
T6	211270	0	0	0
T7	118703	4266	0	0
T8	51951	3543	0	0
T9	4629	0	0	0
T14	1518	0	0	0
T19	27848	0	0	0
T20	0	4284	0	0
T22	326081	10625	0	0
T30	0	3249	0	0
T45	0	1070	0	0
T46	0	8055	0	0
T47	10150	0	0	0
T48	171418	0	0	0
T59	0	48616	0	0
T154	0	5709	0	0

CtrlPrio_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	2382630	0	0
T5	48237	1425	0	0
T6	211270	0	0	0
T7	118703	4266	0	0
T8	51951	3543	0	0
T9	4629	0	0	0
T14	1518	0	0	0
T19	27848	0	0	0
T20	0	4284	0	0
T22	326081	10625	0	0
T30	0	3249	0	0
T45	0	1070	0	0
T46	0	8055	0	0
T47	10150	0	0	0
T48	171418	0	0	0
T59	0	48616	0	0
T154	0	5709	0	0

HostTransIdleChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	23091603	0	0
T1	3195	28	0	0
T2	107248	0	0	0
T3	2343	0	0	0
T4	260719	0	0	0
T5	48237	16435	0	0
T7	0	26744	0	0
T8	0	28016	0	0
T9	4629	0	0	0
T12	3575	0	0	0
T13	393400	0	0	0
T18	1295	0	0	0
T19	27848	207	0	0
T22	0	118110	0	0
T30	0	27527	0	0
T45	0	17121	0	0
T47	0	26	0	0
T49	0	23	0	0

NoRemainder_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	991	991	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

OneHotReqs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	362141048	0	0
T1	3195	3046	0	0
T2	107248	107243	0	0
T3	2343	2289	0	0
T4	260719	260646	0	0
T5	48237	48153	0	0
T9	4629	4128	0	0
T12	3575	2970	0	0
T13	393400	393388	0	0
T18	1295	1226	0	0
T19	27848	27793	0	0

Pow2Multiple_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	991	991	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

RdTxnCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362767218	361919386	0	0
T1	3195	3046	0	0
T2	107248	107243	0	0
T3	2343	2289	0	0
T4	260719	260646	0	0
T5	48237	48153	0	0
T9	4629	4128	0	0
T12	3575	2970	0	0
T13	393400	393388	0	0
T18	1295	1226	0	0
T19	27848	27793	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362988880	362141048	0	0
T1	3195	3046	0	0
T2	107248	107243	0	0
T3	2343	2289	0	0
T4	260719	260646	0	0
T5	48237	48153	0	0
T9	4629	4128	0	0
T12	3575	2970	0	0
T13	393400	393388	0	0
T18	1295	1226	0	0
T19	27848	27793	0	0