Unified Coverage Report :: Module :: flash_phy

Module : flash_phy

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.26	97.67	85.11			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash	94.26	97.67	85.11			100.00

---

Module Instance : tb.dut.u_eflash

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.26	97.67	85.11			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.44	98.01	93.28	99.62	97.62	97.70	98.44

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.22	97.14	92.20	98.44		100.00	98.33	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flash_cores[0].u_core	97.92	97.89	93.73	100.00	100.00	97.94	97.98
gen_flash_cores[0].u_host_rsp_fifo	97.84	100.00	89.19	100.00		100.00	100.00
gen_flash_cores[1].u_core	97.36	97.65	92.66	98.97	100.00	96.91	97.98
gen_flash_cores[1].u_host_rsp_fifo	96.76	100.00	83.78	100.00		100.00	100.00
u_bank_sequence_fifo	95.19	100.00	80.77			100.00	100.00
u_disable_buf	100.00	100.00					100.00
u_flash	97.33	98.05	94.40	100.00	93.75	97.78	100.00
u_lc_nvm_debug_en_sync	100.00	100.00				100.00	100.00
u_region_sel	100.00	100.00	100.00			100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : flash_phy

	Line No.	Total	Covered	Percent
TOTAL		43	42	97.67
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	129	0	0
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	135	1	1	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	174	1	1	100.00
CONT_ASSIGN	174	1	1	100.00
CONT_ASSIGN	174	1	1	100.00
CONT_ASSIGN	174	1	1	100.00
CONT_ASSIGN	174	1	1	100.00
CONT_ASSIGN	174	1	1	100.00
CONT_ASSIGN	174	1	1	100.00
CONT_ASSIGN	174	1	1	100.00
CONT_ASSIGN	174	1	1	100.00
CONT_ASSIGN	189	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	205	1	1	100.00
CONT_ASSIGN	206	1	1	100.00
CONT_ASSIGN	223	1	1	100.00
CONT_ASSIGN	223	1	1	100.00
CONT_ASSIGN	247	1	1	100.00
CONT_ASSIGN	247	1	1	100.00
CONT_ASSIGN	248	1	1	100.00
CONT_ASSIGN	248	1	1	100.00
CONT_ASSIGN	311	0	0
CONT_ASSIGN	327	1	1	100.00
CONT_ASSIGN	367	1	1	100.00
CONT_ASSIGN	370	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
117	1	1
118	1	1
121	1	1
124	1	1
125	1	1
126	1	1
129		unreachable
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
143	1	1
174	9	9
189	1	1
195	1	1
197	1	1
205	1	1
206	1	1
223	2	2
247	2	2
248	2	2
311		unreachable
327	1	1
367	1	1
370	0	1

---

Cond Coverage for Module : flash_phy

	Total	Covered	Percent
Conditions	47	40	85.11
Logical	47	40	85.11
Non-Logical	0	0
Event	0	0

 LINE       117
 EXPRESSION (host_req_i ? host_addr_i[(flash_ctrl_pkg::BusAddrW - 1)-:flash_ctrl_pkg::BankW] : '0)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T19

 LINE       121
 EXPRESSION (host_req_rdy[host_bank_sel] & host_rsp_avail[host_bank_sel] & seq_fifo_rdy)
             -------------1-------------   --------------2--------------   ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T5,T19

 LINE       124
 EXPRESSION (seq_fifo_pending & host_rsp_vld[rsp_bank_sel])
             --------1-------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T132,T133
1	0	Covered	T1,T5,T19
1	1	Covered	T1,T5,T19

 LINE       151
 EXPRESSION (host_req_i & host_req_rdy_o)
             -----1----   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T7,T8
1	1	Covered	T1,T5,T19

 LINE       223
 EXPRESSION (host_req_done_o & (rsp_bank_sel == 0))
             -------1-------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T19,T7
1	1	Covered	T1,T5,T19

 LINE       223
 SUB-EXPRESSION (rsp_bank_sel == 0)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       223
 EXPRESSION (host_req_done_o & (rsp_bank_sel == 1))
             -------1-------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T5,T19,T7
1	0	Covered	T1,T5,T19
1	1	Covered	T5,T19,T7

 LINE       223
 SUB-EXPRESSION (rsp_bank_sel == 1)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T19,T7

 LINE       247
 EXPRESSION (host_req_i & (host_bank_sel == 0) & host_rsp_avail[0])
             -----1----   ----------2---------   --------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T19,T7
1	1	0	Covered	T22,T45,T46
1	1	1	Covered	T1,T5,T19

 LINE       247
 SUB-EXPRESSION (host_bank_sel == 0)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       247
 EXPRESSION (host_req_i & (host_bank_sel == 1) & host_rsp_avail[1])
             -----1----   ----------2---------   --------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T5,T19
1	1	0	Covered	T22,T46,T20
1	1	1	Covered	T5,T19,T7

 LINE       247
 SUB-EXPRESSION (host_bank_sel == 1)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T19,T7

 LINE       248
 EXPRESSION (flash_ctrl_i.req & (ctrl_bank_sel == 0))
             --------1-------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T13
1	1	Covered	T1,T2,T3

 LINE       248
 SUB-EXPRESSION (ctrl_bank_sel == 0)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       248
 EXPRESSION (flash_ctrl_i.req & (ctrl_bank_sel == 1))
             --------1-------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T13

 LINE       248
 SUB-EXPRESSION (ctrl_bank_sel == 1)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T13

 LINE       367
 EXPRESSION (flash_ctrl_i.alert_trig & flash_ctrl_i.alert_ack)
             -----------1-----------   -----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

Branch Coverage for Module : flash_phy

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	117	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	117	(host_req_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T19
0	Covered	T1,T2,T3