Assertions
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Assertions by Category
ASSERTPROPERTIESSEQUENCES
Total995010
Category 0995010

Assertions by Severity
ASSERTPROPERTIESSEQUENCES
Total995010
Severity 0995010

Summary for Assertions
NUMBERPERCENT
Total Number995100.00
Uncovered171.71
Success97898.29
Failure00.00
Incomplete151.51
Without Attempts00.00

Summary for Cover Sequences
NUMBERPERCENT
Total Number10100.00
Uncovered330.00
All Matches770.00
First Matches770.00
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ASSERTIONS   CATEGORY   SEVERITY   ATTEMPTS   REAL SUCCESSES   FAILURES   INCOMPLETE   
tb.dut.u_tl_adapter_eflash.rvalidHighWhenRspFifoFull 00413288616459093000
tb.dut.u_tl_adapter_eflash.u_err.dataWidthOnly32_A 001060106000
tb.dut.u_tl_adapter_eflash.u_reqfifo.DataKnown_A 004132886163653554400
tb.dut.u_tl_adapter_eflash.u_reqfifo.DepthKnown_A 0041328861641243437200
tb.dut.u_tl_adapter_eflash.u_reqfifo.RvalidKnown_A 0041328861641243437200
tb.dut.u_tl_adapter_eflash.u_reqfifo.WreadyKnown_A 0041328861641243437200
tb.dut.u_tl_adapter_eflash.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth 004132886163653554400
tb.dut.u_tl_adapter_eflash.u_rsp_gen.DataWidthCheck_A 001060106000
tb.dut.u_tl_adapter_eflash.u_rsp_gen.PayLoadWidthCheck 001060106000
tb.dut.u_tl_adapter_eflash.u_rspfifo.DataKnown_A 00413288616616051000
tb.dut.u_tl_adapter_eflash.u_rspfifo.DepthKnown_A 0041328861641243437200
tb.dut.u_tl_adapter_eflash.u_rspfifo.RvalidKnown_A 0041328861641243437200
tb.dut.u_tl_adapter_eflash.u_rspfifo.WreadyKnown_A 0041328861641243437200
tb.dut.u_tl_adapter_eflash.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth 00413288616616051000
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.DataKnown_A 004132886163496211300
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.DepthKnown_A 0041328861641243437200
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.RvalidKnown_A 0041328861641243437200
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.WreadyKnown_A 0041328861641243437200
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth 004132886163496211300
tb.dut.u_tl_gate.u_err_en_sync.NumCopiesMustBeGreaterZero_A 001060106000
tb.dut.u_tl_gate.u_err_en_sync.OutputsKnown_A 0040739446340654021900
tb.dut.u_tl_gate.u_err_en_sync.gen_no_flops.OutputDelay_A 0040739446340654021900
tb.dut.u_tl_gate.u_state_regs.AssertConnected_A 001060106000
tb.dut.u_tl_gate.u_state_regs_A 0041328861641243437200
tb.dut.u_tl_gate.u_tlul_err_resp.u_intg_gen.DataWidthCheck_A 001060106000
tb.dut.u_tl_gate.u_tlul_err_resp.u_intg_gen.PayLoadWidthCheck 001060106000
tb.dut.u_to_prog_fifo.AddrOutKnown_A 0041328861641243437200
tb.dut.u_to_prog_fifo.DataIntgOptions_A 001060106000
tb.dut.u_to_prog_fifo.ReqOutKnown_A 0041328861641243437200
tb.dut.u_to_prog_fifo.SramDwHasByteGranularity_A 001060106000
tb.dut.u_to_prog_fifo.SramDwIsMultipleOfTlulWidth_A 001060106000
tb.dut.u_to_prog_fifo.TlOutKnown_A 0041328861641243437200
tb.dut.u_to_prog_fifo.TlOutPayloadKnown_A 00413288616366467100
tb.dut.u_to_prog_fifo.TlOutPayloadKnown_AKnownEnable 0041328861641243437200
tb.dut.u_to_prog_fifo.WdataOutKnown_A 0041328861641243437200
tb.dut.u_to_prog_fifo.WeOutKnown_A 0041328861641243437200
tb.dut.u_to_prog_fifo.WmaskOutKnown_A 0041328861641243437200
tb.dut.u_to_prog_fifo.adapterNoReadOrWrite 001060106000
tb.dut.u_to_prog_fifo.u_err.dataWidthOnly32_A 001060106000
tb.dut.u_to_prog_fifo.u_reqfifo.DataKnown_A 00413288616366467100
tb.dut.u_to_prog_fifo.u_reqfifo.DepthKnown_A 0041328861641243437200
tb.dut.u_to_prog_fifo.u_reqfifo.RvalidKnown_A 0041328861641243437200
tb.dut.u_to_prog_fifo.u_reqfifo.WreadyKnown_A 0041328861641243437200
tb.dut.u_to_prog_fifo.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth 00413288616366467100
tb.dut.u_to_prog_fifo.u_rsp_gen.DataWidthCheck_A 001060106000
tb.dut.u_to_prog_fifo.u_rsp_gen.PayLoadWidthCheck 001060106000
tb.dut.u_to_prog_fifo.u_rspfifo.DepthKnown_A 0041328861641243437200
tb.dut.u_to_prog_fifo.u_rspfifo.RvalidKnown_A 0041328861641243437200
tb.dut.u_to_prog_fifo.u_rspfifo.WreadyKnown_A 0041328861641243437200
tb.dut.u_to_prog_fifo.u_sramreqfifo.DepthKnown_A 0041328861641243437200
tb.dut.u_to_prog_fifo.u_sramreqfifo.RvalidKnown_A 0041328861641243437200
tb.dut.u_to_prog_fifo.u_sramreqfifo.WreadyKnown_A 0041328861641243437200
tb.dut.u_to_rd_fifo.AddrOutKnown_A 0041328861641243437200
tb.dut.u_to_rd_fifo.DataIntgOptions_A 001060106000
tb.dut.u_to_rd_fifo.ReqOutKnown_A 0041328861641243437200
tb.dut.u_to_rd_fifo.SramDwHasByteGranularity_A 001060106000
tb.dut.u_to_rd_fifo.SramDwIsMultipleOfTlulWidth_A 001060106000
tb.dut.u_to_rd_fifo.TlOutKnown_A 0041328861641243437200
tb.dut.u_to_rd_fifo.TlOutPayloadKnown_A 00413288616494017500
tb.dut.u_to_rd_fifo.TlOutPayloadKnown_AKnownEnable 0041328861641243437200
tb.dut.u_to_rd_fifo.WdataOutKnown_A 0041328861641243437200
tb.dut.u_to_rd_fifo.WeOutKnown_A 0041328861641243437200
tb.dut.u_to_rd_fifo.WmaskOutKnown_A 0041328861641243437200
tb.dut.u_to_rd_fifo.adapterNoReadOrWrite 001060106000
tb.dut.u_to_rd_fifo.rvalidHighReqFifoEmpty 00413288616330129100
tb.dut.u_to_rd_fifo.rvalidHighWhenRspFifoFull 00412711616329483200
tb.dut.u_to_rd_fifo.u_err.dataWidthOnly32_A 001060106000
tb.dut.u_to_rd_fifo.u_reqfifo.DataKnown_A 00413288616494017500
tb.dut.u_to_rd_fifo.u_reqfifo.DepthKnown_A 0041328861641243437200
tb.dut.u_to_rd_fifo.u_reqfifo.RvalidKnown_A 0041328861641243437200
tb.dut.u_to_rd_fifo.u_reqfifo.WreadyKnown_A 0041328861641243437200
tb.dut.u_to_rd_fifo.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth 00413288616494017500
tb.dut.u_to_rd_fifo.u_rsp_gen.DataWidthCheck_A 001060106000
tb.dut.u_to_rd_fifo.u_rsp_gen.PayLoadWidthCheck 001060106000
tb.dut.u_to_rd_fifo.u_rspfifo.DataKnown_A 00413121015493241300
tb.dut.u_to_rd_fifo.u_rspfifo.DepthKnown_A 0041328861641243437200
tb.dut.u_to_rd_fifo.u_rspfifo.RvalidKnown_A 0041328861641243437200
tb.dut.u_to_rd_fifo.u_rspfifo.WreadyKnown_A 0041328861641243437200
tb.dut.u_to_rd_fifo.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth 00413288616494180300
tb.dut.u_to_rd_fifo.u_sramreqfifo.DataKnown_A 00413288616330129100
tb.dut.u_to_rd_fifo.u_sramreqfifo.DepthKnown_A 0041328861641243437200
tb.dut.u_to_rd_fifo.u_sramreqfifo.RvalidKnown_A 0041328861641243437200
tb.dut.u_to_rd_fifo.u_sramreqfifo.WreadyKnown_A 0041328861641243437200
tb.dut.u_to_rd_fifo.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth 00413288616330129100

Assertions Incomplete:
ASSERTIONS   CATEGORY   SEVERITY   ATTEMPTS   REAL SUCCESSES   FAILURES   INCOMPLETE   SRC   
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.RoundRobin_A 004132886163583101053
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.RoundRobin_A 004132886163050301053
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_flops.OutputDelay_A 0040739446340650681702769
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.RoundRobin_A 00413288616001053
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.RoundRobin_A 00413288616001053
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.RoundRobin_A 00413288616001053
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.RoundRobin_A 00413288616001053
tb.dut.u_flash_hw_if.DisableChk_A 004009725353810119050
tb.dut.u_flash_hw_if.u_sync_rma_req.gen_flops.OutputDelay_A 0040739449740650683602769
tb.dut.u_lc_escalation_en_sync.gen_flops.OutputDelay_A 0040737077640648326502619
tb.dut.u_lc_seed_hw_rd_en_sync.gen_flops.OutputDelay_A 0040739449740650683602769
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_flops.OutputDelay_A 0040739449740650683602769
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_flops.OutputDelay_A 0040739449740650683602769
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_flops.OutputDelay_A 0040739449740650683602769
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_flops.OutputDelay_A 0040739449740650683602769

Detail Report for Cover Sequences

Cover Sequences Uncovered:
COVER SEQUENCES   CATEGORY   SEVERITY   ATTEMPTS   ALL MATCHES   FIRST MATCHES   INCOMPLETE   SRC   
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C 00415472149000
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C 00415472149000
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C 00415472149000

Cover Sequences All Matches:
COVER SEQUENCES   CATEGORY   SEVERITY   ATTEMPTS   ALL MATCHES   FIRST MATCHES   INCOMPLETE   SRC   
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C 004154721491130711130710
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C 0041547214928280
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C 0041547214912120
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C 0041547214922220
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C 0041547214913389133890
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C 004154721492726492726490
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C 0041547214916993153169931531248

Cover Sequences First Matches:
COVER SEQUENCES   CATEGORY   SEVERITY   ATTEMPTS   ALL MATCHES   FIRST MATCHES   INCOMPLETE   SRC   
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C 004154721491130711130710
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C 0041547214928280
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C 0041547214912120
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C 0041547214922220
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C 0041547214913389133890
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C 004154721492726492726490
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C 0041547214916993153169931531248