FLASH_CTRL Simulation Results

Thursday March 28 2024 19:02:20 UTC

GitHub Revision: 4ee21f808f

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 29834210046083588839632889378999422318513504283488100050460647435812066910143

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.681m	97.271us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.760s	47.672us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	46.860s	41.040us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	17.380s	53.885us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.065m	1.272ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.083m	4.978ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	19.760s	197.408us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	17.380s	53.885us	20	20	100.00
		flash_ctrl_csr_aliasing	1.083m	4.978ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.840s	22.562us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	14.080s	28.171us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	27.820s	21.534us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	2.075m	268.803us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	36.795m	1.334s	3	3	100.00
		flash_ctrl_hw_rma_reset	16.621m	270.265ms	20	20	100.00
		flash_ctrl_lcmgr_intg	14.180s	25.869us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	50.000m	290.655ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	8.052m	29.983ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	15.010s	35.384us	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	1.182h	49.893ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	2.584m	2.819ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	36.140s	635.629us	38	40	95.00
		flash_ctrl_rw_evict_all_en	38.400s	115.483us	39	40	97.50
		flash_ctrl_re_evict	40.520s	483.068us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	10.270m	4.081ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	10.270m	4.081ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	21.314m	64.203ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	29.450s	2.115ms	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	19.116m	3.223ms	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	40.700m	8.799ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	17.135m	1.555ms	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	49.703m	6.294ms	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	13.980s	32.295us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	4.228m	3.286ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	22.670s	26.986us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.520s	13.947us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	27.364m	819.576us	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.863m	3.414ms	50	50	100.00
		flash_ctrl_otp_reset	2.258m	229.357us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	36.795m	1.334s	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	3.997m	2.512ms	40	40	100.00
		flash_ctrl_intr_wr	1.764m	9.528ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	5.544m	8.490ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	8.977m	239.828ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.825m	8.864ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.242m	1.344ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	22.630s	29.378us	5	5	100.00
		flash_ctrl_ro_derr	3.123m	647.659us	10	10	100.00
		flash_ctrl_rw_derr	10.354m	3.436ms	10	10	100.00
		flash_ctrl_derr_detect	1.780m	491.100us	5	5	100.00
		flash_ctrl_integrity	10.947m	16.464ms	5	5	100.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	22.580s	99.380us	5	5	100.00
		flash_ctrl_ro_serr	3.113m	1.387ms	10	10	100.00
		flash_ctrl_rw_serr	11.199m	43.116ms	10	10	100.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.098m	1.875ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.286m	722.644us	5	5	100.00
V2	scramble	flash_ctrl_wo	3.659m	9.329ms	20	20	100.00
		flash_ctrl_write_word_sweep	17.240s	126.011us	1	1	100.00
		flash_ctrl_read_word_sweep	13.310s	96.166us	1	1	100.00
		flash_ctrl_ro	2.180m	6.886ms	20	20	100.00
		flash_ctrl_rw	9.715m	32.970ms	20	20	100.00
V2	filesystem_support	flash_ctrl_fs_sup	39.920s	1.080ms	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	16.483m	42.158ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	5.170m	10.012ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	14.190s	34.763us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	13.940s	32.058us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	20.130s	57.238us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	20.130s	57.238us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	46.860s	41.040us	5	5	100.00
		flash_ctrl_csr_rw	17.380s	53.885us	20	20	100.00
		flash_ctrl_csr_aliasing	1.083m	4.978ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	35.740s	641.605us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	46.860s	41.040us	5	5	100.00
		flash_ctrl_csr_rw	17.380s	53.885us	20	20	100.00
		flash_ctrl_csr_aliasing	1.083m	4.978ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	35.740s	641.605us	20	20	100.00
V2		TOTAL			1010	1013	99.70
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	16.520s	21.830us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	16.520s	21.830us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	16.520s	21.830us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	16.520s	21.830us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	15.890s	72.204us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.342h	2.640ms	5	5	100.00
		flash_ctrl_tl_intg_err	15.343m	2.967ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.343m	2.967ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.343m	2.967ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	31.570s	208.555us	3	3	100.00
		flash_ctrl_wr_intg	14.870s	181.889us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.681m	97.271us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.258m	229.357us	80	80	100.00
		flash_ctrl_disable	22.670s	26.986us	50	50	100.00
		flash_ctrl_sec_info_access	1.453m	3.416ms	50	50	100.00
		flash_ctrl_connect	16.520s	13.947us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	14.140s	27.849us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	17.380s	53.885us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.520s	21.830us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	17.380s	53.885us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.520s	21.830us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	17.380s	53.885us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	16.520s	21.830us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	22.670s	26.986us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	31.570s	208.555us	3	3	100.00
		flash_ctrl_access_after_disable	13.770s	22.329us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	22.670s	26.986us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	29.450s	2.115ms	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	9.715m	32.970ms	20	20	100.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	11.199m	43.116ms	10	10	100.00
		flash_ctrl_rw_derr	10.354m	3.436ms	10	10	100.00
		flash_ctrl_integrity	10.947m	16.464ms	5	5	100.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	36.795m	1.334s	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.342h	2.640ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.342h	2.640ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.342h	2.640ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.342h	2.640ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	1.502m	814.719us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.330s	134.766us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	14.110s	24.697us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.342h	2.640ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.342h	2.640ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.342h	2.640ms	5	5	100.00
V2S		TOTAL			144	144	100.00
V3	asymmetric_read_path	flash_ctrl_rd_ooo	47.710s	99.154us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1275	1278	99.77

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	53	96.36
V2S	12	12	12	100.00
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.17	95.29	94.06	98.85	91.84	97.02	98.01	98.12

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: * has 2 failures:

  • Test flash_ctrl_rw_evict has 2 failures.

    • 20.flash_ctrl_rw_evict.21676051858538895704338805416875007620037511745246690735262376653640009911244
      Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/20.flash_ctrl_rw_evict/latest/run.log

        UVM_ERROR @ 35980.7 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: 0x0
        UVM_INFO @ 35980.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 33.flash_ctrl_rw_evict.6258423902545824203801744172273763281053544001576906291853013870796038749026
      Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/33.flash_ctrl_rw_evict/latest/run.log

        UVM_ERROR @ 13059.5 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: 0x0
        UVM_INFO @ 13059.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 1 failures:

  • Test flash_ctrl_rw_evict_all_en has 1 failures.

    • 16.flash_ctrl_rw_evict_all_en.15211496324601784163277018145790679980165721144381819225252614888120570655149
      Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/16.flash_ctrl_rw_evict_all_en/latest/run.log

        UVM_ERROR @ 13206.0 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
        UVM_INFO @ 13206.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• lint
• 2024.03.27_04.32.47
• 2024.03.25_03.49.38
• 2024.03.22_04.27.49
• 2024.03.20_03.31.50
• 2024.03.18_04.29.22
• 2024.03.15_00.03.50