FLASH_CTRL Simulation Results

Sunday March 17 2024 19:02:52 UTC

GitHub Revision: c187a82ee8

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 28440605375541353837496064678278045899395893237469128852560697715229879921060

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.550m	167.733us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.660s	15.991us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	45.350s	93.854us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	17.790s	54.114us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.406m	4.864ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.179m	1.761ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	20.650s	108.242us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	17.790s	54.114us	20	20	100.00
		flash_ctrl_csr_aliasing	1.179m	1.761ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.660s	95.704us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	14.010s	168.095us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	27.500s	22.459us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	2.030m	67.777us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	28.781m	212.928ms	3	3	100.00
		flash_ctrl_hw_rma_reset	14.695m	160.189ms	20	20	100.00
		flash_ctrl_lcmgr_intg	13.820s	124.867us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	50.921m	287.014ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	9.208m	6.971ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	5.749m	8.633ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	1.195h	122.279ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	2.570m	2.803ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	35.590s	247.258us	40	40	100.00
		flash_ctrl_rw_evict_all_en	37.490s	338.932us	39	40	97.50
		flash_ctrl_re_evict	39.260s	222.092us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	9.467m	5.747ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	9.467m	5.747ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	19.731m	69.024ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	28.570s	533.989us	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	17.700m	131.401us	19	20	95.00
V2	error_mp	flash_ctrl_error_mp	39.647m	4.443ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	15.107m	2.631ms	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	41.929m	624.899us	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	14.140s	15.005us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	3.563m	1.148ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	23.330s	65.014us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.580s	232.998us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	29.916m	277.165us	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.211m	6.384ms	50	50	100.00
		flash_ctrl_otp_reset	2.321m	40.509us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	28.781m	212.928ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	4.184m	2.389ms	40	40	100.00
		flash_ctrl_intr_wr	2.010m	14.407ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	4.981m	8.762ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	9.120m	187.132ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.732m	2.507ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.270m	4.024ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	23.740s	32.501us	5	5	100.00
		flash_ctrl_ro_derr	2.554m	2.424ms	10	10	100.00
		flash_ctrl_rw_derr	11.889m	9.025ms	10	10	100.00
		flash_ctrl_derr_detect	1.780m	169.732us	5	5	100.00
		flash_ctrl_integrity	11.488m	45.228ms	5	5	100.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	22.890s	130.537us	5	5	100.00
		flash_ctrl_ro_serr	2.672m	2.830ms	10	10	100.00
		flash_ctrl_rw_serr	13.103m	40.214ms	10	10	100.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.235m	659.057us	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.501m	1.702ms	5	5	100.00
V2	scramble	flash_ctrl_wo	3.472m	2.567ms	20	20	100.00
		flash_ctrl_write_word_sweep	16.590s	64.086us	1	1	100.00
		flash_ctrl_read_word_sweep	14.230s	77.807us	1	1	100.00
		flash_ctrl_ro	1.894m	716.061us	20	20	100.00
		flash_ctrl_rw	11.831m	83.761ms	20	20	100.00
V2	filesystem_support	flash_ctrl_fs_sup	37.590s	637.052us	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	13.674m	79.019ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	5.418m	10.012ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	14.440s	237.355us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	14.190s	45.688us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	20.280s	234.850us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	20.280s	234.850us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	45.350s	93.854us	5	5	100.00
		flash_ctrl_csr_rw	17.790s	54.114us	20	20	100.00
		flash_ctrl_csr_aliasing	1.179m	1.761ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	34.350s	170.119us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	45.350s	93.854us	5	5	100.00
		flash_ctrl_csr_rw	17.790s	54.114us	20	20	100.00
		flash_ctrl_csr_aliasing	1.179m	1.761ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	34.350s	170.119us	20	20	100.00
V2		TOTAL			1011	1013	99.80
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	16.230s	32.360us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	16.230s	32.360us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	16.230s	32.360us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	16.230s	32.360us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.370s	15.805us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.353h	4.067ms	5	5	100.00
		flash_ctrl_tl_intg_err	15.337m	819.597us	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.337m	819.597us	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.337m	819.597us	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	33.250s	76.714us	3	3	100.00
		flash_ctrl_wr_intg	15.020s	82.213us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.550m	167.733us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.321m	40.509us	80	80	100.00
		flash_ctrl_disable	23.330s	65.014us	50	50	100.00
		flash_ctrl_sec_info_access	1.487m	10.156ms	50	50	100.00
		flash_ctrl_connect	16.580s	232.998us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	14.280s	26.026us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	17.790s	54.114us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.230s	32.360us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	17.790s	54.114us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.230s	32.360us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	17.790s	54.114us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	16.230s	32.360us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	23.330s	65.014us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	33.250s	76.714us	3	3	100.00
		flash_ctrl_access_after_disable	14.160s	18.424us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	23.330s	65.014us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	28.570s	533.989us	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	11.831m	83.761ms	20	20	100.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	13.103m	40.214ms	10	10	100.00
		flash_ctrl_rw_derr	11.889m	9.025ms	10	10	100.00
		flash_ctrl_integrity	11.488m	45.228ms	5	5	100.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	28.781m	212.928ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.353h	4.067ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.353h	4.067ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.353h	4.067ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.353h	4.067ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	36.690s	725.153us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.470s	162.771us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	14.690s	15.261us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.353h	4.067ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.353h	4.067ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.353h	4.067ms	5	5	100.00
V2S		TOTAL			144	144	100.00
V3	asymmetric_read_path	flash_ctrl_rd_ooo	43.580s	194.044us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1276	1278	99.84

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	53	96.36
V2S	12	12	12	100.00
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.59	95.77	94.20	98.95	92.52	98.26	98.30	98.15

Failure Buckets

• UVM_ERROR (flash_ctrl_scoreboard.sv:736) [scoreboard] Check failed exp_data_part[addr] == data (* [*] vs * [*]) read addr:* data: * has 1 failures:

  • Test flash_ctrl_rand_ops has 1 failures.

    • 2.flash_ctrl_rand_ops.64445552233172733123399154467071249272258060822919628468974001920395055116946
      Line 2257, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_rand_ops/latest/run.log

        UVM_ERROR @ 274110.3 ns: (flash_ctrl_scoreboard.sv:736) [uvm_test_top.env.scoreboard] Check failed exp_data_part[addr] == data (1384616206 [0x5287910e] vs 1549650542 [0x5c5dca6e]) read addr:0x80140 data: 0x5c5dca6e
        UVM_INFO @ 274110.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 1 failures:

  • Test flash_ctrl_rw_evict_all_en has 1 failures.

    • 5.flash_ctrl_rw_evict_all_en.80657978677888900148481813832376843212016090333953614851628457213870219412475
      Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_rw_evict_all_en/latest/run.log

        UVM_ERROR @ 87101.8 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
        UVM_INFO @ 87101.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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