e844018f2c| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | flash_ctrl_smoke | 0 | 50 | 0.00 | ||
| V1 | smoke_hw | flash_ctrl_smoke_hw | 0 | 5 | 0.00 | ||
| V1 | csr_hw_reset | flash_ctrl_csr_hw_reset | 45.880s | 46.779us | 5 | 5 | 100.00 |
| V1 | csr_rw | flash_ctrl_csr_rw | 17.340s | 45.741us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | flash_ctrl_csr_bit_bash | 1.426m | 9.087ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | flash_ctrl_csr_aliasing | 1.041m | 1.625ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | flash_ctrl_csr_mem_rw_with_rand_reset | 19.520s | 155.323us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | flash_ctrl_csr_rw | 17.340s | 45.741us | 20 | 20 | 100.00 |
| flash_ctrl_csr_aliasing | 1.041m | 1.625ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | flash_ctrl_mem_walk | 13.520s | 66.701us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | flash_ctrl_mem_partial_access | 13.530s | 31.631us | 5 | 5 | 100.00 |
| V1 | TOTAL | 65 | 120 | 54.17 | |||
| V2 | sw_op | flash_ctrl_sw_op | 0 | 5 | 0.00 | ||
| V2 | host_read_direct | flash_ctrl_host_dir_rd | 0 | 5 | 0.00 | ||
| V2 | rma_hw_if | flash_ctrl_hw_rma | 0 | 3 | 0.00 | ||
| flash_ctrl_hw_rma_reset | 0 | 20 | 0.00 | ||||
| flash_ctrl_lcmgr_intg | 0 | 20 | 0.00 | ||||
| V2 | host_controller_arb | flash_ctrl_host_ctrl_arb | 0 | 5 | 0.00 | ||
| V2 | erase_suspend | flash_ctrl_erase_suspend | 0 | 5 | 0.00 | ||
| V2 | program_reset | flash_ctrl_prog_reset | 0 | 30 | 0.00 | ||
| V2 | full_memory_access | flash_ctrl_full_mem_access | 0 | 5 | 0.00 | ||
| V2 | rd_buff_eviction | flash_ctrl_rd_buff_evict | 0 | 5 | 0.00 | ||
| V2 | rd_buff_eviction_w_ecc | flash_ctrl_rw_evict | 0 | 40 | 0.00 | ||
| flash_ctrl_rw_evict_all_en | 0 | 40 | 0.00 | ||||
| flash_ctrl_re_evict | 0 | 20 | 0.00 | ||||
| V2 | host_arb | flash_ctrl_phy_arb | 0 | 20 | 0.00 | ||
| V2 | host_interleave | flash_ctrl_phy_arb | 0 | 20 | 0.00 | ||
| V2 | memory_protection | flash_ctrl_mp_regions | 0 | 20 | 0.00 | ||
| V2 | fetch_code | flash_ctrl_fetch_code | 0 | 10 | 0.00 | ||
| V2 | all_partitions | flash_ctrl_rand_ops | 0 | 20 | 0.00 | ||
| V2 | error_mp | flash_ctrl_error_mp | 0 | 10 | 0.00 | ||
| V2 | error_prog_win | flash_ctrl_error_prog_win | 0 | 10 | 0.00 | ||
| V2 | error_prog_type | flash_ctrl_error_prog_type | 0 | 5 | 0.00 | ||
| V2 | error_read_seed | flash_ctrl_hw_read_seed_err | 0 | 20 | 0.00 | ||
| V2 | read_write_overflow | flash_ctrl_oversize_error | 0 | 5 | 0.00 | ||
| V2 | flash_ctrl_disable | flash_ctrl_disable | 0 | 50 | 0.00 | ||
| V2 | flash_ctrl_connect | flash_ctrl_connect | 0 | 80 | 0.00 | ||
| V2 | stress_all | flash_ctrl_stress_all | 0 | 5 | 0.00 | ||
| V2 | secret_partition | flash_ctrl_hw_sec_otp | 0 | 50 | 0.00 | ||
| flash_ctrl_otp_reset | 0 | 80 | 0.00 | ||||
| V2 | isolation_partition | flash_ctrl_hw_rma | 0 | 3 | 0.00 | ||
| V2 | interrupts | flash_ctrl_intr_rd | 0 | 40 | 0.00 | ||
| flash_ctrl_intr_wr | 0 | 10 | 0.00 | ||||
| flash_ctrl_intr_rd_slow_flash | 0 | 40 | 0.00 | ||||
| flash_ctrl_intr_wr_slow_flash | 0 | 10 | 0.00 | ||||
| V2 | invalid_op | flash_ctrl_invalid_op | 0 | 20 | 0.00 | ||
| V2 | mid_op_rst | flash_ctrl_mid_op_rst | 0 | 5 | 0.00 | ||
| V2 | double_bit_err | flash_ctrl_read_word_sweep_derr | 0 | 5 | 0.00 | ||
| flash_ctrl_ro_derr | 0 | 10 | 0.00 | ||||
| flash_ctrl_rw_derr | 0 | 10 | 0.00 | ||||
| flash_ctrl_derr_detect | 0 | 5 | 0.00 | ||||
| flash_ctrl_integrity | 0 | 5 | 0.00 | ||||
| V2 | single_bit_err | flash_ctrl_read_word_sweep_serr | 0 | 5 | 0.00 | ||
| flash_ctrl_ro_serr | 0 | 10 | 0.00 | ||||
| flash_ctrl_rw_serr | 0 | 10 | 0.00 | ||||
| V2 | singlebit_err_counter | flash_ctrl_serr_counter | 0 | 5 | 0.00 | ||
| V2 | singlebit_err_address | flash_ctrl_serr_address | 0 | 5 | 0.00 | ||
| V2 | scramble | flash_ctrl_wo | 0 | 20 | 0.00 | ||
| flash_ctrl_write_word_sweep | 0 | 1 | 0.00 | ||||
| flash_ctrl_read_word_sweep | 0 | 1 | 0.00 | ||||
| flash_ctrl_ro | 0 | 20 | 0.00 | ||||
| flash_ctrl_rw | 0 | 20 | 0.00 | ||||
| V2 | filesystem_support | flash_ctrl_fs_sup | 0 | 5 | 0.00 | ||
| V2 | rma_write_process_error | flash_ctrl_rma_err | 0 | 3 | 0.00 | ||
| flash_ctrl_hw_prog_rma_wipe_err | 0 | 20 | 0.00 | ||||
| V2 | alert_test | flash_ctrl_alert_test | 0 | 50 | 0.00 | ||
| V2 | intr_test | flash_ctrl_intr_test | 13.760s | 14.773us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | flash_ctrl_tl_errors | 19.380s | 52.014us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | flash_ctrl_tl_errors | 19.380s | 52.014us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | flash_ctrl_csr_hw_reset | 45.880s | 46.779us | 5 | 5 | 100.00 |
| flash_ctrl_csr_rw | 17.340s | 45.741us | 20 | 20 | 100.00 | ||
| flash_ctrl_csr_aliasing | 1.041m | 1.625ms | 5 | 5 | 100.00 | ||
| flash_ctrl_same_csr_outstanding | 34.440s | 2.562ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | flash_ctrl_csr_hw_reset | 45.880s | 46.779us | 5 | 5 | 100.00 |
| flash_ctrl_csr_rw | 17.340s | 45.741us | 20 | 20 | 100.00 | ||
| flash_ctrl_csr_aliasing | 1.041m | 1.625ms | 5 | 5 | 100.00 | ||
| flash_ctrl_same_csr_outstanding | 34.440s | 2.562ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 90 | 1013 | 8.88 | |||
| V2S | shadow_reg_update_error | flash_ctrl_shadow_reg_errors | 16.080s | 40.284us | 20 | 20 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | flash_ctrl_shadow_reg_errors | 16.080s | 40.284us | 20 | 20 | 100.00 |
| V2S | shadow_reg_storage_error | flash_ctrl_shadow_reg_errors | 16.080s | 40.284us | 20 | 20 | 100.00 |
| V2S | shadowed_reset_glitch | flash_ctrl_shadow_reg_errors | 16.080s | 40.284us | 20 | 20 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | flash_ctrl_shadow_reg_errors_with_csr_rw | 15.930s | 25.356us | 20 | 20 | 100.00 |
| V2S | tl_intg_err | flash_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| flash_ctrl_tl_intg_err | 15.261m | 2.608ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_reg_bus_integrity | flash_ctrl_tl_intg_err | 15.261m | 2.608ms | 20 | 20 | 100.00 |
| V2S | sec_cm_host_bus_integrity | flash_ctrl_tl_intg_err | 15.261m | 2.608ms | 20 | 20 | 100.00 |
| V2S | sec_cm_mem_bus_integrity | flash_ctrl_rd_intg | 0 | 3 | 0.00 | ||
| flash_ctrl_wr_intg | 0 | 3 | 0.00 | ||||
| V2S | sec_cm_scramble_key_sideload | flash_ctrl_smoke | 0 | 50 | 0.00 | ||
| V2S | sec_cm_lc_ctrl_intersig_mubi | flash_ctrl_otp_reset | 0 | 80 | 0.00 | ||
| flash_ctrl_disable | 0 | 50 | 0.00 | ||||
| flash_ctrl_sec_info_access | 0 | 50 | 0.00 | ||||
| flash_ctrl_connect | 0 | 80 | 0.00 | ||||
| V2S | sec_cm_ctrl_config_regwen | flash_ctrl_config_regwen | 0 | 5 | 0.00 | ||
| V2S | sec_cm_data_regions_config_regwen | flash_ctrl_csr_rw | 17.340s | 45.741us | 20 | 20 | 100.00 |
| V2S | sec_cm_data_regions_config_shadow | flash_ctrl_shadow_reg_errors | 16.080s | 40.284us | 20 | 20 | 100.00 |
| V2S | sec_cm_info_regions_config_regwen | flash_ctrl_csr_rw | 17.340s | 45.741us | 20 | 20 | 100.00 |
| V2S | sec_cm_info_regions_config_shadow | flash_ctrl_shadow_reg_errors | 16.080s | 40.284us | 20 | 20 | 100.00 |
| V2S | sec_cm_bank_config_regwen | flash_ctrl_csr_rw | 17.340s | 45.741us | 20 | 20 | 100.00 |
| V2S | sec_cm_bank_config_shadow | flash_ctrl_shadow_reg_errors | 16.080s | 40.284us | 20 | 20 | 100.00 |
| V2S | sec_cm_mem_ctrl_global_esc | flash_ctrl_disable | 0 | 50 | 0.00 | ||
| V2S | sec_cm_mem_ctrl_local_esc | flash_ctrl_rd_intg | 0 | 3 | 0.00 | ||
| flash_ctrl_access_after_disable | 0 | 3 | 0.00 | ||||
| V2S | sec_cm_mem_disable_config_mubi | flash_ctrl_disable | 0 | 50 | 0.00 | ||
| V2S | sec_cm_exec_config_redun | flash_ctrl_fetch_code | 0 | 10 | 0.00 | ||
| V2S | sec_cm_mem_scramble | flash_ctrl_rw | 0 | 20 | 0.00 | ||
| V2S | sec_cm_mem_integrity | flash_ctrl_rw_serr | 0 | 10 | 0.00 | ||
| flash_ctrl_rw_derr | 0 | 10 | 0.00 | ||||
| flash_ctrl_integrity | 0 | 5 | 0.00 | ||||
| V2S | sec_cm_rma_entry_mem_sec_wipe | flash_ctrl_hw_rma | 0 | 3 | 0.00 | ||
| V2S | sec_cm_ctrl_fsm_sparse | flash_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_phy_fsm_sparse | flash_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_phy_prog_fsm_sparse | flash_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_ctr_redun | flash_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_phy_arbiter_ctrl_redun | flash_ctrl_phy_arb_redun | 0 | 5 | 0.00 | ||
| V2S | sec_cm_phy_host_grant_ctrl_consistency | flash_ctrl_phy_host_grant_err | 0 | 5 | 0.00 | ||
| V2S | sec_cm_phy_ack_ctrl_consistency | flash_ctrl_phy_ack_consistency | 0 | 5 | 0.00 | ||
| V2S | sec_cm_fifo_ctr_redun | flash_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_mem_tl_lc_gate_fsm_sparse | flash_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_prog_tl_lc_gate_fsm_sparse | flash_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | TOTAL | 60 | 144 | 41.67 | |||
| V3 | asymmetric_read_path | flash_ctrl_rd_ooo | 0 | 1 | 0.00 | ||
| V3 | stress_all_with_rand_reset | flash_ctrl_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 1 | 0.00 | |||
| TOTAL | 215 | 1278 | 16.82 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 9 | 9 | 7 | 77.78 |
| V2 | 55 | 55 | 3 | 5.45 |
| V2S | 12 | 12 | 3 | 25.00 |
| V3 | 2 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 54.97 | 51.78 | 51.55 | 49.37 | 0.00 | 65.89 | 99.33 | 66.86 |
launch_task.returncode != *, err: * *:*:* * lswatcher.go:*] Failed to connect to Watcher service in the Envelope (you probably need to import _ "google3/tech/env/go/envelope"): generic::unimplemented: envrpc: no envelope available for service "chubby.googleapis.com" Failure to submit jobs: rpc error: code = Unavailable desc = The service is currently unavailable. has 532 failures:
0.flash_ctrl_smoke.3354054469289651422567631287792492823007120260204041084086328502335252891264
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_smoke/latest/run.log
1.flash_ctrl_smoke.65580542059226220905394976640178865296438689869586027297309845898407426400767
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_smoke/latest/run.log
... and 15 more failures.
0.flash_ctrl_rand_ops.114064699862093447003263548119684316604378665238272248402941808470056225322298
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rand_ops/latest/run.log
1.flash_ctrl_rand_ops.44381368432867962344330951005039855378110999373729763652178151089814337136034
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rand_ops/latest/run.log
... and 14 more failures.
0.flash_ctrl_host_dir_rd.27596186169024951940245445648424436145538040614588726939201705838515019629439
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_host_dir_rd/latest/run.log
1.flash_ctrl_host_dir_rd.80650731088704303413052905450610172809330139562327552468882198102630532893648
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_host_dir_rd/latest/run.log
... and 2 more failures.
0.flash_ctrl_phy_arb.20727202863176157101358666191840375292433052841687092377355331351421780980877
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_phy_arb/latest/run.log
1.flash_ctrl_phy_arb.33131479715383152999899901124811331952072529279014468661994277026112652558933
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_phy_arb/latest/run.log
... and 5 more failures.
0.flash_ctrl_erase_suspend.93291634834232117028154519783795901014714264435425818588504238068507342021648
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_erase_suspend/latest/run.log
1.flash_ctrl_erase_suspend.67892563906524069533559215801614959569391643952877932219395990263186006673328
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_erase_suspend/latest/run.log
... and 2 more failures.
Job killed most likely because its dependent job failed. has 531 failures:
Test flash_ctrl_smoke_hw has 4 failures.
0.flash_ctrl_smoke_hw.97834024777216940149613491153595589007712584815489994342387263342423722411498
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_smoke_hw/latest/run.log
1.flash_ctrl_smoke_hw.91498471289113879803853227958434435927889225748198652612954118093480803121664
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_smoke_hw/latest/run.log
... and 2 more failures.
Test flash_ctrl_sw_op has 4 failures.
0.flash_ctrl_sw_op.2088905554611650974829527393055148142322245361843582990599093122534836633964
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_sw_op/latest/run.log
1.flash_ctrl_sw_op.56391512447682529478958410811829724562799291913837809465457909143547442715418
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_sw_op/latest/run.log
... and 2 more failures.
Test flash_ctrl_rd_buff_evict has 4 failures.
0.flash_ctrl_rd_buff_evict.62410185551168741426551969297692079905739843672496814523004456213481149886107
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rd_buff_evict/latest/run.log
1.flash_ctrl_rd_buff_evict.67360010833903865073082290071789682958807553857838601333244008585879675101026
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rd_buff_evict/latest/run.log
... and 2 more failures.
Test flash_ctrl_hw_sec_otp has 17 failures.
0.flash_ctrl_hw_sec_otp.7954526319556820347913242915609050770437842285086635189759878260007542336268
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_hw_sec_otp/latest/run.log
1.flash_ctrl_hw_sec_otp.55411059144807813461327445783353041251359895000768016885887245444029482950014
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_hw_sec_otp/latest/run.log
... and 15 more failures.
Test flash_ctrl_hw_rma has 2 failures.
0.flash_ctrl_hw_rma.85263953779462554641969620608189849239312431157726853777062573004967969310396
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_hw_rma/latest/run.log
1.flash_ctrl_hw_rma.44326382768539838310350876691878809738413316663282120308988909139231043873109
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_hw_rma/latest/run.log
... and 57 more tests.