FLASH_CTRL Simulation Results

Sunday March 31 2024 19:03:23 UTC

GitHub Revision: 919341eb22

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 80856351313811177568455658403012118288310064949310327557570531903004064389549

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.627m	103.251us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.210s	55.999us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	45.200s	79.100us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	17.770s	975.024us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.273m	2.235ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.032m	5.052ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	20.720s	172.441us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	17.770s	975.024us	20	20	100.00
		flash_ctrl_csr_aliasing	1.032m	5.052ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.510s	16.948us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	13.900s	32.947us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	26.480s	36.165us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	1.327m	46.894us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	35.527m	148.736ms	3	3	100.00
		flash_ctrl_hw_rma_reset	17.350m	420.338ms	20	20	100.00
		flash_ctrl_lcmgr_intg	13.800s	19.329us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	45.463m	1.039s	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	7.086m	2.132ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	5.569m	4.099ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	48.742m	311.684ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	3.043m	2.772ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	37.020s	433.181us	40	40	100.00
		flash_ctrl_rw_evict_all_en	35.380s	306.457us	37	40	92.50
		flash_ctrl_re_evict	39.530s	174.849us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	10.568m	4.109ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	10.568m	4.109ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	14.608m	46.064ms	19	20	95.00
V2	fetch_code	flash_ctrl_fetch_code	29.180s	579.140us	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	23.349m	1.583ms	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	38.120m	122.076ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	15.827m	1.871ms	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	40.731m	3.895ms	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	13.910s	15.918us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	3.318m	7.903ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	22.570s	36.831us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.060s	56.902us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	30.764m	2.094ms	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.492m	13.257ms	50	50	100.00
		flash_ctrl_otp_reset	2.213m	163.244us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	35.527m	148.736ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	4.085m	1.320ms	40	40	100.00
		flash_ctrl_intr_wr	1.857m	11.279ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	4.723m	8.263ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	9.563m	192.878ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.553m	6.099ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.204m	3.790ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	22.580s	33.181us	5	5	100.00
		flash_ctrl_ro_derr	2.517m	2.534ms	10	10	100.00
		flash_ctrl_rw_derr	11.326m	14.287ms	10	10	100.00
		flash_ctrl_derr_detect	1.723m	1.121ms	5	5	100.00
		flash_ctrl_integrity	10.856m	18.117ms	5	5	100.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	23.040s	25.501us	5	5	100.00
		flash_ctrl_ro_serr	2.455m	707.477us	10	10	100.00
		flash_ctrl_rw_serr	10.971m	18.901ms	10	10	100.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.170m	2.452ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.515m	3.756ms	5	5	100.00
V2	scramble	flash_ctrl_wo	3.953m	10.414ms	20	20	100.00
		flash_ctrl_write_word_sweep	16.690s	243.312us	1	1	100.00
		flash_ctrl_read_word_sweep	14.090s	95.516us	1	1	100.00
		flash_ctrl_ro	2.292m	6.751ms	20	20	100.00
		flash_ctrl_rw	10.066m	8.499ms	20	20	100.00
V2	filesystem_support	flash_ctrl_fs_sup	38.390s	1.223ms	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	16.306m	568.522ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	5.368m	10.012ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	14.000s	404.674us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	13.960s	14.867us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	20.330s	208.516us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	20.330s	208.516us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	45.200s	79.100us	5	5	100.00
		flash_ctrl_csr_rw	17.770s	975.024us	20	20	100.00
		flash_ctrl_csr_aliasing	1.032m	5.052ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	35.470s	1.129ms	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	45.200s	79.100us	5	5	100.00
		flash_ctrl_csr_rw	17.770s	975.024us	20	20	100.00
		flash_ctrl_csr_aliasing	1.032m	5.052ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	35.470s	1.129ms	20	20	100.00
V2		TOTAL			1009	1013	99.61
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	16.070s	18.521us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	16.070s	18.521us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	16.070s	18.521us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	16.070s	18.521us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.040s	34.564us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.318h	1.612ms	5	5	100.00
		flash_ctrl_tl_intg_err	14.884m	1.407ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	14.884m	1.407ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	14.884m	1.407ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	31.440s	115.227us	3	3	100.00
		flash_ctrl_wr_intg	14.470s	87.816us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.627m	103.251us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.213m	163.244us	80	80	100.00
		flash_ctrl_disable	22.570s	36.831us	50	50	100.00
		flash_ctrl_sec_info_access	1.381m	7.570ms	50	50	100.00
		flash_ctrl_connect	16.060s	56.902us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	13.920s	39.440us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	17.770s	975.024us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.070s	18.521us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	17.770s	975.024us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.070s	18.521us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	17.770s	975.024us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	16.070s	18.521us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	22.570s	36.831us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	31.440s	115.227us	3	3	100.00
		flash_ctrl_access_after_disable	13.570s	23.332us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	22.570s	36.831us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	29.180s	579.140us	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	10.066m	8.499ms	20	20	100.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	10.971m	18.901ms	10	10	100.00
		flash_ctrl_rw_derr	11.326m	14.287ms	10	10	100.00
		flash_ctrl_integrity	10.856m	18.117ms	5	5	100.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	35.527m	148.736ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.318h	1.612ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.318h	1.612ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.318h	1.612ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.318h	1.612ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	1.266m	886.255us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.270s	164.622us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	14.240s	58.880us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.318h	1.612ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.318h	1.612ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.318h	1.612ms	5	5	100.00
V2S		TOTAL			144	144	100.00
V3	asymmetric_read_path	flash_ctrl_rd_ooo	44.110s	114.727us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1274	1278	99.69

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	53	96.36
V2S	12	12	12	100.00
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.44	95.82	94.22	98.85	91.84	98.27	98.01	98.06

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 3 failures:
  • Test flash_ctrl_rw_evict_all_en has 3 failures.

    • 10.flash_ctrl_rw_evict_all_en.7696784931233205969121705487006296189729533839166425372558101360721864092993
      Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/10.flash_ctrl_rw_evict_all_en/latest/run.log

        UVM_ERROR @ 18878.9 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
        UVM_INFO @ 18878.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 13.flash_ctrl_rw_evict_all_en.84252002046998195294113395780301385990871147389967469582113845014236920295853
      Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/13.flash_ctrl_rw_evict_all_en/latest/run.log

        UVM_ERROR @ 15415.4 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
        UVM_INFO @ 15415.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_FATAL (flash_ctrl_mp_regions_vseq.sv:196) [flash_ctrl_mp_regions_vseq] wait timeout for alert_count == exp_alertcnt after do_mp_reg() alert_cnt:* exp_alert_cnt:* has 1 failures:
  • Test flash_ctrl_mp_regions has 1 failures.

    • 14.flash_ctrl_mp_regions.56655122052172764455267758380051408673215930575457930221563614329062427410241
      Line 559, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/14.flash_ctrl_mp_regions/latest/run.log

        UVM_FATAL @ 386556.4 ns: (flash_ctrl_mp_regions_vseq.sv:196) [uvm_test_top.env.virtual_sequencer.flash_ctrl_mp_regions_vseq] wait timeout for alert_count == exp_alertcnt after do_mp_reg() alert_cnt:14  exp_alert_cnt:15
        UVM_INFO @ 386556.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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