FLASH_CTRL Simulation Results

Tuesday April 02 2024 19:02:21 UTC

GitHub Revision: 1fbe1ece8d

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 10515816417091650402163962333134174777740454699264757911298152460288222033634

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.637m	704.285us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.060s	24.604us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	46.550s	46.606us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	17.450s	57.233us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.632m	18.260ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.147m	5.223ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	19.720s	182.973us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	17.450s	57.233us	20	20	100.00
		flash_ctrl_csr_aliasing	1.147m	5.223ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.690s	43.041us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	13.820s	15.700us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	26.430s	105.159us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	2.050m	256.066us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	40.419m	676.820ms	3	3	100.00
		flash_ctrl_hw_rma_reset	17.046m	160.198ms	20	20	100.00
		flash_ctrl_lcmgr_intg	14.170s	15.609us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	49.151m	264.838ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	10.373m	8.171ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	1.569m	3.039ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	1.071h	543.872ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	2.321m	2.805ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	34.050s	174.561us	40	40	100.00
		flash_ctrl_rw_evict_all_en	31.960s	54.591us	40	40	100.00
		flash_ctrl_re_evict	40.030s	1.834ms	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	11.586m	13.436ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	11.586m	13.436ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	18.616m	14.996ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	30.510s	4.829ms	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	18.384m	234.237us	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	44.227m	27.920ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	15.732m	2.830ms	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	38.658m	14.699ms	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	13.770s	49.252us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	2.545m	1.344ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	22.190s	32.275us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.480s	16.054us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	23.572m	730.683us	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	5.050m	21.850ms	50	50	100.00
		flash_ctrl_otp_reset	2.262m	75.778us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	40.419m	676.820ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	4.021m	16.121ms	40	40	100.00
		flash_ctrl_intr_wr	1.986m	43.551ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	4.639m	73.154ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	7.604m	90.593ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.683m	1.937ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.375m	10.539ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	23.530s	19.693us	5	5	100.00
		flash_ctrl_ro_derr	2.804m	2.666ms	10	10	100.00
		flash_ctrl_rw_derr	11.508m	4.636ms	10	10	100.00
		flash_ctrl_derr_detect	1.757m	221.732us	5	5	100.00
		flash_ctrl_integrity	11.060m	3.754ms	5	5	100.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	22.530s	46.492us	5	5	100.00
		flash_ctrl_ro_serr	3.035m	939.703us	10	10	100.00
		flash_ctrl_rw_serr	10.585m	12.521ms	10	10	100.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.342m	1.035ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.616m	3.675ms	5	5	100.00
V2	scramble	flash_ctrl_wo	3.436m	29.049ms	20	20	100.00
		flash_ctrl_write_word_sweep	17.690s	68.777us	1	1	100.00
		flash_ctrl_read_word_sweep	13.420s	14.189us	1	1	100.00
		flash_ctrl_ro	2.191m	2.058ms	20	20	100.00
		flash_ctrl_rw	11.011m	5.686ms	20	20	100.00
V2	filesystem_support	flash_ctrl_fs_sup	38.040s	1.507ms	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	15.159m	40.200ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	5.356m	10.013ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	14.110s	109.887us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	13.890s	49.688us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	19.530s	52.870us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	19.530s	52.870us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	46.550s	46.606us	5	5	100.00
		flash_ctrl_csr_rw	17.450s	57.233us	20	20	100.00
		flash_ctrl_csr_aliasing	1.147m	5.223ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	35.960s	598.392us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	46.550s	46.606us	5	5	100.00
		flash_ctrl_csr_rw	17.450s	57.233us	20	20	100.00
		flash_ctrl_csr_aliasing	1.147m	5.223ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	35.960s	598.392us	20	20	100.00
V2		TOTAL			1013	1013	100.00
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	16.070s	28.813us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	16.070s	28.813us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	16.070s	28.813us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	16.070s	28.813us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.200s	21.379us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.294h	3.191ms	5	5	100.00
		flash_ctrl_tl_intg_err	15.141m	1.511ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.141m	1.511ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.141m	1.511ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	32.170s	217.602us	3	3	100.00
		flash_ctrl_wr_intg	14.600s	83.940us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.637m	704.285us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.262m	75.778us	80	80	100.00
		flash_ctrl_disable	22.190s	32.275us	50	50	100.00
		flash_ctrl_sec_info_access	1.744m	35.554ms	50	50	100.00
		flash_ctrl_connect	16.480s	16.054us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	14.210s	174.996us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	17.450s	57.233us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.070s	28.813us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	17.450s	57.233us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.070s	28.813us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	17.450s	57.233us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	16.070s	28.813us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	22.190s	32.275us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	32.170s	217.602us	3	3	100.00
		flash_ctrl_access_after_disable	13.880s	24.752us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	22.190s	32.275us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	30.510s	4.829ms	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	11.011m	5.686ms	20	20	100.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	10.585m	12.521ms	10	10	100.00
		flash_ctrl_rw_derr	11.508m	4.636ms	10	10	100.00
		flash_ctrl_integrity	11.060m	3.754ms	5	5	100.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	40.419m	676.820ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.294h	3.191ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.294h	3.191ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.294h	3.191ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.294h	3.191ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	1.269m	805.556us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	13.960s	17.214us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	22.350s	364.124us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.294h	3.191ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.294h	3.191ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.294h	3.191ms	5	5	100.00
V2S		TOTAL			144	144	100.00
V3	asymmetric_read_path	flash_ctrl_rd_ooo	45.960s	75.779us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1278	1278	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	55	100.00
V2S	12	12	12	100.00
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.17	95.28	93.98	98.85	91.84	97.00	98.11	98.15

Past Results

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• 2024.04.01_04.28.41
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