Assertions
dashboard | hierarchy | modlist | groups | tests | asserts
Assertions by Category
ASSERTPROPERTIESSEQUENCES
Total992010
Category 0992010

Assertions by Severity
ASSERTPROPERTIESSEQUENCES
Total992010
Severity 0992010

Summary for Assertions
NUMBERPERCENT
Total Number992100.00
Uncovered171.71
Success97598.29
Failure00.00
Incomplete151.51
Without Attempts00.00

Summary for Cover Sequences
NUMBERPERCENT
Total Number10100.00
Uncovered330.00
All Matches770.00
First Matches770.00
Go previous page
ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETE
tb.dut.u_tl_adapter_eflash.rvalidHighWhenRspFifoFull 00425076783458850300
tb.dut.u_tl_adapter_eflash.u_err.dataWidthOnly32_A 001062106200
tb.dut.u_tl_adapter_eflash.u_reqfifo.DataKnown_A 004250767833601401700
tb.dut.u_tl_adapter_eflash.u_reqfifo.DepthKnown_A 0042507678342419496500
tb.dut.u_tl_adapter_eflash.u_reqfifo.RvalidKnown_A 0042507678342419496500
tb.dut.u_tl_adapter_eflash.u_reqfifo.WreadyKnown_A 0042507678342419496500
tb.dut.u_tl_adapter_eflash.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth 004250767833601401700
tb.dut.u_tl_adapter_eflash.u_rsp_gen.DataWidthCheck_A 001062106200
tb.dut.u_tl_adapter_eflash.u_rsp_gen.PayLoadWidthCheck 001062106200
tb.dut.u_tl_adapter_eflash.u_rspfifo.DataKnown_A 00425076783550946700
tb.dut.u_tl_adapter_eflash.u_rspfifo.DepthKnown_A 0042507678342419496500
tb.dut.u_tl_adapter_eflash.u_rspfifo.RvalidKnown_A 0042507678342419496500
tb.dut.u_tl_adapter_eflash.u_rspfifo.WreadyKnown_A 0042507678342419496500
tb.dut.u_tl_adapter_eflash.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth 00425076783550946700
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.DataKnown_A 004250767833508811700
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.DepthKnown_A 0042507678342419496500
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.RvalidKnown_A 0042507678342419496500
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.WreadyKnown_A 0042507678342419496500
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth 004250767833508811700
tb.dut.u_tl_gate.u_err_en_sync.NumCopiesMustBeGreaterZero_A 001062106200
tb.dut.u_tl_gate.u_err_en_sync.OutputsKnown_A 0041948165041859983200
tb.dut.u_tl_gate.u_err_en_sync.gen_no_flops.OutputDelay_A 0041948165041859983200
tb.dut.u_tl_gate.u_state_regs.AssertConnected_A 001062106200
tb.dut.u_tl_gate.u_state_regs_A 0042507678342419496500
tb.dut.u_tl_gate.u_tlul_err_resp.u_intg_gen.DataWidthCheck_A 001062106200
tb.dut.u_tl_gate.u_tlul_err_resp.u_intg_gen.PayLoadWidthCheck 001062106200
tb.dut.u_to_prog_fifo.AddrOutKnown_A 0042507678342419496500
tb.dut.u_to_prog_fifo.DataIntgOptions_A 001062106200
tb.dut.u_to_prog_fifo.ReqOutKnown_A 0042507678342419496500
tb.dut.u_to_prog_fifo.SramDwHasByteGranularity_A 001062106200
tb.dut.u_to_prog_fifo.SramDwIsMultipleOfTlulWidth_A 001062106200
tb.dut.u_to_prog_fifo.TlOutKnownIfFifoKnown_A 0042507678342419496500
tb.dut.u_to_prog_fifo.TlOutValidKnown_A 0042507678342419496500
tb.dut.u_to_prog_fifo.WdataOutKnown_A 0042507678342419496500
tb.dut.u_to_prog_fifo.WeOutKnown_A 0042507678342419496500
tb.dut.u_to_prog_fifo.WmaskOutKnown_A 0042507678342419496500
tb.dut.u_to_prog_fifo.adapterNoReadOrWrite 001062106200
tb.dut.u_to_prog_fifo.u_err.dataWidthOnly32_A 001062106200
tb.dut.u_to_prog_fifo.u_reqfifo.DataKnown_A 00425076783400659400
tb.dut.u_to_prog_fifo.u_reqfifo.DepthKnown_A 0042507678342419496500
tb.dut.u_to_prog_fifo.u_reqfifo.RvalidKnown_A 0042507678342419496500
tb.dut.u_to_prog_fifo.u_reqfifo.WreadyKnown_A 0042507678342419496500
tb.dut.u_to_prog_fifo.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth 00425076783400659400
tb.dut.u_to_prog_fifo.u_rsp_gen.DataWidthCheck_A 001062106200
tb.dut.u_to_prog_fifo.u_rsp_gen.PayLoadWidthCheck 001062106200
tb.dut.u_to_prog_fifo.u_rspfifo.DepthKnown_A 0042507678342419496500
tb.dut.u_to_prog_fifo.u_rspfifo.RvalidKnown_A 0042507678342419496500
tb.dut.u_to_prog_fifo.u_rspfifo.WreadyKnown_A 0042507678342419496500
tb.dut.u_to_prog_fifo.u_sramreqfifo.DepthKnown_A 0042507678342419496500
tb.dut.u_to_prog_fifo.u_sramreqfifo.RvalidKnown_A 0042507678342419496500
tb.dut.u_to_prog_fifo.u_sramreqfifo.WreadyKnown_A 0042507678342419496500
tb.dut.u_to_rd_fifo.AddrOutKnown_A 0042507678342419496500
tb.dut.u_to_rd_fifo.DataIntgOptions_A 001062106200
tb.dut.u_to_rd_fifo.ReqOutKnown_A 0042507678342419496500
tb.dut.u_to_rd_fifo.SramDwHasByteGranularity_A 001062106200
tb.dut.u_to_rd_fifo.SramDwIsMultipleOfTlulWidth_A 001062106200
tb.dut.u_to_rd_fifo.TlOutKnownIfFifoKnown_A 0042507678342419496500
tb.dut.u_to_rd_fifo.TlOutValidKnown_A 0042507678342419496500
tb.dut.u_to_rd_fifo.WdataOutKnown_A 0042507678342419496500
tb.dut.u_to_rd_fifo.WeOutKnown_A 0042507678342419496500
tb.dut.u_to_rd_fifo.WmaskOutKnown_A 0042507678342419496500
tb.dut.u_to_rd_fifo.adapterNoReadOrWrite 001062106200
tb.dut.u_to_rd_fifo.rvalidHighReqFifoEmpty 00425076783330958100
tb.dut.u_to_rd_fifo.rvalidHighWhenRspFifoFull 00424353780330333600
tb.dut.u_to_rd_fifo.u_err.dataWidthOnly32_A 001062106200
tb.dut.u_to_rd_fifo.u_reqfifo.DataKnown_A 00425076783532828100
tb.dut.u_to_rd_fifo.u_reqfifo.DepthKnown_A 0042507678342419496500
tb.dut.u_to_rd_fifo.u_reqfifo.RvalidKnown_A 0042507678342419496500
tb.dut.u_to_rd_fifo.u_reqfifo.WreadyKnown_A 0042507678342419496500
tb.dut.u_to_rd_fifo.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth 00425076783532828100
tb.dut.u_to_rd_fifo.u_rsp_gen.DataWidthCheck_A 001062106200
tb.dut.u_to_rd_fifo.u_rsp_gen.PayLoadWidthCheck 001062106200
tb.dut.u_to_rd_fifo.u_rspfifo.DataKnown_A 00424850133532043800
tb.dut.u_to_rd_fifo.u_rspfifo.DepthKnown_A 0042507678342419496500
tb.dut.u_to_rd_fifo.u_rspfifo.RvalidKnown_A 0042507678342419496500
tb.dut.u_to_rd_fifo.u_rspfifo.WreadyKnown_A 0042507678342419496500
tb.dut.u_to_rd_fifo.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth 00425076783533463900
tb.dut.u_to_rd_fifo.u_sramreqfifo.DataKnown_A 00425076783330958100
tb.dut.u_to_rd_fifo.u_sramreqfifo.DepthKnown_A 0042507678342419496500
tb.dut.u_to_rd_fifo.u_sramreqfifo.RvalidKnown_A 0042507678342419496500
tb.dut.u_to_rd_fifo.u_sramreqfifo.WreadyKnown_A 0042507678342419496500
tb.dut.u_to_rd_fifo.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth 00425076783330958100

Assertions Incomplete:
ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETESRC
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.RoundRobin_A 004250767833185301056
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.RoundRobin_A 004250767832461801056
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_flops.OutputDelay_A 0041948165041856544602778
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.RoundRobin_A 00425076783001056
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.RoundRobin_A 00425076783001056
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.RoundRobin_A 00425076783001056
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.RoundRobin_A 00425076783001056
tb.dut.u_flash_hw_if.DisableChk_A 004087022589255742044
tb.dut.u_flash_hw_if.u_sync_rma_req.gen_flops.OutputDelay_A 0041948172641856550702778
tb.dut.u_lc_escalation_en_sync.gen_flops.OutputDelay_A 0041946020941854414002628
tb.dut.u_lc_seed_hw_rd_en_sync.gen_flops.OutputDelay_A 0041948172641856550702778
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_flops.OutputDelay_A 0041948172641856550702778
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_flops.OutputDelay_A 0041948172641856550702778
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_flops.OutputDelay_A 0041948172641856550702778
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_flops.OutputDelay_A 0041948172641856550702778

Detail Report for Cover Sequences

Cover Sequences Uncovered:
COVER SEQUENCESCATEGORYSEVERITYATTEMPTSALL MATCHESFIRST MATCHESINCOMPLETESRC
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C 00428226574000
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C 00428226574000
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C 00428226574000

Cover Sequences All Matches:
COVER SEQUENCESCATEGORYSEVERITYATTEMPTSALL MATCHESFIRST MATCHESINCOMPLETESRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C 004282265741144681144680
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C 0042822657420200
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C 00428226574880
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C 00428226574220
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C 0042822657415945159450
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C 004282265742747532747530
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C 0042822657418519284185192841251

Cover Sequences First Matches:
COVER SEQUENCESCATEGORYSEVERITYATTEMPTSALL MATCHESFIRST MATCHESINCOMPLETESRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C 004282265741144681144680
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C 0042822657420200
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C 00428226574880
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C 00428226574220
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C 0042822657415945159450
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C 004282265742747532747530
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C 0042822657418519284185192841251