Module Definition
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Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.98 100.00 82.08 100.00 97.83 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.60 97.92 91.86 93.02 100.00 98.86 97.94


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.89 97.67 90.00 100.00 u_eflash


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prog_data.u_prog 98.65 100.00 96.92 95.00 100.00 100.00 100.00
u_disable_buf 100.00 100.00 100.00
u_erase 97.22 100.00 88.89 100.00 100.00
u_host_arb 91.95 75.93 91.89 100.00 100.00
u_host_outstanding_cnt 88.89 88.89
u_rd 95.29 99.17 92.50 90.00 98.55 96.23
u_state_regs 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.68 100.00 90.57 100.00 97.83 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.26 97.92 92.71 96.12 100.00 98.86 97.94


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.89 97.67 90.00 100.00 u_eflash


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prog_data.u_prog 99.49 100.00 96.92 100.00 100.00 100.00 100.00
u_disable_buf 100.00 100.00 100.00
u_erase 97.22 100.00 88.89 100.00 100.00
u_host_arb 93.98 75.93 100.00 100.00 100.00
u_host_outstanding_cnt 88.89 88.89
u_rd 95.29 99.17 92.50 90.00 98.55 96.23
u_state_regs 100.00 100.00 100.00 100.00

Line Coverage for Module : flash_phy_core
Line No.TotalCoveredPercent
TOTAL8989100.00
ALWAYS15166100.00
ALWAYS16433100.00
CONT_ASSIGN19511100.00
CONT_ASSIGN19911100.00
ALWAYS20244100.00
ALWAYS21466100.00
ALWAYS22866100.00
CONT_ASSIGN27611100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28611100.00
CONT_ASSIGN31611100.00
CONT_ASSIGN32011100.00
ALWAYS3242929100.00
CONT_ASSIGN38711100.00
CONT_ASSIGN39111100.00
CONT_ASSIGN39211100.00
CONT_ASSIGN39311100.00
CONT_ASSIGN39411100.00
CONT_ASSIGN39511100.00
CONT_ASSIGN39611100.00
CONT_ASSIGN39711100.00
CONT_ASSIGN41411100.00
CONT_ASSIGN42711100.00
CONT_ASSIGN52111100.00
CONT_ASSIGN54811100.00
CONT_ASSIGN54911100.00
CONT_ASSIGN55011100.00
CONT_ASSIGN55111100.00
CONT_ASSIGN55311100.00
CONT_ASSIGN55411100.00
CONT_ASSIGN55511100.00
CONT_ASSIGN55611100.00
CONT_ASSIGN55711100.00
CONT_ASSIGN55811100.00
CONT_ASSIGN55911100.00
CONT_ASSIGN56611100.00
CONT_ASSIGN58311100.00
CONT_ASSIGN58411100.00
CONT_ASSIGN58511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
151 1 1
152 1 1
153 1 1
154 1 1
155 1 1
156 1 1
MISSING_ELSE
164 3 3
195 1 1
199 1 1
202 1 1
203 1 1
204 1 1
205 1 1
MISSING_ELSE
214 1 1
215 1 1
216 1 1
217 1 1
218 1 1
219 1 1
MISSING_ELSE
228 1 1
229 1 1
230 1 1
231 1 1
232 1 1
233 1 1
MISSING_ELSE
276 1 1
279 1 1
280 1 1
281 1 1
286 1 1
316 1 1
320 1 1
324 1 1
325 1 1
326 1 1
327 1 1
328 1 1
330 1 1
332 1 1
333 1 1
334 1 1
335 1 1
336 1 1
337 1 1
338 1 1
339 1 1
340 1 1
MISSING_ELSE
346 1 1
347 1 1
348 1 1
MISSING_ELSE
355 1 1
356 1 1
357 1 1
358 1 1
MISSING_ELSE
364 1 1
365 1 1
366 1 1
367 1 1
368 1 1
MISSING_ELSE
373 1 1
374 1 1
387 1 1
391 1 1
392 1 1
393 1 1
394 1 1
395 1 1
396 1 1
397 1 1
414 1 1
427 1 1
521 1 1
548 1 1
549 1 1
550 1 1
551 1 1
553 1 1
554 1 1
555 1 1
556 1 1
557 1 1
558 1 1
559 1 1
566 1 1
583 1 1
584 1 1
585 1 1


Cond Coverage for Module : flash_phy_core
TotalCoveredPercent
Conditions1069690.57
Logical1069690.57
Non-Logical00
Event00

 LINE       195
 EXPRESSION (host_gnt && (muxed_part != FlashPartData))
             ----1---    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T6,T26
11CoveredT20,T23,T24

 LINE       195
 SUB-EXPRESSION (muxed_part != FlashPartData)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       199
 EXPRESSION (((|host_outstanding)) & ((!ctrl_fsm_idle)))
             ----------1----------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T6,T26
11Not Covered

 LINE       204
 EXPRESSION (host_gnt_err_event | host_outstanding_err_event)
             ---------1--------   -------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT20,T23,T24

 LINE       216
 EXPRESSION (host_outstanding == '0)
            ------------1-----------
-1-StatusTests
0CoveredT4,T6,T26
1CoveredT1,T2,T3

 LINE       230
 EXPRESSION ((host_outstanding == '0) && ctrl_fsm_idle)
             ------------1-----------    ------2------
-1--2-StatusTests
01CoveredT4,T6,T26
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       230
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------
-1-StatusTests
0CoveredT4,T6,T26
1CoveredT1,T2,T3

 LINE       241
 EXPRESSION (host_gnt && ((!host_req_done_o)) && (host_outstanding <= flash_phy_pkg::RspOrderDepth))
             ----1---    ----------2---------    -------------------------3------------------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT6,T26,T16
110Not Covered
111CoveredT4,T6,T26

 LINE       241
 EXPRESSION (((!host_gnt)) && host_req_done_o && ((|host_outstanding)))
             ------1------    -------2-------    ----------3----------
-1--2--3-StatusTests
011CoveredT6,T26,T16
101CoveredT4,T6,T26
110CoveredT4,T127,T128
111CoveredT4,T6,T26

 LINE       280
 EXPRESSION (host_req & host_req_rdy_o)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT96
10CoveredT4,T6,T16
11CoveredT4,T6,T26

 LINE       281
 EXPRESSION (((|host_outstanding)) & rd_stage_data_valid)
             ----------1----------   ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T6,T26
11CoveredT4,T6,T26

 LINE       316
 EXPRESSION ((phy_req & host_req) ? rd_stage_rdy : rd_stage_idle)
             ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T6,T26

 LINE       316
 SUB-EXPRESSION (phy_req & host_req)
                 ---1---   ----2---
-1--2-StatusTests
01CoveredT159
10CoveredT1,T2,T3
11CoveredT4,T6,T26

 LINE       320
 EXPRESSION (req_i & host_gnt)
             --1--   ----2---
-1--2-StatusTests
01CoveredT4,T6,T26
10CoveredT1,T2,T3
11CoveredT6,T16,T17

 LINE       335
 EXPRESSION (ctrl_gnt && rd_i)
             ----1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       337
 EXPRESSION (ctrl_gnt && prog_i)
             ----1---    ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       387
 EXPRESSION ((ctrl_fsm_idle & ctrl_rsp_vld) | ((host_outstanding == '0) & host_req_done_o))
             ---------------1--------------   ----------------------2---------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T127,T128
10CoveredT142

 LINE       387
 SUB-EXPRESSION (ctrl_fsm_idle & ctrl_rsp_vld)
                 ------1------   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT142

 LINE       387
 SUB-EXPRESSION ((host_outstanding == '0) & host_req_done_o)
                 ------------1-----------   -------2-------
-1--2-StatusTests
01CoveredT4,T6,T26
10CoveredT1,T2,T3
11CoveredT4,T127,T128

 LINE       387
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       391
 EXPRESSION (host_sel ? host_addr_i : addr_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T6,T26

 LINE       392
 EXPRESSION (host_sel ? FlashPartData : part_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T6,T26

 LINE       393
 EXPRESSION (host_sel ? host_scramble_en_i : scramble_en_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T6,T26

 LINE       394
 EXPRESSION (host_sel ? host_ecc_en_i : ecc_en_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T6,T26

 LINE       395
 EXPRESSION (ctrl_rsp_vld & rd_i)
             ------1-----   --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       396
 EXPRESSION (ctrl_rsp_vld & prog_i)
             ------1-----   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       397
 EXPRESSION (ctrl_rsp_vld & (pg_erase_i | bk_erase_i))
             ------1-----   ------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       397
 SUB-EXPRESSION (pg_erase_i | bk_erase_i)
                 -----1----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T42,T43
10CoveredT1,T2,T3

 LINE       427
 EXPRESSION ((host_gnt_rd_err & (host_outstanding == 1'b1)) | host_outstanding_rd_err)
             -----------------------1----------------------   -----------2-----------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered

 LINE       427
 SUB-EXPRESSION (host_gnt_rd_err & (host_outstanding == 1'b1))
                 -------1-------   -------------2------------
-1--2-StatusTests
01CoveredT4,T6,T26
10Not Covered
11Not Covered

 LINE       427
 SUB-EXPRESSION (host_outstanding == 1'b1)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T6,T26

 LINE       430
 EXPRESSION (phy_req & (rd_i | host_req))
             ---1---   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       430
 SUB-EXPRESSION (rd_i | host_req)
                 --1-   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T6,T26
10CoveredT1,T2,T3

 LINE       430
 EXPRESSION (arb_host_gnt_err ? ({flash_phy_pkg::FullDataWidth {1'b1}}) : flash_rdata)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       521
 EXPRESSION (fsm_err | prog_fsm_err)
             ---1---   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered

 LINE       548
 EXPRESSION (prog_calc_req | rd_calc_req)
             ------1------   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T4,T15

 LINE       549
 EXPRESSION (prog_op_req | rd_op_req)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T4,T15

 LINE       550
 EXPRESSION (prog_op_req ? ScrambleOp : DeScrambleOp)
             -----1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T15

 LINE       551
 EXPRESSION (prog_calc_req ? muxed_addr[(flash_phy_pkg::BusBankAddrW - 1):flash_phy_pkg::LsbAddrBit] : rd_calc_addr)
             ------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T15

FSM Coverage for Module : flash_phy_core
Summary for FSM :: state_q
TotalCoveredPercent
States 5 5 100.00 (Not included in score)
Transitions 7 7 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
StCtrl 340 Covered T1,T2,T3
StCtrlProg 338 Covered T1,T2,T3
StCtrlRead 336 Covered T1,T2,T3
StDisable 334 Covered T1,T21,T22
StIdle 348 Covered T1,T2,T3


transitionsLine No.CoveredTests
StCtrl->StIdle 368 Covered T1,T2,T3
StCtrlProg->StIdle 358 Covered T1,T2,T3
StCtrlRead->StIdle 348 Covered T1,T2,T3
StIdle->StCtrl 340 Covered T1,T2,T3
StIdle->StCtrlProg 338 Covered T1,T2,T3
StIdle->StCtrlRead 336 Covered T1,T2,T3
StIdle->StDisable 334 Covered T1,T21,T22



Branch Coverage for Module : flash_phy_core
Line No.TotalCoveredPercent
Branches 46 45 97.83
TERNARY 316 2 2 100.00
TERNARY 391 2 2 100.00
TERNARY 392 2 2 100.00
TERNARY 393 2 2 100.00
TERNARY 394 2 2 100.00
TERNARY 550 2 2 100.00
TERNARY 551 2 2 100.00
TERNARY 430 2 1 50.00
IF 151 4 4 100.00
IF 164 2 2 100.00
IF 202 3 3 100.00
IF 214 4 4 100.00
IF 228 4 4 100.00
CASE 330 13 13 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 316 ((phy_req & host_req)) ?

Branches:
-1-StatusTests
1 Covered T4,T6,T26
0 Covered T1,T2,T3


LineNo. Expression -1-: 391 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T4,T6,T26
0 Covered T1,T2,T3


LineNo. Expression -1-: 392 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T4,T6,T26
0 Covered T1,T2,T3


LineNo. Expression -1-: 393 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T4,T6,T26
0 Covered T1,T2,T3


LineNo. Expression -1-: 394 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T4,T6,T26
0 Covered T1,T2,T3


LineNo. Expression -1-: 550 (prog_op_req) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T15
0 Covered T1,T2,T3


LineNo. Expression -1-: 551 (prog_calc_req) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T15
0 Covered T1,T2,T3


LineNo. Expression -1-: 430 (arb_host_gnt_err) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 151 if ((!rst_ni)) -2-: 153 if (ctrl_rsp_vld) -3-: 155 if (inc_arb_cnt)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T6,T16,T17
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 164 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 202 if ((!rst_ni)) -2-: 204 if ((host_gnt_err_event | host_outstanding_err_event))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T20,T23,T24
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 214 if ((!rst_ni)) -2-: 216 if ((host_outstanding == '0)) -3-: 218 if (host_gnt_err_event)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T20,T23,T24
0 0 0 Covered T4,T6,T26


LineNo. Expression -1-: 228 if ((!rst_ni)) -2-: 230 if (((host_outstanding == '0) && ctrl_fsm_idle)) -3-: 232 if (host_outstanding_err_event)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T20,T23,T24
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 330 case (state_q) -2-: 333 if (prim_mubi_pkg::mubi4_test_true_loose(flash_disable[FsmDisableIdx])) -3-: 335 if ((ctrl_gnt && rd_i)) -4-: 337 if ((ctrl_gnt && prog_i)) -5-: 339 if (ctrl_gnt) -6-: 346 if (rd_stage_data_valid) -7-: 356 if (prog_ack) -8-: 366 if (erase_ack)

Branches:
-1--2--3--4--5--6--7--8-StatusTests
StIdle 1 - - - - - - Covered T1,T21,T22
StIdle 0 1 - - - - - Covered T1,T2,T3
StIdle 0 0 1 - - - - Covered T1,T2,T3
StIdle 0 0 0 1 - - - Covered T1,T2,T3
StIdle 0 0 0 0 - - - Covered T1,T2,T3
StCtrlRead - - - - 1 - - Covered T1,T2,T3
StCtrlRead - - - - 0 - - Covered T1,T2,T3
StCtrlProg - - - - - 1 - Covered T1,T2,T3
StCtrlProg - - - - - 0 - Covered T1,T2,T3
StCtrl - - - - - - 1 Covered T1,T2,T3
StCtrl - - - - - - 0 Covered T1,T2,T3
StDisable - - - - - - - Covered T1,T21,T22
default - - - - - - - Covered T20,T23,T24


Assert Coverage for Module : flash_phy_core
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 8 8 100.00 8 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 8 8 100.00 8 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
ArbCntMax_A 697411980 3818115 0 0
CtrlPrio_A 697411980 3818110 0 0
HostTransIdleChk_A 697411980 40883786 0 0
NoRemainder_A 1750 1750 0 0
OneHotReqs_A 697411980 696197020 0 0
Pow2Multiple_A 1750 1750 0 0
RdTxnCheck_A 697411980 696197020 0 0
u_state_regs_A 697411980 696197020 0 0


ArbCntMax_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 697411980 3818115 0 0
T6 941302 10492 0 0
T10 128806 0 0 0
T12 0 82091 0 0
T13 0 6345 0 0
T14 0 6109 0 0
T16 147032 3186 0 0
T17 0 3057 0 0
T25 2538 0 0 0
T26 1565718 0 0 0
T33 0 17368 0 0
T42 409114 0 0 0
T49 375150 0 0 0
T61 2228 0 0 0
T72 3222 0 0 0
T73 146562 0 0 0
T92 0 2779 0 0
T129 0 16955 0 0
T162 0 87756 0 0

CtrlPrio_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 697411980 3818110 0 0
T6 941302 10492 0 0
T10 128806 0 0 0
T12 0 82091 0 0
T13 0 6345 0 0
T14 0 6109 0 0
T16 147032 3186 0 0
T17 0 3057 0 0
T25 2538 0 0 0
T26 1565718 0 0 0
T33 0 17368 0 0
T42 409114 0 0 0
T49 375150 0 0 0
T61 2228 0 0 0
T72 3222 0 0 0
T73 146562 0 0 0
T92 0 2779 0 0
T129 0 16955 0 0
T162 0 87756 0 0

HostTransIdleChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 697411980 40883786 0 0
T4 967 2 0 0
T5 3254 0 0 0
T6 941302 117092 0 0
T10 128806 0 0 0
T11 0 40 0 0
T12 0 443955 0 0
T13 0 27235 0 0
T15 82348 0 0 0
T16 73516 32838 0 0
T17 0 33548 0 0
T21 0 35 0 0
T25 2538 0 0 0
T26 1565718 196608 0 0
T33 0 141518 0 0
T42 204557 0 0 0
T49 375150 0 0 0
T55 0 28 0 0
T61 2228 0 0 0
T64 0 203 0 0
T72 1611 0 0 0
T73 146562 0 0 0
T87 0 15 0 0
T92 0 14825 0 0
T93 0 220 0 0

NoRemainder_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1750 1750 0 0
T1 2 2 0 0
T2 2 2 0 0
T3 2 2 0 0
T4 2 2 0 0
T5 2 2 0 0
T6 2 2 0 0
T10 2 2 0 0
T15 2 2 0 0
T25 2 2 0 0
T26 2 2 0 0

OneHotReqs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 697411980 696197020 0 0
T1 800906 800870 0 0
T2 868658 868464 0 0
T3 191034 190768 0 0
T4 1934 1644 0 0
T5 6508 6334 0 0
T6 941302 941192 0 0
T10 128806 128704 0 0
T15 164696 157092 0 0
T25 2538 2398 0 0
T26 1565718 1565702 0 0

Pow2Multiple_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1750 1750 0 0
T1 2 2 0 0
T2 2 2 0 0
T3 2 2 0 0
T4 2 2 0 0
T5 2 2 0 0
T6 2 2 0 0
T10 2 2 0 0
T15 2 2 0 0
T25 2 2 0 0
T26 2 2 0 0

RdTxnCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 697411980 696197020 0 0
T1 800906 800870 0 0
T2 868658 868464 0 0
T3 191034 190768 0 0
T4 1934 1644 0 0
T5 6508 6334 0 0
T6 941302 941192 0 0
T10 128806 128704 0 0
T15 164696 157092 0 0
T25 2538 2398 0 0
T26 1565718 1565702 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 697411980 696197020 0 0
T1 800906 800870 0 0
T2 868658 868464 0 0
T3 191034 190768 0 0
T4 1934 1644 0 0
T5 6508 6334 0 0
T6 941302 941192 0 0
T10 128806 128704 0 0
T15 164696 157092 0 0
T25 2538 2398 0 0
T26 1565718 1565702 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core
Line No.TotalCoveredPercent
TOTAL8989100.00
ALWAYS15166100.00
ALWAYS16433100.00
CONT_ASSIGN19511100.00
CONT_ASSIGN19911100.00
ALWAYS20244100.00
ALWAYS21466100.00
ALWAYS22866100.00
CONT_ASSIGN27611100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28611100.00
CONT_ASSIGN31611100.00
CONT_ASSIGN32011100.00
ALWAYS3242929100.00
CONT_ASSIGN38711100.00
CONT_ASSIGN39111100.00
CONT_ASSIGN39211100.00
CONT_ASSIGN39311100.00
CONT_ASSIGN39411100.00
CONT_ASSIGN39511100.00
CONT_ASSIGN39611100.00
CONT_ASSIGN39711100.00
CONT_ASSIGN41411100.00
CONT_ASSIGN42711100.00
CONT_ASSIGN52111100.00
CONT_ASSIGN54811100.00
CONT_ASSIGN54911100.00
CONT_ASSIGN55011100.00
CONT_ASSIGN55111100.00
CONT_ASSIGN55311100.00
CONT_ASSIGN55411100.00
CONT_ASSIGN55511100.00
CONT_ASSIGN55611100.00
CONT_ASSIGN55711100.00
CONT_ASSIGN55811100.00
CONT_ASSIGN55911100.00
CONT_ASSIGN56611100.00
CONT_ASSIGN58311100.00
CONT_ASSIGN58411100.00
CONT_ASSIGN58511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
151 1 1
152 1 1
153 1 1
154 1 1
155 1 1
156 1 1
MISSING_ELSE
164 3 3
195 1 1
199 1 1
202 1 1
203 1 1
204 1 1
205 1 1
MISSING_ELSE
214 1 1
215 1 1
216 1 1
217 1 1
218 1 1
219 1 1
MISSING_ELSE
228 1 1
229 1 1
230 1 1
231 1 1
232 1 1
233 1 1
MISSING_ELSE
276 1 1
279 1 1
280 1 1
281 1 1
286 1 1
316 1 1
320 1 1
324 1 1
325 1 1
326 1 1
327 1 1
328 1 1
330 1 1
332 1 1
333 1 1
334 1 1
335 1 1
336 1 1
337 1 1
338 1 1
339 1 1
340 1 1
MISSING_ELSE
346 1 1
347 1 1
348 1 1
MISSING_ELSE
355 1 1
356 1 1
357 1 1
358 1 1
MISSING_ELSE
364 1 1
365 1 1
366 1 1
367 1 1
368 1 1
MISSING_ELSE
373 1 1
374 1 1
387 1 1
391 1 1
392 1 1
393 1 1
394 1 1
395 1 1
396 1 1
397 1 1
414 1 1
427 1 1
521 1 1
548 1 1
549 1 1
550 1 1
551 1 1
553 1 1
554 1 1
555 1 1
556 1 1
557 1 1
558 1 1
559 1 1
566 1 1
583 1 1
584 1 1
585 1 1


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core
TotalCoveredPercent
Conditions1068782.08
Logical1068782.08
Non-Logical00
Event00

 LINE       195
 EXPRESSION (host_gnt && (muxed_part != FlashPartData))
             ----1---    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T6,T26
11Not Covered

 LINE       195
 SUB-EXPRESSION (muxed_part != FlashPartData)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       199
 EXPRESSION (((|host_outstanding)) & ((!ctrl_fsm_idle)))
             ----------1----------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T6,T26
11Not Covered

 LINE       204
 EXPRESSION (host_gnt_err_event | host_outstanding_err_event)
             ---------1--------   -------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered

 LINE       216
 EXPRESSION (host_outstanding == '0)
            ------------1-----------
-1-StatusTests
0CoveredT4,T6,T26
1CoveredT1,T2,T3

 LINE       230
 EXPRESSION ((host_outstanding == '0) && ctrl_fsm_idle)
             ------------1-----------    ------2------
-1--2-StatusTests
01CoveredT4,T6,T26
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       230
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------
-1-StatusTests
0CoveredT4,T6,T26
1CoveredT1,T2,T3

 LINE       241
 EXPRESSION (host_gnt && ((!host_req_done_o)) && (host_outstanding <= flash_phy_pkg::RspOrderDepth))
             ----1---    ----------2---------    -------------------------3------------------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT6,T26,T16
110Not Covered
111CoveredT4,T6,T26

 LINE       241
 EXPRESSION (((!host_gnt)) && host_req_done_o && ((|host_outstanding)))
             ------1------    -------2-------    ----------3----------
-1--2--3-StatusTests
011CoveredT6,T26,T16
101CoveredT4,T6,T26
110Not Covered
111CoveredT4,T6,T26

 LINE       280
 EXPRESSION (host_req & host_req_rdy_o)
             ----1---   -------2------
-1--2-StatusTests
01Not Covered
10CoveredT4,T6,T16
11CoveredT4,T6,T26

 LINE       281
 EXPRESSION (((|host_outstanding)) & rd_stage_data_valid)
             ----------1----------   ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T6,T26
11CoveredT4,T6,T26

 LINE       316
 EXPRESSION ((phy_req & host_req) ? rd_stage_rdy : rd_stage_idle)
             ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T6,T26

 LINE       316
 SUB-EXPRESSION (phy_req & host_req)
                 ---1---   ----2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT4,T6,T26

 LINE       320
 EXPRESSION (req_i & host_gnt)
             --1--   ----2---
-1--2-StatusTests
01CoveredT4,T6,T26
10CoveredT1,T2,T3
11CoveredT6,T16,T17

 LINE       335
 EXPRESSION (ctrl_gnt && rd_i)
             ----1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       337
 EXPRESSION (ctrl_gnt && prog_i)
             ----1---    ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       387
 EXPRESSION ((ctrl_fsm_idle & ctrl_rsp_vld) | ((host_outstanding == '0) & host_req_done_o))
             ---------------1--------------   ----------------------2---------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered

 LINE       387
 SUB-EXPRESSION (ctrl_fsm_idle & ctrl_rsp_vld)
                 ------1------   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Not Covered

 LINE       387
 SUB-EXPRESSION ((host_outstanding == '0) & host_req_done_o)
                 ------------1-----------   -------2-------
-1--2-StatusTests
01CoveredT4,T6,T26
10CoveredT1,T2,T3
11Not Covered

 LINE       387
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       391
 EXPRESSION (host_sel ? host_addr_i : addr_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T6,T26

 LINE       392
 EXPRESSION (host_sel ? FlashPartData : part_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T6,T26

 LINE       393
 EXPRESSION (host_sel ? host_scramble_en_i : scramble_en_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T6,T26

 LINE       394
 EXPRESSION (host_sel ? host_ecc_en_i : ecc_en_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T6,T26

 LINE       395
 EXPRESSION (ctrl_rsp_vld & rd_i)
             ------1-----   --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       396
 EXPRESSION (ctrl_rsp_vld & prog_i)
             ------1-----   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       397
 EXPRESSION (ctrl_rsp_vld & (pg_erase_i | bk_erase_i))
             ------1-----   ------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       397
 SUB-EXPRESSION (pg_erase_i | bk_erase_i)
                 -----1----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T42,T43
10CoveredT1,T2,T3

 LINE       427
 EXPRESSION ((host_gnt_rd_err & (host_outstanding == 1'b1)) | host_outstanding_rd_err)
             -----------------------1----------------------   -----------2-----------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered

 LINE       427
 SUB-EXPRESSION (host_gnt_rd_err & (host_outstanding == 1'b1))
                 -------1-------   -------------2------------
-1--2-StatusTests
01CoveredT4,T6,T26
10Not Covered
11Not Covered

 LINE       427
 SUB-EXPRESSION (host_outstanding == 1'b1)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T6,T26

 LINE       430
 EXPRESSION (phy_req & (rd_i | host_req))
             ---1---   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       430
 SUB-EXPRESSION (rd_i | host_req)
                 --1-   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T6,T26
10CoveredT1,T2,T3

 LINE       430
 EXPRESSION (arb_host_gnt_err ? ({flash_phy_pkg::FullDataWidth {1'b1}}) : flash_rdata)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       521
 EXPRESSION (fsm_err | prog_fsm_err)
             ---1---   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered

 LINE       548
 EXPRESSION (prog_calc_req | rd_calc_req)
             ------1------   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T4,T6
10CoveredT1,T6,T11

 LINE       549
 EXPRESSION (prog_op_req | rd_op_req)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T6,T42
10CoveredT1,T6,T11

 LINE       550
 EXPRESSION (prog_op_req ? ScrambleOp : DeScrambleOp)
             -----1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T6,T11

 LINE       551
 EXPRESSION (prog_calc_req ? muxed_addr[(flash_phy_pkg::BusBankAddrW - 1):flash_phy_pkg::LsbAddrBit] : rd_calc_addr)
             ------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T6,T11

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core
Summary for FSM :: state_q
TotalCoveredPercent
States 5 5 100.00 (Not included in score)
Transitions 7 7 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
StCtrl 340 Covered T1,T2,T3
StCtrlProg 338 Covered T2,T3,T5
StCtrlRead 336 Covered T2,T3,T5
StDisable 334 Covered T1,T21,T22
StIdle 348 Covered T1,T2,T3


transitionsLine No.CoveredTests
StCtrl->StIdle 368 Covered T1,T2,T3
StCtrlProg->StIdle 358 Covered T2,T3,T5
StCtrlRead->StIdle 348 Covered T2,T3,T5
StIdle->StCtrl 340 Covered T1,T2,T3
StIdle->StCtrlProg 338 Covered T2,T3,T5
StIdle->StCtrlRead 336 Covered T2,T3,T5
StIdle->StDisable 334 Covered T1,T21,T22



Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core
Line No.TotalCoveredPercent
Branches 46 45 97.83
TERNARY 316 2 2 100.00
TERNARY 391 2 2 100.00
TERNARY 392 2 2 100.00
TERNARY 393 2 2 100.00
TERNARY 394 2 2 100.00
TERNARY 550 2 2 100.00
TERNARY 551 2 2 100.00
TERNARY 430 2 1 50.00
IF 151 4 4 100.00
IF 164 2 2 100.00
IF 202 3 3 100.00
IF 214 4 4 100.00
IF 228 4 4 100.00
CASE 330 13 13 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 316 ((phy_req & host_req)) ?

Branches:
-1-StatusTests
1 Covered T4,T6,T26
0 Covered T1,T2,T3


LineNo. Expression -1-: 391 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T4,T6,T26
0 Covered T1,T2,T3


LineNo. Expression -1-: 392 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T4,T6,T26
0 Covered T1,T2,T3


LineNo. Expression -1-: 393 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T4,T6,T26
0 Covered T1,T2,T3


LineNo. Expression -1-: 394 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T4,T6,T26
0 Covered T1,T2,T3


LineNo. Expression -1-: 550 (prog_op_req) ?

Branches:
-1-StatusTests
1 Covered T1,T6,T11
0 Covered T1,T2,T3


LineNo. Expression -1-: 551 (prog_calc_req) ?

Branches:
-1-StatusTests
1 Covered T1,T6,T11
0 Covered T1,T2,T3


LineNo. Expression -1-: 430 (arb_host_gnt_err) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 151 if ((!rst_ni)) -2-: 153 if (ctrl_rsp_vld) -3-: 155 if (inc_arb_cnt)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T6,T16,T17
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 164 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 202 if ((!rst_ni)) -2-: 204 if ((host_gnt_err_event | host_outstanding_err_event))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T20,T23,T24
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 214 if ((!rst_ni)) -2-: 216 if ((host_outstanding == '0)) -3-: 218 if (host_gnt_err_event)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T20,T23,T24
0 0 0 Covered T4,T6,T26


LineNo. Expression -1-: 228 if ((!rst_ni)) -2-: 230 if (((host_outstanding == '0) && ctrl_fsm_idle)) -3-: 232 if (host_outstanding_err_event)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T20,T23,T24
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 330 case (state_q) -2-: 333 if (prim_mubi_pkg::mubi4_test_true_loose(flash_disable[FsmDisableIdx])) -3-: 335 if ((ctrl_gnt && rd_i)) -4-: 337 if ((ctrl_gnt && prog_i)) -5-: 339 if (ctrl_gnt) -6-: 346 if (rd_stage_data_valid) -7-: 356 if (prog_ack) -8-: 366 if (erase_ack)

Branches:
-1--2--3--4--5--6--7--8-StatusTests
StIdle 1 - - - - - - Covered T1,T21,T22
StIdle 0 1 - - - - - Covered T1,T2,T3
StIdle 0 0 1 - - - - Covered T1,T2,T3
StIdle 0 0 0 1 - - - Covered T1,T2,T3
StIdle 0 0 0 0 - - - Covered T1,T2,T3
StCtrlRead - - - - 1 - - Covered T1,T2,T3
StCtrlRead - - - - 0 - - Covered T1,T2,T3
StCtrlProg - - - - - 1 - Covered T1,T2,T3
StCtrlProg - - - - - 0 - Covered T1,T2,T3
StCtrl - - - - - - 1 Covered T1,T2,T3
StCtrl - - - - - - 0 Covered T1,T2,T3
StDisable - - - - - - - Covered T1,T21,T22
default - - - - - - - Covered T20,T23,T24


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 8 8 100.00 8 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 8 8 100.00 8 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
ArbCntMax_A 348705990 1932443 0 0
CtrlPrio_A 348705990 1932443 0 0
HostTransIdleChk_A 348705990 20380045 0 0
NoRemainder_A 875 875 0 0
OneHotReqs_A 348705990 348098510 0 0
Pow2Multiple_A 875 875 0 0
RdTxnCheck_A 348705990 348098510 0 0
u_state_regs_A 348705990 348098510 0 0


ArbCntMax_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 348705990 1932443 0 0
T6 470651 5505 0 0
T10 64403 0 0 0
T12 0 31209 0 0
T13 0 2448 0 0
T14 0 2634 0 0
T16 73516 1430 0 0
T17 0 1320 0 0
T25 1269 0 0 0
T26 782859 0 0 0
T33 0 5984 0 0
T42 204557 0 0 0
T49 187575 0 0 0
T61 1114 0 0 0
T72 1611 0 0 0
T73 73281 0 0 0
T92 0 1964 0 0
T129 0 7213 0 0
T162 0 43157 0 0

CtrlPrio_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 348705990 1932443 0 0
T6 470651 5505 0 0
T10 64403 0 0 0
T12 0 31209 0 0
T13 0 2448 0 0
T14 0 2634 0 0
T16 73516 1430 0 0
T17 0 1320 0 0
T25 1269 0 0 0
T26 782859 0 0 0
T33 0 5984 0 0
T42 204557 0 0 0
T49 187575 0 0 0
T61 1114 0 0 0
T72 1611 0 0 0
T73 73281 0 0 0
T92 0 1964 0 0
T129 0 7213 0 0
T162 0 43157 0 0

HostTransIdleChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 348705990 20380045 0 0
T4 967 2 0 0
T5 3254 0 0 0
T6 470651 61915 0 0
T10 64403 0 0 0
T11 0 40 0 0
T15 82348 0 0 0
T16 0 16790 0 0
T17 0 17174 0 0
T21 0 35 0 0
T25 1269 0 0 0
T26 782859 196608 0 0
T33 0 62273 0 0
T49 187575 0 0 0
T55 0 28 0 0
T61 1114 0 0 0
T64 0 60 0 0
T73 73281 0 0 0

NoRemainder_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 875 875 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T25 1 1 0 0
T26 1 1 0 0

OneHotReqs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 348705990 348098510 0 0
T1 400453 400435 0 0
T2 434329 434232 0 0
T3 95517 95384 0 0
T4 967 822 0 0
T5 3254 3167 0 0
T6 470651 470596 0 0
T10 64403 64352 0 0
T15 82348 78546 0 0
T25 1269 1199 0 0
T26 782859 782851 0 0

Pow2Multiple_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 875 875 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T25 1 1 0 0
T26 1 1 0 0

RdTxnCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 348705990 348098510 0 0
T1 400453 400435 0 0
T2 434329 434232 0 0
T3 95517 95384 0 0
T4 967 822 0 0
T5 3254 3167 0 0
T6 470651 470596 0 0
T10 64403 64352 0 0
T15 82348 78546 0 0
T25 1269 1199 0 0
T26 782859 782851 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 348705990 348098510 0 0
T1 400453 400435 0 0
T2 434329 434232 0 0
T3 95517 95384 0 0
T4 967 822 0 0
T5 3254 3167 0 0
T6 470651 470596 0 0
T10 64403 64352 0 0
T15 82348 78546 0 0
T25 1269 1199 0 0
T26 782859 782851 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core
Line No.TotalCoveredPercent
TOTAL8989100.00
ALWAYS15166100.00
ALWAYS16433100.00
CONT_ASSIGN19511100.00
CONT_ASSIGN19911100.00
ALWAYS20244100.00
ALWAYS21466100.00
ALWAYS22866100.00
CONT_ASSIGN27611100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28611100.00
CONT_ASSIGN31611100.00
CONT_ASSIGN32011100.00
ALWAYS3242929100.00
CONT_ASSIGN38711100.00
CONT_ASSIGN39111100.00
CONT_ASSIGN39211100.00
CONT_ASSIGN39311100.00
CONT_ASSIGN39411100.00
CONT_ASSIGN39511100.00
CONT_ASSIGN39611100.00
CONT_ASSIGN39711100.00
CONT_ASSIGN41411100.00
CONT_ASSIGN42711100.00
CONT_ASSIGN52111100.00
CONT_ASSIGN54811100.00
CONT_ASSIGN54911100.00
CONT_ASSIGN55011100.00
CONT_ASSIGN55111100.00
CONT_ASSIGN55311100.00
CONT_ASSIGN55411100.00
CONT_ASSIGN55511100.00
CONT_ASSIGN55611100.00
CONT_ASSIGN55711100.00
CONT_ASSIGN55811100.00
CONT_ASSIGN55911100.00
CONT_ASSIGN56611100.00
CONT_ASSIGN58311100.00
CONT_ASSIGN58411100.00
CONT_ASSIGN58511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
151 1 1
152 1 1
153 1 1
154 1 1
155 1 1
156 1 1
MISSING_ELSE
164 3 3
195 1 1
199 1 1
202 1 1
203 1 1
204 1 1
205 1 1
MISSING_ELSE
214 1 1
215 1 1
216 1 1
217 1 1
218 1 1
219 1 1
MISSING_ELSE
228 1 1
229 1 1
230 1 1
231 1 1
232 1 1
233 1 1
MISSING_ELSE
276 1 1
279 1 1
280 1 1
281 1 1
286 1 1
316 1 1
320 1 1
324 1 1
325 1 1
326 1 1
327 1 1
328 1 1
330 1 1
332 1 1
333 1 1
334 1 1
335 1 1
336 1 1
337 1 1
338 1 1
339 1 1
340 1 1
MISSING_ELSE
346 1 1
347 1 1
348 1 1
MISSING_ELSE
355 1 1
356 1 1
357 1 1
358 1 1
MISSING_ELSE
364 1 1
365 1 1
366 1 1
367 1 1
368 1 1
MISSING_ELSE
373 1 1
374 1 1
387 1 1
391 1 1
392 1 1
393 1 1
394 1 1
395 1 1
396 1 1
397 1 1
414 1 1
427 1 1
521 1 1
548 1 1
549 1 1
550 1 1
551 1 1
553 1 1
554 1 1
555 1 1
556 1 1
557 1 1
558 1 1
559 1 1
566 1 1
583 1 1
584 1 1
585 1 1


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core
TotalCoveredPercent
Conditions1069690.57
Logical1069690.57
Non-Logical00
Event00

 LINE       195
 EXPRESSION (host_gnt && (muxed_part != FlashPartData))
             ----1---    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT6,T16,T17
11CoveredT20,T23,T24

 LINE       195
 SUB-EXPRESSION (muxed_part != FlashPartData)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       199
 EXPRESSION (((|host_outstanding)) & ((!ctrl_fsm_idle)))
             ----------1----------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT6,T16,T17
11Not Covered

 LINE       204
 EXPRESSION (host_gnt_err_event | host_outstanding_err_event)
             ---------1--------   -------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT20,T23,T24

 LINE       216
 EXPRESSION (host_outstanding == '0)
            ------------1-----------
-1-StatusTests
0CoveredT6,T16,T17
1CoveredT1,T2,T3

 LINE       230
 EXPRESSION ((host_outstanding == '0) && ctrl_fsm_idle)
             ------------1-----------    ------2------
-1--2-StatusTests
01CoveredT6,T16,T17
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       230
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------
-1-StatusTests
0CoveredT6,T16,T17
1CoveredT1,T2,T3

 LINE       241
 EXPRESSION (host_gnt && ((!host_req_done_o)) && (host_outstanding <= flash_phy_pkg::RspOrderDepth))
             ----1---    ----------2---------    -------------------------3------------------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT6,T16,T17
110Not Covered
111CoveredT6,T16,T17

 LINE       241
 EXPRESSION (((!host_gnt)) && host_req_done_o && ((|host_outstanding)))
             ------1------    -------2-------    ----------3----------
-1--2--3-StatusTests
011CoveredT6,T16,T17
101CoveredT6,T16,T17
110CoveredT4,T127,T128
111CoveredT6,T16,T17

 LINE       280
 EXPRESSION (host_req & host_req_rdy_o)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT96
10CoveredT6,T16,T17
11CoveredT6,T16,T17

 LINE       281
 EXPRESSION (((|host_outstanding)) & rd_stage_data_valid)
             ----------1----------   ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT6,T16,T17
11CoveredT6,T16,T17

 LINE       316
 EXPRESSION ((phy_req & host_req) ? rd_stage_rdy : rd_stage_idle)
             ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT6,T16,T17

 LINE       316
 SUB-EXPRESSION (phy_req & host_req)
                 ---1---   ----2---
-1--2-StatusTests
01CoveredT159
10CoveredT1,T2,T3
11CoveredT6,T16,T17

 LINE       320
 EXPRESSION (req_i & host_gnt)
             --1--   ----2---
-1--2-StatusTests
01CoveredT6,T16,T17
10CoveredT1,T2,T3
11CoveredT6,T16,T17

 LINE       335
 EXPRESSION (ctrl_gnt && rd_i)
             ----1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       337
 EXPRESSION (ctrl_gnt && prog_i)
             ----1---    ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       387
 EXPRESSION ((ctrl_fsm_idle & ctrl_rsp_vld) | ((host_outstanding == '0) & host_req_done_o))
             ---------------1--------------   ----------------------2---------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T127,T128
10CoveredT142

 LINE       387
 SUB-EXPRESSION (ctrl_fsm_idle & ctrl_rsp_vld)
                 ------1------   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT142

 LINE       387
 SUB-EXPRESSION ((host_outstanding == '0) & host_req_done_o)
                 ------------1-----------   -------2-------
-1--2-StatusTests
01CoveredT6,T16,T17
10CoveredT1,T2,T3
11CoveredT4,T127,T128

 LINE       387
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       391
 EXPRESSION (host_sel ? host_addr_i : addr_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT6,T16,T17

 LINE       392
 EXPRESSION (host_sel ? FlashPartData : part_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT6,T16,T17

 LINE       393
 EXPRESSION (host_sel ? host_scramble_en_i : scramble_en_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT6,T16,T17

 LINE       394
 EXPRESSION (host_sel ? host_ecc_en_i : ecc_en_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT6,T16,T17

 LINE       395
 EXPRESSION (ctrl_rsp_vld & rd_i)
             ------1-----   --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       396
 EXPRESSION (ctrl_rsp_vld & prog_i)
             ------1-----   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       397
 EXPRESSION (ctrl_rsp_vld & (pg_erase_i | bk_erase_i))
             ------1-----   ------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       397
 SUB-EXPRESSION (pg_erase_i | bk_erase_i)
                 -----1----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T42,T43
10CoveredT1,T2,T3

 LINE       427
 EXPRESSION ((host_gnt_rd_err & (host_outstanding == 1'b1)) | host_outstanding_rd_err)
             -----------------------1----------------------   -----------2-----------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered

 LINE       427
 SUB-EXPRESSION (host_gnt_rd_err & (host_outstanding == 1'b1))
                 -------1-------   -------------2------------
-1--2-StatusTests
01CoveredT6,T16,T17
10Not Covered
11Not Covered

 LINE       427
 SUB-EXPRESSION (host_outstanding == 1'b1)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT6,T16,T17

 LINE       430
 EXPRESSION (phy_req & (rd_i | host_req))
             ---1---   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       430
 SUB-EXPRESSION (rd_i | host_req)
                 --1-   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT6,T16,T17
10CoveredT1,T2,T3

 LINE       430
 EXPRESSION (arb_host_gnt_err ? ({flash_phy_pkg::FullDataWidth {1'b1}}) : flash_rdata)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       521
 EXPRESSION (fsm_err | prog_fsm_err)
             ---1---   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered

 LINE       548
 EXPRESSION (prog_calc_req | rd_calc_req)
             ------1------   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T4,T15

 LINE       549
 EXPRESSION (prog_op_req | rd_op_req)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T4,T15

 LINE       550
 EXPRESSION (prog_op_req ? ScrambleOp : DeScrambleOp)
             -----1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T15

 LINE       551
 EXPRESSION (prog_calc_req ? muxed_addr[(flash_phy_pkg::BusBankAddrW - 1):flash_phy_pkg::LsbAddrBit] : rd_calc_addr)
             ------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T15

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core
Summary for FSM :: state_q
TotalCoveredPercent
States 5 5 100.00 (Not included in score)
Transitions 7 7 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
StCtrl 340 Covered T1,T2,T3
StCtrlProg 338 Covered T1,T2,T3
StCtrlRead 336 Covered T1,T2,T3
StDisable 334 Covered T1,T21,T79
StIdle 348 Covered T1,T2,T3


transitionsLine No.CoveredTests
StCtrl->StIdle 368 Covered T1,T2,T3
StCtrlProg->StIdle 358 Covered T1,T2,T3
StCtrlRead->StIdle 348 Covered T1,T2,T3
StIdle->StCtrl 340 Covered T1,T2,T3
StIdle->StCtrlProg 338 Covered T1,T2,T3
StIdle->StCtrlRead 336 Covered T1,T2,T3
StIdle->StDisable 334 Covered T1,T21,T79



Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core
Line No.TotalCoveredPercent
Branches 46 45 97.83
TERNARY 316 2 2 100.00
TERNARY 391 2 2 100.00
TERNARY 392 2 2 100.00
TERNARY 393 2 2 100.00
TERNARY 394 2 2 100.00
TERNARY 550 2 2 100.00
TERNARY 551 2 2 100.00
TERNARY 430 2 1 50.00
IF 151 4 4 100.00
IF 164 2 2 100.00
IF 202 3 3 100.00
IF 214 4 4 100.00
IF 228 4 4 100.00
CASE 330 13 13 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 316 ((phy_req & host_req)) ?

Branches:
-1-StatusTests
1 Covered T6,T16,T17
0 Covered T1,T2,T3


LineNo. Expression -1-: 391 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T6,T16,T17
0 Covered T1,T2,T3


LineNo. Expression -1-: 392 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T6,T16,T17
0 Covered T1,T2,T3


LineNo. Expression -1-: 393 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T6,T16,T17
0 Covered T1,T2,T3


LineNo. Expression -1-: 394 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T6,T16,T17
0 Covered T1,T2,T3


LineNo. Expression -1-: 550 (prog_op_req) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T15
0 Covered T1,T2,T3


LineNo. Expression -1-: 551 (prog_calc_req) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T15
0 Covered T1,T2,T3


LineNo. Expression -1-: 430 (arb_host_gnt_err) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 151 if ((!rst_ni)) -2-: 153 if (ctrl_rsp_vld) -3-: 155 if (inc_arb_cnt)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T6,T16,T17
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 164 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 202 if ((!rst_ni)) -2-: 204 if ((host_gnt_err_event | host_outstanding_err_event))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T20,T23,T24
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 214 if ((!rst_ni)) -2-: 216 if ((host_outstanding == '0)) -3-: 218 if (host_gnt_err_event)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T20,T23,T24
0 0 0 Covered T6,T16,T17


LineNo. Expression -1-: 228 if ((!rst_ni)) -2-: 230 if (((host_outstanding == '0) && ctrl_fsm_idle)) -3-: 232 if (host_outstanding_err_event)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T20,T23,T24
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 330 case (state_q) -2-: 333 if (prim_mubi_pkg::mubi4_test_true_loose(flash_disable[FsmDisableIdx])) -3-: 335 if ((ctrl_gnt && rd_i)) -4-: 337 if ((ctrl_gnt && prog_i)) -5-: 339 if (ctrl_gnt) -6-: 346 if (rd_stage_data_valid) -7-: 356 if (prog_ack) -8-: 366 if (erase_ack)

Branches:
-1--2--3--4--5--6--7--8-StatusTests
StIdle 1 - - - - - - Covered T1,T21,T22
StIdle 0 1 - - - - - Covered T1,T2,T3
StIdle 0 0 1 - - - - Covered T1,T2,T3
StIdle 0 0 0 1 - - - Covered T1,T2,T3
StIdle 0 0 0 0 - - - Covered T1,T2,T3
StCtrlRead - - - - 1 - - Covered T1,T2,T3
StCtrlRead - - - - 0 - - Covered T1,T2,T3
StCtrlProg - - - - - 1 - Covered T1,T2,T3
StCtrlProg - - - - - 0 - Covered T1,T2,T3
StCtrl - - - - - - 1 Covered T1,T2,T3
StCtrl - - - - - - 0 Covered T1,T2,T3
StDisable - - - - - - - Covered T1,T21,T79
default - - - - - - - Covered T20,T23,T24


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 8 8 100.00 8 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 8 8 100.00 8 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
ArbCntMax_A 348705990 1885672 0 0
CtrlPrio_A 348705990 1885667 0 0
HostTransIdleChk_A 348705990 20503741 0 0
NoRemainder_A 875 875 0 0
OneHotReqs_A 348705990 348098510 0 0
Pow2Multiple_A 875 875 0 0
RdTxnCheck_A 348705990 348098510 0 0
u_state_regs_A 348705990 348098510 0 0


ArbCntMax_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 348705990 1885672 0 0
T6 470651 4987 0 0
T10 64403 0 0 0
T12 0 50882 0 0
T13 0 3897 0 0
T14 0 3475 0 0
T16 73516 1756 0 0
T17 0 1737 0 0
T25 1269 0 0 0
T26 782859 0 0 0
T33 0 11384 0 0
T42 204557 0 0 0
T49 187575 0 0 0
T61 1114 0 0 0
T72 1611 0 0 0
T73 73281 0 0 0
T92 0 815 0 0
T129 0 9742 0 0
T162 0 44599 0 0

CtrlPrio_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 348705990 1885667 0 0
T6 470651 4987 0 0
T10 64403 0 0 0
T12 0 50882 0 0
T13 0 3897 0 0
T14 0 3475 0 0
T16 73516 1756 0 0
T17 0 1737 0 0
T25 1269 0 0 0
T26 782859 0 0 0
T33 0 11384 0 0
T42 204557 0 0 0
T49 187575 0 0 0
T61 1114 0 0 0
T72 1611 0 0 0
T73 73281 0 0 0
T92 0 815 0 0
T129 0 9742 0 0
T162 0 44599 0 0

HostTransIdleChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 348705990 20503741 0 0
T6 470651 55177 0 0
T10 64403 0 0 0
T12 0 443955 0 0
T13 0 27235 0 0
T16 73516 16048 0 0
T17 0 16374 0 0
T25 1269 0 0 0
T26 782859 0 0 0
T33 0 79245 0 0
T42 204557 0 0 0
T49 187575 0 0 0
T61 1114 0 0 0
T64 0 143 0 0
T72 1611 0 0 0
T73 73281 0 0 0
T87 0 15 0 0
T92 0 14825 0 0
T93 0 220 0 0

NoRemainder_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 875 875 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T25 1 1 0 0
T26 1 1 0 0

OneHotReqs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 348705990 348098510 0 0
T1 400453 400435 0 0
T2 434329 434232 0 0
T3 95517 95384 0 0
T4 967 822 0 0
T5 3254 3167 0 0
T6 470651 470596 0 0
T10 64403 64352 0 0
T15 82348 78546 0 0
T25 1269 1199 0 0
T26 782859 782851 0 0

Pow2Multiple_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 875 875 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T25 1 1 0 0
T26 1 1 0 0

RdTxnCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 348705990 348098510 0 0
T1 400453 400435 0 0
T2 434329 434232 0 0
T3 95517 95384 0 0
T4 967 822 0 0
T5 3254 3167 0 0
T6 470651 470596 0 0
T10 64403 64352 0 0
T15 82348 78546 0 0
T25 1269 1199 0 0
T26 782859 782851 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 348705990 348098510 0 0
T1 400453 400435 0 0
T2 434329 434232 0 0
T3 95517 95384 0 0
T4 967 822 0 0
T5 3254 3167 0 0
T6 470651 470596 0 0
T10 64403 64352 0 0
T15 82348 78546 0 0
T25 1269 1199 0 0
T26 782859 782851 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%