Unified Coverage Report :: Module :: flash_phy

Module : flash_phy

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.89	97.67	90.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash	95.89	97.67	90.00			100.00

---

Module Instance : tb.dut.u_eflash

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.89	97.67	90.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.32	98.50	92.39	93.72	96.43	99.07	97.81

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
84.89	97.12	87.20	98.44		100.00	41.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flash_cores[0].u_core	97.26	97.92	92.71	96.12	100.00	98.86	97.94
gen_flash_cores[0].u_host_rsp_fifo	88.08	100.00	78.72	70.00		91.67	100.00
gen_flash_cores[1].u_core	96.60	97.92	91.86	93.02	100.00	98.86	97.94
gen_flash_cores[1].u_host_rsp_fifo	87.23	100.00	74.47	70.00		91.67	100.00
u_bank_sequence_fifo	96.53	100.00	86.11			100.00	100.00
u_disable_buf	100.00	100.00					100.00
u_flash	95.48	98.80	94.49	89.59	90.62	99.37	100.00
u_lc_nvm_debug_en_sync	100.00	100.00				100.00	100.00
u_region_sel	98.61	100.00	95.83			100.00
u_scramble	97.19	100.00	90.50	100.00		100.00	95.45

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : flash_phy

	Line No.	Total	Covered	Percent
TOTAL		43	42	97.67
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	127	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	0	0
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	135	1	1	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	177	1	1	100.00
CONT_ASSIGN	177	1	1	100.00
CONT_ASSIGN	177	1	1	100.00
CONT_ASSIGN	177	1	1	100.00
CONT_ASSIGN	177	1	1	100.00
CONT_ASSIGN	177	1	1	100.00
CONT_ASSIGN	177	1	1	100.00
CONT_ASSIGN	177	1	1	100.00
CONT_ASSIGN	177	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	198	1	1	100.00
CONT_ASSIGN	200	1	1	100.00
CONT_ASSIGN	210	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	229	1	1	100.00
CONT_ASSIGN	229	1	1	100.00
CONT_ASSIGN	253	1	1	100.00
CONT_ASSIGN	253	1	1	100.00
CONT_ASSIGN	254	1	1	100.00
CONT_ASSIGN	254	1	1	100.00
CONT_ASSIGN	331	0	0
CONT_ASSIGN	347	1	1	100.00
CONT_ASSIGN	387	1	1	100.00
CONT_ASSIGN	390	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
120	1	1
121	1	1
124	1	1
127	1	1
128	1	1
129	1	1
132		unreachable
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
143	1	1
144	1	1
145	1	1
146	1	1
177	9	9
192	1	1
198	1	1
200	1	1
210	1	1
211	1	1
229	2	2
253	2	2
254	2	2
331		unreachable
347	1	1
387	1	1
390	0	1

---

Cond Coverage for Module : flash_phy

	Total	Covered	Percent
Conditions	50	45	90.00
Logical	50	45	90.00
Non-Logical	0	0
Event	0	0

 LINE       120
 EXPRESSION (host_req_i ? host_addr_i[(flash_ctrl_pkg::BusAddrW - 1)-:flash_ctrl_pkg::BankW] : '0)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T26

 LINE       124
 EXPRESSION (host_req_rdy[host_bank_sel] & host_rsp_avail[host_bank_sel] & seq_fifo_rdy)
             -------------1-------------   --------------2--------------   ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T96
1	1	1	Covered	T4,T6,T26

 LINE       127
 EXPRESSION (seq_fifo_pending & host_rsp_vld[rsp_bank_sel])
             --------1-------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T127,T128
1	0	Covered	T4,T6,T26
1	1	Covered	T4,T6,T26

 LINE       144
 EXPRESSION (((|arb_err)) | scramble_arb_err)
             ------1-----   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T158,T156,T157
1	0	Covered	T96,T159

 LINE       154
 EXPRESSION (host_req_i & host_req_rdy_o)
             -----1----   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T96
1	0	Covered	T4,T6,T16
1	1	Covered	T4,T6,T26

 LINE       229
 EXPRESSION (host_req_done_o & (rsp_bank_sel == 0))
             -------1-------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T26
1	1	Covered	T6,T16,T17

 LINE       229
 SUB-EXPRESSION (rsp_bank_sel == 0)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       229
 EXPRESSION (host_req_done_o & (rsp_bank_sel == 1))
             -------1-------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T26
1	0	Covered	T6,T16,T17
1	1	Covered	T4,T6,T26

 LINE       229
 SUB-EXPRESSION (rsp_bank_sel == 1)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T26

 LINE       253
 EXPRESSION (host_req_i & (host_bank_sel == 0) & host_rsp_avail[0])
             -----1----   ----------2---------   --------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T6,T26,T16
1	1	0	Covered	T4,T6,T33
1	1	1	Covered	T6,T16,T17

 LINE       253
 SUB-EXPRESSION (host_bank_sel == 0)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       253
 EXPRESSION (host_req_i & (host_bank_sel == 1) & host_rsp_avail[1])
             -----1----   ----------2---------   --------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T6,T16
1	1	0	Covered	T6,T33,T129
1	1	1	Covered	T4,T6,T26

 LINE       253
 SUB-EXPRESSION (host_bank_sel == 1)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T26

 LINE       254
 EXPRESSION (flash_ctrl_i.req & (ctrl_bank_sel == 0))
             --------1-------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       254
 SUB-EXPRESSION (ctrl_bank_sel == 0)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       254
 EXPRESSION (flash_ctrl_i.req & (ctrl_bank_sel == 1))
             --------1-------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       254
 SUB-EXPRESSION (ctrl_bank_sel == 1)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       387
 EXPRESSION (flash_ctrl_i.alert_trig & flash_ctrl_i.alert_ack)
             -----------1-----------   -----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

Branch Coverage for Module : flash_phy

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	120	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	120	(host_req_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T26
0	Covered	T1,T2,T3