Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.17 100.00 83.02 100.00 97.83 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.61 97.92 91.93 93.02 100.00 98.86 97.94


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.56 97.67 86.00 100.00 u_eflash


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prog_data.u_prog 98.65 100.00 96.92 95.00 100.00 100.00 100.00
u_disable_buf 100.00 100.00 100.00
u_erase 97.22 100.00 88.89 100.00 100.00
u_host_arb 93.98 75.93 100.00 100.00 100.00
u_host_outstanding_cnt 88.89 88.89
u_rd 95.24 99.17 92.25 90.00 98.55 96.23
u_state_regs 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.49 100.00 89.62 100.00 97.83 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.26 97.92 92.71 96.12 100.00 98.86 97.94


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.56 97.67 86.00 100.00 u_eflash


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prog_data.u_prog 99.74 100.00 98.46 100.00 100.00 100.00 100.00
u_disable_buf 100.00 100.00 100.00
u_erase 97.22 100.00 88.89 100.00 100.00
u_host_arb 93.98 75.93 100.00 100.00 100.00
u_host_outstanding_cnt 88.89 88.89
u_rd 95.29 99.17 92.50 90.00 98.55 96.23
u_state_regs 100.00 100.00 100.00 100.00

Line Coverage for Module : flash_phy_core
Line No.TotalCoveredPercent
TOTAL8989100.00
ALWAYS15166100.00
ALWAYS16433100.00
CONT_ASSIGN19511100.00
CONT_ASSIGN19911100.00
ALWAYS20244100.00
ALWAYS21466100.00
ALWAYS22866100.00
CONT_ASSIGN27611100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28611100.00
CONT_ASSIGN31611100.00
CONT_ASSIGN32011100.00
ALWAYS3242929100.00
CONT_ASSIGN38711100.00
CONT_ASSIGN39111100.00
CONT_ASSIGN39211100.00
CONT_ASSIGN39311100.00
CONT_ASSIGN39411100.00
CONT_ASSIGN39511100.00
CONT_ASSIGN39611100.00
CONT_ASSIGN39711100.00
CONT_ASSIGN41411100.00
CONT_ASSIGN42711100.00
CONT_ASSIGN52111100.00
CONT_ASSIGN54811100.00
CONT_ASSIGN54911100.00
CONT_ASSIGN55011100.00
CONT_ASSIGN55111100.00
CONT_ASSIGN55311100.00
CONT_ASSIGN55411100.00
CONT_ASSIGN55511100.00
CONT_ASSIGN55611100.00
CONT_ASSIGN55711100.00
CONT_ASSIGN55811100.00
CONT_ASSIGN55911100.00
CONT_ASSIGN56611100.00
CONT_ASSIGN58311100.00
CONT_ASSIGN58411100.00
CONT_ASSIGN58511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
151 1 1
152 1 1
153 1 1
154 1 1
155 1 1
156 1 1
MISSING_ELSE
164 3 3
195 1 1
199 1 1
202 1 1
203 1 1
204 1 1
205 1 1
MISSING_ELSE
214 1 1
215 1 1
216 1 1
217 1 1
218 1 1
219 1 1
MISSING_ELSE
228 1 1
229 1 1
230 1 1
231 1 1
232 1 1
233 1 1
MISSING_ELSE
276 1 1
279 1 1
280 1 1
281 1 1
286 1 1
316 1 1
320 1 1
324 1 1
325 1 1
326 1 1
327 1 1
328 1 1
330 1 1
332 1 1
333 1 1
334 1 1
335 1 1
336 1 1
337 1 1
338 1 1
339 1 1
340 1 1
MISSING_ELSE
346 1 1
347 1 1
348 1 1
MISSING_ELSE
355 1 1
356 1 1
357 1 1
358 1 1
MISSING_ELSE
364 1 1
365 1 1
366 1 1
367 1 1
368 1 1
MISSING_ELSE
373 1 1
374 1 1
387 1 1
391 1 1
392 1 1
393 1 1
394 1 1
395 1 1
396 1 1
397 1 1
414 1 1
427 1 1
521 1 1
548 1 1
549 1 1
550 1 1
551 1 1
553 1 1
554 1 1
555 1 1
556 1 1
557 1 1
558 1 1
559 1 1
566 1 1
583 1 1
584 1 1
585 1 1


Cond Coverage for Module : flash_phy_core
TotalCoveredPercent
Conditions1069690.57
Logical1069690.57
Non-Logical00
Event00

 LINE       195
 EXPRESSION (host_gnt && (muxed_part != FlashPartData))
             ----1---    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T16,T4
11CoveredT18,T171,T22

 LINE       195
 SUB-EXPRESSION (muxed_part != FlashPartData)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       199
 EXPRESSION (((|host_outstanding)) & ((!ctrl_fsm_idle)))
             ----------1----------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T16,T4
11Not Covered

 LINE       204
 EXPRESSION (host_gnt_err_event | host_outstanding_err_event)
             ---------1--------   -------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT18,T171,T22

 LINE       216
 EXPRESSION (host_outstanding == '0)
            ------------1-----------
-1-StatusTests
0CoveredT2,T16,T4
1CoveredT1,T2,T3

 LINE       230
 EXPRESSION ((host_outstanding == '0) && ctrl_fsm_idle)
             ------------1-----------    ------2------
-1--2-StatusTests
01CoveredT2,T16,T4
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       230
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------
-1-StatusTests
0CoveredT2,T16,T4
1CoveredT1,T2,T3

 LINE       241
 EXPRESSION (host_gnt && ((!host_req_done_o)) && (host_outstanding <= flash_phy_pkg::RspOrderDepth))
             ----1---    ----------2---------    -------------------------3------------------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT2,T16,T4
110Not Covered
111CoveredT2,T16,T4

 LINE       241
 EXPRESSION (((!host_gnt)) && host_req_done_o && ((|host_outstanding)))
             ------1------    -------2-------    ----------3----------
-1--2--3-StatusTests
011CoveredT2,T16,T4
101CoveredT2,T16,T4
110CoveredT98
111CoveredT2,T16,T4

 LINE       280
 EXPRESSION (host_req & host_req_rdy_o)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT137
10CoveredT16,T5,T17
11CoveredT2,T16,T4

 LINE       281
 EXPRESSION (((|host_outstanding)) & rd_stage_data_valid)
             ----------1----------   ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T16,T4
11CoveredT2,T16,T4

 LINE       316
 EXPRESSION ((phy_req & host_req) ? rd_stage_rdy : rd_stage_idle)
             ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T16,T4

 LINE       316
 SUB-EXPRESSION (phy_req & host_req)
                 ---1---   ----2---
-1--2-StatusTests
01CoveredT135,T136,T197
10CoveredT1,T2,T3
11CoveredT2,T16,T4

 LINE       320
 EXPRESSION (req_i & host_gnt)
             --1--   ----2---
-1--2-StatusTests
01CoveredT2,T16,T4
10CoveredT1,T2,T3
11CoveredT16,T5,T17

 LINE       335
 EXPRESSION (ctrl_gnt && rd_i)
             ----1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       337
 EXPRESSION (ctrl_gnt && prog_i)
             ----1---    ---2--
-1--2-StatusTests
01CoveredT1,T2,T10
10CoveredT1,T2,T3
11CoveredT1,T2,T10

 LINE       387
 EXPRESSION ((ctrl_fsm_idle & ctrl_rsp_vld) | ((host_outstanding == '0) & host_req_done_o))
             ---------------1--------------   ----------------------2---------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT98
10CoveredT198,T199,T38

 LINE       387
 SUB-EXPRESSION (ctrl_fsm_idle & ctrl_rsp_vld)
                 ------1------   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT198,T199,T38

 LINE       387
 SUB-EXPRESSION ((host_outstanding == '0) & host_req_done_o)
                 ------------1-----------   -------2-------
-1--2-StatusTests
01CoveredT2,T16,T4
10CoveredT1,T2,T3
11CoveredT98

 LINE       387
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       391
 EXPRESSION (host_sel ? host_addr_i : addr_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T16,T4

 LINE       392
 EXPRESSION (host_sel ? FlashPartData : part_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T16,T4

 LINE       393
 EXPRESSION (host_sel ? host_scramble_en_i : scramble_en_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T16,T4

 LINE       394
 EXPRESSION (host_sel ? host_ecc_en_i : ecc_en_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T16,T4

 LINE       395
 EXPRESSION (ctrl_rsp_vld & rd_i)
             ------1-----   --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       396
 EXPRESSION (ctrl_rsp_vld & prog_i)
             ------1-----   ---2--
-1--2-StatusTests
01CoveredT1,T2,T10
10CoveredT1,T2,T3
11CoveredT1,T2,T10

 LINE       397
 EXPRESSION (ctrl_rsp_vld & (pg_erase_i | bk_erase_i))
             ------1-----   ------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       397
 SUB-EXPRESSION (pg_erase_i | bk_erase_i)
                 -----1----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T20,T12
10CoveredT1,T2,T3

 LINE       427
 EXPRESSION ((host_gnt_rd_err & (host_outstanding == 1'b1)) | host_outstanding_rd_err)
             -----------------------1----------------------   -----------2-----------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered

 LINE       427
 SUB-EXPRESSION (host_gnt_rd_err & (host_outstanding == 1'b1))
                 -------1-------   -------------2------------
-1--2-StatusTests
01CoveredT2,T16,T4
10Not Covered
11Not Covered

 LINE       427
 SUB-EXPRESSION (host_outstanding == 1'b1)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T16,T4

 LINE       430
 EXPRESSION (phy_req & (rd_i | host_req))
             ---1---   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       430
 SUB-EXPRESSION (rd_i | host_req)
                 --1-   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T16,T4
10CoveredT1,T2,T3

 LINE       430
 EXPRESSION (arb_host_gnt_err ? ({flash_phy_pkg::FullDataWidth {1'b1}}) : flash_rdata)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       521
 EXPRESSION (fsm_err | prog_fsm_err)
             ---1---   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered

 LINE       548
 EXPRESSION (prog_calc_req | rd_calc_req)
             ------1------   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT16,T83,T20

 LINE       549
 EXPRESSION (prog_op_req | rd_op_req)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT16,T83,T20

 LINE       550
 EXPRESSION (prog_op_req ? ScrambleOp : DeScrambleOp)
             -----1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT16,T83,T20

 LINE       551
 EXPRESSION (prog_calc_req ? muxed_addr[(flash_phy_pkg::BusBankAddrW - 1):flash_phy_pkg::LsbAddrBit] : rd_calc_addr)
             ------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT16,T83,T20

FSM Coverage for Module : flash_phy_core
Summary for FSM :: state_q
TotalCoveredPercent
States 5 5 100.00 (Not included in score)
Transitions 7 7 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
StCtrl 340 Covered T1,T2,T3
StCtrlProg 338 Covered T1,T2,T10
StCtrlRead 336 Covered T1,T2,T3
StDisable 334 Covered T20,T11,T21
StIdle 348 Covered T1,T2,T3


transitionsLine No.CoveredTests
StCtrl->StIdle 368 Covered T1,T2,T3
StCtrlProg->StIdle 358 Covered T1,T2,T10
StCtrlRead->StIdle 348 Covered T1,T2,T3
StIdle->StCtrl 340 Covered T1,T2,T3
StIdle->StCtrlProg 338 Covered T1,T2,T10
StIdle->StCtrlRead 336 Covered T1,T2,T3
StIdle->StDisable 334 Covered T20,T11,T21



Branch Coverage for Module : flash_phy_core
Line No.TotalCoveredPercent
Branches 46 45 97.83
TERNARY 316 2 2 100.00
TERNARY 391 2 2 100.00
TERNARY 392 2 2 100.00
TERNARY 393 2 2 100.00
TERNARY 394 2 2 100.00
TERNARY 550 2 2 100.00
TERNARY 551 2 2 100.00
TERNARY 430 2 1 50.00
IF 151 4 4 100.00
IF 164 2 2 100.00
IF 202 3 3 100.00
IF 214 4 4 100.00
IF 228 4 4 100.00
CASE 330 13 13 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 316 ((phy_req & host_req)) ?

Branches:
-1-StatusTests
1 Covered T2,T16,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 391 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T2,T16,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 392 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T2,T16,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 393 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T2,T16,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 394 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T2,T16,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 550 (prog_op_req) ?

Branches:
-1-StatusTests
1 Covered T16,T83,T20
0 Covered T1,T2,T3


LineNo. Expression -1-: 551 (prog_calc_req) ?

Branches:
-1-StatusTests
1 Covered T16,T83,T20
0 Covered T1,T2,T3


LineNo. Expression -1-: 430 (arb_host_gnt_err) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 151 if ((!rst_ni)) -2-: 153 if (ctrl_rsp_vld) -3-: 155 if (inc_arb_cnt)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T16,T5,T17
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 164 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 202 if ((!rst_ni)) -2-: 204 if ((host_gnt_err_event | host_outstanding_err_event))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T18,T171,T22
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 214 if ((!rst_ni)) -2-: 216 if ((host_outstanding == '0)) -3-: 218 if (host_gnt_err_event)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T18,T22,T23
0 0 0 Covered T2,T16,T4


LineNo. Expression -1-: 228 if ((!rst_ni)) -2-: 230 if (((host_outstanding == '0) && ctrl_fsm_idle)) -3-: 232 if (host_outstanding_err_event)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T18,T22,T23
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 330 case (state_q) -2-: 333 if (prim_mubi_pkg::mubi4_test_true_loose(flash_disable[FsmDisableIdx])) -3-: 335 if ((ctrl_gnt && rd_i)) -4-: 337 if ((ctrl_gnt && prog_i)) -5-: 339 if (ctrl_gnt) -6-: 346 if (rd_stage_data_valid) -7-: 356 if (prog_ack) -8-: 366 if (erase_ack)

Branches:
-1--2--3--4--5--6--7--8-StatusTests
StIdle 1 - - - - - - Covered T20,T11,T21
StIdle 0 1 - - - - - Covered T1,T2,T3
StIdle 0 0 1 - - - - Covered T1,T2,T10
StIdle 0 0 0 1 - - - Covered T1,T2,T3
StIdle 0 0 0 0 - - - Covered T1,T2,T3
StCtrlRead - - - - 1 - - Covered T1,T2,T3
StCtrlRead - - - - 0 - - Covered T1,T2,T3
StCtrlProg - - - - - 1 - Covered T1,T2,T10
StCtrlProg - - - - - 0 - Covered T1,T2,T10
StCtrl - - - - - - 1 Covered T1,T2,T3
StCtrl - - - - - - 0 Covered T1,T2,T3
StDisable - - - - - - - Covered T20,T11,T21
default - - - - - - - Covered T18,T22,T23


Assert Coverage for Module : flash_phy_core
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 8 8 100.00 8 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 8 8 100.00 8 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
ArbCntMax_A 738411270 3820880 0 0
CtrlPrio_A 738411270 3820880 0 0
HostTransIdleChk_A 738411270 40968398 0 0
NoRemainder_A 1758 1758 0 0
OneHotReqs_A 738411270 737073932 0 0
Pow2Multiple_A 1758 1758 0 0
RdTxnCheck_A 738411270 737073932 0 0
u_state_regs_A 738411270 737073932 0 0


ArbCntMax_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 738411270 3820880 0 0
T4 51978 0 0 0
T5 1670770 92906 0 0
T14 263154 5940 0 0
T15 216206 5492 0 0
T16 879516 14248 0 0
T17 118670 2332 0 0
T25 2412 0 0 0
T42 0 3997 0 0
T44 328346 0 0 0
T60 0 66126 0 0
T82 2458 0 0 0
T83 1424 0 0 0
T84 0 3042 0 0
T100 0 3491 0 0
T130 0 2696 0 0

CtrlPrio_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 738411270 3820880 0 0
T4 51978 0 0 0
T5 1670770 92906 0 0
T14 263154 5940 0 0
T15 216206 5492 0 0
T16 879516 14248 0 0
T17 118670 2332 0 0
T25 2412 0 0 0
T42 0 3997 0 0
T44 328346 0 0 0
T60 0 66126 0 0
T82 2458 0 0 0
T83 1424 0 0 0
T84 0 3042 0 0
T100 0 3491 0 0
T130 0 2696 0 0

HostTransIdleChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 738411270 40968398 0 0
T2 70426 162 0 0
T3 231244 0 0 0
T4 51978 45 0 0
T5 1670770 837012 0 0
T6 2278 0 0 0
T10 1656 0 0 0
T14 131577 56865 0 0
T15 108103 57533 0 0
T16 879516 130270 0 0
T17 118670 33546 0 0
T25 2412 0 0 0
T42 0 38448 0 0
T44 328346 0 0 0
T58 0 490 0 0
T82 1229 0 0 0
T83 712 23 0 0
T84 0 32645 0 0
T99 0 19 0 0

NoRemainder_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1758 1758 0 0
T1 2 2 0 0
T2 2 2 0 0
T3 2 2 0 0
T4 2 2 0 0
T5 2 2 0 0
T6 2 2 0 0
T10 2 2 0 0
T16 2 2 0 0
T17 2 2 0 0
T25 2 2 0 0

OneHotReqs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 738411270 737073932 0 0
T1 844250 844134 0 0
T2 140852 140726 0 0
T3 462488 462162 0 0
T4 51978 49372 0 0
T5 1670770 1670464 0 0
T6 4556 4430 0 0
T10 3312 3196 0 0
T16 879516 879404 0 0
T17 118670 118524 0 0
T25 2412 2308 0 0

Pow2Multiple_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1758 1758 0 0
T1 2 2 0 0
T2 2 2 0 0
T3 2 2 0 0
T4 2 2 0 0
T5 2 2 0 0
T6 2 2 0 0
T10 2 2 0 0
T16 2 2 0 0
T17 2 2 0 0
T25 2 2 0 0

RdTxnCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 738411270 737073932 0 0
T1 844250 844134 0 0
T2 140852 140726 0 0
T3 462488 462162 0 0
T4 51978 49372 0 0
T5 1670770 1670464 0 0
T6 4556 4430 0 0
T10 3312 3196 0 0
T16 879516 879404 0 0
T17 118670 118524 0 0
T25 2412 2308 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 738411270 737073932 0 0
T1 844250 844134 0 0
T2 140852 140726 0 0
T3 462488 462162 0 0
T4 51978 49372 0 0
T5 1670770 1670464 0 0
T6 4556 4430 0 0
T10 3312 3196 0 0
T16 879516 879404 0 0
T17 118670 118524 0 0
T25 2412 2308 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core
Line No.TotalCoveredPercent
TOTAL8989100.00
ALWAYS15166100.00
ALWAYS16433100.00
CONT_ASSIGN19511100.00
CONT_ASSIGN19911100.00
ALWAYS20244100.00
ALWAYS21466100.00
ALWAYS22866100.00
CONT_ASSIGN27611100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28611100.00
CONT_ASSIGN31611100.00
CONT_ASSIGN32011100.00
ALWAYS3242929100.00
CONT_ASSIGN38711100.00
CONT_ASSIGN39111100.00
CONT_ASSIGN39211100.00
CONT_ASSIGN39311100.00
CONT_ASSIGN39411100.00
CONT_ASSIGN39511100.00
CONT_ASSIGN39611100.00
CONT_ASSIGN39711100.00
CONT_ASSIGN41411100.00
CONT_ASSIGN42711100.00
CONT_ASSIGN52111100.00
CONT_ASSIGN54811100.00
CONT_ASSIGN54911100.00
CONT_ASSIGN55011100.00
CONT_ASSIGN55111100.00
CONT_ASSIGN55311100.00
CONT_ASSIGN55411100.00
CONT_ASSIGN55511100.00
CONT_ASSIGN55611100.00
CONT_ASSIGN55711100.00
CONT_ASSIGN55811100.00
CONT_ASSIGN55911100.00
CONT_ASSIGN56611100.00
CONT_ASSIGN58311100.00
CONT_ASSIGN58411100.00
CONT_ASSIGN58511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
151 1 1
152 1 1
153 1 1
154 1 1
155 1 1
156 1 1
MISSING_ELSE
164 3 3
195 1 1
199 1 1
202 1 1
203 1 1
204 1 1
205 1 1
MISSING_ELSE
214 1 1
215 1 1
216 1 1
217 1 1
218 1 1
219 1 1
MISSING_ELSE
228 1 1
229 1 1
230 1 1
231 1 1
232 1 1
233 1 1
MISSING_ELSE
276 1 1
279 1 1
280 1 1
281 1 1
286 1 1
316 1 1
320 1 1
324 1 1
325 1 1
326 1 1
327 1 1
328 1 1
330 1 1
332 1 1
333 1 1
334 1 1
335 1 1
336 1 1
337 1 1
338 1 1
339 1 1
340 1 1
MISSING_ELSE
346 1 1
347 1 1
348 1 1
MISSING_ELSE
355 1 1
356 1 1
357 1 1
358 1 1
MISSING_ELSE
364 1 1
365 1 1
366 1 1
367 1 1
368 1 1
MISSING_ELSE
373 1 1
374 1 1
387 1 1
391 1 1
392 1 1
393 1 1
394 1 1
395 1 1
396 1 1
397 1 1
414 1 1
427 1 1
521 1 1
548 1 1
549 1 1
550 1 1
551 1 1
553 1 1
554 1 1
555 1 1
556 1 1
557 1 1
558 1 1
559 1 1
566 1 1
583 1 1
584 1 1
585 1 1


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core
TotalCoveredPercent
Conditions1068883.02
Logical1068883.02
Non-Logical00
Event00

 LINE       195
 EXPRESSION (host_gnt && (muxed_part != FlashPartData))
             ----1---    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT16,T5,T17
11Not Covered

 LINE       195
 SUB-EXPRESSION (muxed_part != FlashPartData)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       199
 EXPRESSION (((|host_outstanding)) & ((!ctrl_fsm_idle)))
             ----------1----------   ---------2--------
-1--2-StatusTests
01CoveredT1,T6,T10
10CoveredT16,T5,T17
11Not Covered

 LINE       204
 EXPRESSION (host_gnt_err_event | host_outstanding_err_event)
             ---------1--------   -------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered

 LINE       216
 EXPRESSION (host_outstanding == '0)
            ------------1-----------
-1-StatusTests
0CoveredT16,T5,T17
1CoveredT1,T2,T3

 LINE       230
 EXPRESSION ((host_outstanding == '0) && ctrl_fsm_idle)
             ------------1-----------    ------2------
-1--2-StatusTests
01CoveredT16,T5,T17
10CoveredT1,T6,T10
11CoveredT1,T2,T3

 LINE       230
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------
-1-StatusTests
0CoveredT16,T5,T17
1CoveredT1,T2,T3

 LINE       241
 EXPRESSION (host_gnt && ((!host_req_done_o)) && (host_outstanding <= flash_phy_pkg::RspOrderDepth))
             ----1---    ----------2---------    -------------------------3------------------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT16,T5,T17
110Not Covered
111CoveredT16,T5,T17

 LINE       241
 EXPRESSION (((!host_gnt)) && host_req_done_o && ((|host_outstanding)))
             ------1------    -------2-------    ----------3----------
-1--2--3-StatusTests
011CoveredT16,T5,T17
101CoveredT16,T5,T17
110Not Covered
111CoveredT16,T5,T17

 LINE       280
 EXPRESSION (host_req & host_req_rdy_o)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT137
10CoveredT16,T5,T17
11CoveredT16,T5,T17

 LINE       281
 EXPRESSION (((|host_outstanding)) & rd_stage_data_valid)
             ----------1----------   ---------2---------
-1--2-StatusTests
01CoveredT1,T6,T10
10CoveredT16,T5,T17
11CoveredT16,T5,T17

 LINE       316
 EXPRESSION ((phy_req & host_req) ? rd_stage_rdy : rd_stage_idle)
             ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT16,T5,T17

 LINE       316
 SUB-EXPRESSION (phy_req & host_req)
                 ---1---   ----2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T6,T10
11CoveredT16,T5,T17

 LINE       320
 EXPRESSION (req_i & host_gnt)
             --1--   ----2---
-1--2-StatusTests
01CoveredT16,T5,T17
10CoveredT1,T6,T10
11CoveredT16,T5,T17

 LINE       335
 EXPRESSION (ctrl_gnt && rd_i)
             ----1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T10,T16
11CoveredT1,T6,T10

 LINE       337
 EXPRESSION (ctrl_gnt && prog_i)
             ----1---    ---2--
-1--2-StatusTests
01CoveredT1,T2,T16
10CoveredT1,T4,T20
11CoveredT1,T10,T16

 LINE       387
 EXPRESSION ((ctrl_fsm_idle & ctrl_rsp_vld) | ((host_outstanding == '0) & host_req_done_o))
             ---------------1--------------   ----------------------2---------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered

 LINE       387
 SUB-EXPRESSION (ctrl_fsm_idle & ctrl_rsp_vld)
                 ------1------   ------2-----
-1--2-StatusTests
01CoveredT1,T6,T10
10CoveredT1,T2,T3
11Not Covered

 LINE       387
 SUB-EXPRESSION ((host_outstanding == '0) & host_req_done_o)
                 ------------1-----------   -------2-------
-1--2-StatusTests
01CoveredT16,T5,T17
10CoveredT1,T2,T3
11Not Covered

 LINE       387
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       391
 EXPRESSION (host_sel ? host_addr_i : addr_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT16,T5,T17

 LINE       392
 EXPRESSION (host_sel ? FlashPartData : part_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT16,T5,T17

 LINE       393
 EXPRESSION (host_sel ? host_scramble_en_i : scramble_en_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT16,T5,T17

 LINE       394
 EXPRESSION (host_sel ? host_ecc_en_i : ecc_en_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT16,T5,T17

 LINE       395
 EXPRESSION (ctrl_rsp_vld & rd_i)
             ------1-----   --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T10,T16
11CoveredT1,T6,T10

 LINE       396
 EXPRESSION (ctrl_rsp_vld & prog_i)
             ------1-----   ---2--
-1--2-StatusTests
01CoveredT1,T2,T10
10CoveredT1,T6,T10
11CoveredT1,T10,T16

 LINE       397
 EXPRESSION (ctrl_rsp_vld & (pg_erase_i | bk_erase_i))
             ------1-----   ------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T6,T10
11CoveredT1,T4,T20

 LINE       397
 SUB-EXPRESSION (pg_erase_i | bk_erase_i)
                 -----1----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T20,T12
10CoveredT1,T2,T3

 LINE       427
 EXPRESSION ((host_gnt_rd_err & (host_outstanding == 1'b1)) | host_outstanding_rd_err)
             -----------------------1----------------------   -----------2-----------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered

 LINE       427
 SUB-EXPRESSION (host_gnt_rd_err & (host_outstanding == 1'b1))
                 -------1-------   -------------2------------
-1--2-StatusTests
01CoveredT16,T5,T17
10Not Covered
11Not Covered

 LINE       427
 SUB-EXPRESSION (host_outstanding == 1'b1)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT16,T5,T17

 LINE       430
 EXPRESSION (phy_req & (rd_i | host_req))
             ---1---   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T10,T16
11CoveredT1,T6,T10

 LINE       430
 SUB-EXPRESSION (rd_i | host_req)
                 --1-   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT16,T5,T17
10CoveredT1,T2,T3

 LINE       430
 EXPRESSION (arb_host_gnt_err ? ({flash_phy_pkg::FullDataWidth {1'b1}}) : flash_rdata)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       521
 EXPRESSION (fsm_err | prog_fsm_err)
             ---1---   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered

 LINE       548
 EXPRESSION (prog_calc_req | rd_calc_req)
             ------1------   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT6,T17,T14
10CoveredT20,T11,T27

 LINE       549
 EXPRESSION (prog_op_req | rd_op_req)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT6,T14,T15
10CoveredT20,T11,T27

 LINE       550
 EXPRESSION (prog_op_req ? ScrambleOp : DeScrambleOp)
             -----1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT20,T11,T27

 LINE       551
 EXPRESSION (prog_calc_req ? muxed_addr[(flash_phy_pkg::BusBankAddrW - 1):flash_phy_pkg::LsbAddrBit] : rd_calc_addr)
             ------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT20,T11,T27

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core
Summary for FSM :: state_q
TotalCoveredPercent
States 5 5 100.00 (Not included in score)
Transitions 7 7 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
StCtrl 340 Covered T1,T4,T20
StCtrlProg 338 Covered T1,T10,T16
StCtrlRead 336 Covered T1,T6,T10
StDisable 334 Covered T20,T11,T21
StIdle 348 Covered T1,T2,T3


transitionsLine No.CoveredTests
StCtrl->StIdle 368 Covered T1,T4,T20
StCtrlProg->StIdle 358 Covered T1,T10,T16
StCtrlRead->StIdle 348 Covered T1,T6,T10
StIdle->StCtrl 340 Covered T1,T4,T20
StIdle->StCtrlProg 338 Covered T1,T10,T16
StIdle->StCtrlRead 336 Covered T1,T6,T10
StIdle->StDisable 334 Covered T20,T11,T21



Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core
Line No.TotalCoveredPercent
Branches 46 45 97.83
TERNARY 316 2 2 100.00
TERNARY 391 2 2 100.00
TERNARY 392 2 2 100.00
TERNARY 393 2 2 100.00
TERNARY 394 2 2 100.00
TERNARY 550 2 2 100.00
TERNARY 551 2 2 100.00
TERNARY 430 2 1 50.00
IF 151 4 4 100.00
IF 164 2 2 100.00
IF 202 3 3 100.00
IF 214 4 4 100.00
IF 228 4 4 100.00
CASE 330 13 13 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 316 ((phy_req & host_req)) ?

Branches:
-1-StatusTests
1 Covered T16,T5,T17
0 Covered T1,T2,T3


LineNo. Expression -1-: 391 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T16,T5,T17
0 Covered T1,T2,T3


LineNo. Expression -1-: 392 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T16,T5,T17
0 Covered T1,T2,T3


LineNo. Expression -1-: 393 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T16,T5,T17
0 Covered T1,T2,T3


LineNo. Expression -1-: 394 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T16,T5,T17
0 Covered T1,T2,T3


LineNo. Expression -1-: 550 (prog_op_req) ?

Branches:
-1-StatusTests
1 Covered T20,T11,T27
0 Covered T1,T2,T3


LineNo. Expression -1-: 551 (prog_calc_req) ?

Branches:
-1-StatusTests
1 Covered T20,T11,T27
0 Covered T1,T2,T3


LineNo. Expression -1-: 430 (arb_host_gnt_err) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 151 if ((!rst_ni)) -2-: 153 if (ctrl_rsp_vld) -3-: 155 if (inc_arb_cnt)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T6,T10
0 0 1 Covered T16,T5,T17
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 164 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 202 if ((!rst_ni)) -2-: 204 if ((host_gnt_err_event | host_outstanding_err_event))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T18,T22,T23
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 214 if ((!rst_ni)) -2-: 216 if ((host_outstanding == '0)) -3-: 218 if (host_gnt_err_event)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T18,T22,T23
0 0 0 Covered T16,T5,T17


LineNo. Expression -1-: 228 if ((!rst_ni)) -2-: 230 if (((host_outstanding == '0) && ctrl_fsm_idle)) -3-: 232 if (host_outstanding_err_event)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T18,T22,T23
0 0 0 Covered T1,T6,T10


LineNo. Expression -1-: 330 case (state_q) -2-: 333 if (prim_mubi_pkg::mubi4_test_true_loose(flash_disable[FsmDisableIdx])) -3-: 335 if ((ctrl_gnt && rd_i)) -4-: 337 if ((ctrl_gnt && prog_i)) -5-: 339 if (ctrl_gnt) -6-: 346 if (rd_stage_data_valid) -7-: 356 if (prog_ack) -8-: 366 if (erase_ack)

Branches:
-1--2--3--4--5--6--7--8-StatusTests
StIdle 1 - - - - - - Covered T20,T11,T21
StIdle 0 1 - - - - - Covered T1,T6,T10
StIdle 0 0 1 - - - - Covered T1,T10,T16
StIdle 0 0 0 1 - - - Covered T1,T4,T20
StIdle 0 0 0 0 - - - Covered T1,T2,T3
StCtrlRead - - - - 1 - - Covered T1,T6,T10
StCtrlRead - - - - 0 - - Covered T1,T6,T10
StCtrlProg - - - - - 1 - Covered T1,T10,T16
StCtrlProg - - - - - 0 - Covered T1,T10,T16
StCtrl - - - - - - 1 Covered T1,T4,T20
StCtrl - - - - - - 0 Covered T1,T4,T20
StDisable - - - - - - - Covered T20,T11,T21
default - - - - - - - Covered T18,T22,T23


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 8 8 100.00 8 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 8 8 100.00 8 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
ArbCntMax_A 369205635 1820432 0 0
CtrlPrio_A 369205635 1820432 0 0
HostTransIdleChk_A 369205635 20572567 0 0
NoRemainder_A 879 879 0 0
OneHotReqs_A 369205635 368536966 0 0
Pow2Multiple_A 879 879 0 0
RdTxnCheck_A 369205635 368536966 0 0
u_state_regs_A 369205635 368536966 0 0


ArbCntMax_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 369205635 1820432 0 0
T4 25989 0 0 0
T5 835385 61594 0 0
T14 131577 1170 0 0
T15 108103 3317 0 0
T16 439758 4929 0 0
T17 59335 1465 0 0
T25 1206 0 0 0
T42 0 3107 0 0
T44 164173 0 0 0
T60 0 33166 0 0
T82 1229 0 0 0
T83 712 0 0 0
T84 0 1719 0 0
T100 0 2205 0 0
T130 0 1620 0 0

CtrlPrio_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 369205635 1820432 0 0
T4 25989 0 0 0
T5 835385 61594 0 0
T14 131577 1170 0 0
T15 108103 3317 0 0
T16 439758 4929 0 0
T17 59335 1465 0 0
T25 1206 0 0 0
T42 0 3107 0 0
T44 164173 0 0 0
T60 0 33166 0 0
T82 1229 0 0 0
T83 712 0 0 0
T84 0 1719 0 0
T100 0 2205 0 0
T130 0 1620 0 0

HostTransIdleChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 369205635 20572567 0 0
T4 25989 0 0 0
T5 835385 439671 0 0
T14 131577 29373 0 0
T15 108103 30986 0 0
T16 439758 46247 0 0
T17 59335 15510 0 0
T25 1206 0 0 0
T42 0 21640 0 0
T44 164173 0 0 0
T58 0 316 0 0
T82 1229 0 0 0
T83 712 23 0 0
T84 0 16546 0 0
T99 0 19 0 0

NoRemainder_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 879 879 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T10 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T25 1 1 0 0

OneHotReqs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 369205635 368536966 0 0
T1 422125 422067 0 0
T2 70426 70363 0 0
T3 231244 231081 0 0
T4 25989 24686 0 0
T5 835385 835232 0 0
T6 2278 2215 0 0
T10 1656 1598 0 0
T16 439758 439702 0 0
T17 59335 59262 0 0
T25 1206 1154 0 0

Pow2Multiple_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 879 879 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T10 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T25 1 1 0 0

RdTxnCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 369205635 368536966 0 0
T1 422125 422067 0 0
T2 70426 70363 0 0
T3 231244 231081 0 0
T4 25989 24686 0 0
T5 835385 835232 0 0
T6 2278 2215 0 0
T10 1656 1598 0 0
T16 439758 439702 0 0
T17 59335 59262 0 0
T25 1206 1154 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 369205635 368536966 0 0
T1 422125 422067 0 0
T2 70426 70363 0 0
T3 231244 231081 0 0
T4 25989 24686 0 0
T5 835385 835232 0 0
T6 2278 2215 0 0
T10 1656 1598 0 0
T16 439758 439702 0 0
T17 59335 59262 0 0
T25 1206 1154 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core
Line No.TotalCoveredPercent
TOTAL8989100.00
ALWAYS15166100.00
ALWAYS16433100.00
CONT_ASSIGN19511100.00
CONT_ASSIGN19911100.00
ALWAYS20244100.00
ALWAYS21466100.00
ALWAYS22866100.00
CONT_ASSIGN27611100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28611100.00
CONT_ASSIGN31611100.00
CONT_ASSIGN32011100.00
ALWAYS3242929100.00
CONT_ASSIGN38711100.00
CONT_ASSIGN39111100.00
CONT_ASSIGN39211100.00
CONT_ASSIGN39311100.00
CONT_ASSIGN39411100.00
CONT_ASSIGN39511100.00
CONT_ASSIGN39611100.00
CONT_ASSIGN39711100.00
CONT_ASSIGN41411100.00
CONT_ASSIGN42711100.00
CONT_ASSIGN52111100.00
CONT_ASSIGN54811100.00
CONT_ASSIGN54911100.00
CONT_ASSIGN55011100.00
CONT_ASSIGN55111100.00
CONT_ASSIGN55311100.00
CONT_ASSIGN55411100.00
CONT_ASSIGN55511100.00
CONT_ASSIGN55611100.00
CONT_ASSIGN55711100.00
CONT_ASSIGN55811100.00
CONT_ASSIGN55911100.00
CONT_ASSIGN56611100.00
CONT_ASSIGN58311100.00
CONT_ASSIGN58411100.00
CONT_ASSIGN58511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
151 1 1
152 1 1
153 1 1
154 1 1
155 1 1
156 1 1
MISSING_ELSE
164 3 3
195 1 1
199 1 1
202 1 1
203 1 1
204 1 1
205 1 1
MISSING_ELSE
214 1 1
215 1 1
216 1 1
217 1 1
218 1 1
219 1 1
MISSING_ELSE
228 1 1
229 1 1
230 1 1
231 1 1
232 1 1
233 1 1
MISSING_ELSE
276 1 1
279 1 1
280 1 1
281 1 1
286 1 1
316 1 1
320 1 1
324 1 1
325 1 1
326 1 1
327 1 1
328 1 1
330 1 1
332 1 1
333 1 1
334 1 1
335 1 1
336 1 1
337 1 1
338 1 1
339 1 1
340 1 1
MISSING_ELSE
346 1 1
347 1 1
348 1 1
MISSING_ELSE
355 1 1
356 1 1
357 1 1
358 1 1
MISSING_ELSE
364 1 1
365 1 1
366 1 1
367 1 1
368 1 1
MISSING_ELSE
373 1 1
374 1 1
387 1 1
391 1 1
392 1 1
393 1 1
394 1 1
395 1 1
396 1 1
397 1 1
414 1 1
427 1 1
521 1 1
548 1 1
549 1 1
550 1 1
551 1 1
553 1 1
554 1 1
555 1 1
556 1 1
557 1 1
558 1 1
559 1 1
566 1 1
583 1 1
584 1 1
585 1 1


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core
TotalCoveredPercent
Conditions1069589.62
Logical1069589.62
Non-Logical00
Event00

 LINE       195
 EXPRESSION (host_gnt && (muxed_part != FlashPartData))
             ----1---    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T16,T4
11CoveredT18,T171,T22

 LINE       195
 SUB-EXPRESSION (muxed_part != FlashPartData)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       199
 EXPRESSION (((|host_outstanding)) & ((!ctrl_fsm_idle)))
             ----------1----------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T16,T4
11Not Covered

 LINE       204
 EXPRESSION (host_gnt_err_event | host_outstanding_err_event)
             ---------1--------   -------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT18,T171,T22

 LINE       216
 EXPRESSION (host_outstanding == '0)
            ------------1-----------
-1-StatusTests
0CoveredT2,T16,T4
1CoveredT1,T2,T3

 LINE       230
 EXPRESSION ((host_outstanding == '0) && ctrl_fsm_idle)
             ------------1-----------    ------2------
-1--2-StatusTests
01CoveredT2,T16,T4
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       230
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------
-1-StatusTests
0CoveredT2,T16,T4
1CoveredT1,T2,T3

 LINE       241
 EXPRESSION (host_gnt && ((!host_req_done_o)) && (host_outstanding <= flash_phy_pkg::RspOrderDepth))
             ----1---    ----------2---------    -------------------------3------------------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT2,T16,T4
110Not Covered
111CoveredT2,T16,T4

 LINE       241
 EXPRESSION (((!host_gnt)) && host_req_done_o && ((|host_outstanding)))
             ------1------    -------2-------    ----------3----------
-1--2--3-StatusTests
011CoveredT2,T16,T4
101CoveredT2,T16,T4
110CoveredT98
111CoveredT2,T16,T4

 LINE       280
 EXPRESSION (host_req & host_req_rdy_o)
             ----1---   -------2------
-1--2-StatusTests
01Not Covered
10CoveredT16,T5,T17
11CoveredT2,T16,T4

 LINE       281
 EXPRESSION (((|host_outstanding)) & rd_stage_data_valid)
             ----------1----------   ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T16,T4
11CoveredT2,T16,T4

 LINE       316
 EXPRESSION ((phy_req & host_req) ? rd_stage_rdy : rd_stage_idle)
             ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T16,T4

 LINE       316
 SUB-EXPRESSION (phy_req & host_req)
                 ---1---   ----2---
-1--2-StatusTests
01CoveredT135,T136,T197
10CoveredT1,T2,T3
11CoveredT2,T16,T4

 LINE       320
 EXPRESSION (req_i & host_gnt)
             --1--   ----2---
-1--2-StatusTests
01CoveredT2,T16,T4
10CoveredT1,T2,T3
11CoveredT16,T5,T17

 LINE       335
 EXPRESSION (ctrl_gnt && rd_i)
             ----1---    --2-
-1--2-StatusTests
01CoveredT1,T6,T10
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       337
 EXPRESSION (ctrl_gnt && prog_i)
             ----1---    ---2--
-1--2-StatusTests
01CoveredT1,T10,T16
10CoveredT1,T2,T3
11CoveredT1,T2,T16

 LINE       387
 EXPRESSION ((ctrl_fsm_idle & ctrl_rsp_vld) | ((host_outstanding == '0) & host_req_done_o))
             ---------------1--------------   ----------------------2---------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT98
10CoveredT198,T199,T38

 LINE       387
 SUB-EXPRESSION (ctrl_fsm_idle & ctrl_rsp_vld)
                 ------1------   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT198,T199,T38

 LINE       387
 SUB-EXPRESSION ((host_outstanding == '0) & host_req_done_o)
                 ------------1-----------   -------2-------
-1--2-StatusTests
01CoveredT2,T16,T4
10CoveredT1,T2,T3
11CoveredT98

 LINE       387
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       391
 EXPRESSION (host_sel ? host_addr_i : addr_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T16,T4

 LINE       392
 EXPRESSION (host_sel ? FlashPartData : part_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T16,T4

 LINE       393
 EXPRESSION (host_sel ? host_scramble_en_i : scramble_en_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T16,T4

 LINE       394
 EXPRESSION (host_sel ? host_ecc_en_i : ecc_en_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T16,T4

 LINE       395
 EXPRESSION (ctrl_rsp_vld & rd_i)
             ------1-----   --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       396
 EXPRESSION (ctrl_rsp_vld & prog_i)
             ------1-----   ---2--
-1--2-StatusTests
01CoveredT1,T2,T10
10CoveredT1,T2,T3
11CoveredT1,T2,T16

 LINE       397
 EXPRESSION (ctrl_rsp_vld & (pg_erase_i | bk_erase_i))
             ------1-----   ------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       397
 SUB-EXPRESSION (pg_erase_i | bk_erase_i)
                 -----1----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T20,T12
10CoveredT1,T2,T3

 LINE       427
 EXPRESSION ((host_gnt_rd_err & (host_outstanding == 1'b1)) | host_outstanding_rd_err)
             -----------------------1----------------------   -----------2-----------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered

 LINE       427
 SUB-EXPRESSION (host_gnt_rd_err & (host_outstanding == 1'b1))
                 -------1-------   -------------2------------
-1--2-StatusTests
01CoveredT2,T16,T4
10Not Covered
11Not Covered

 LINE       427
 SUB-EXPRESSION (host_outstanding == 1'b1)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T16,T4

 LINE       430
 EXPRESSION (phy_req & (rd_i | host_req))
             ---1---   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       430
 SUB-EXPRESSION (rd_i | host_req)
                 --1-   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T16,T4
10CoveredT1,T2,T3

 LINE       430
 EXPRESSION (arb_host_gnt_err ? ({flash_phy_pkg::FullDataWidth {1'b1}}) : flash_rdata)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       521
 EXPRESSION (fsm_err | prog_fsm_err)
             ---1---   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered

 LINE       548
 EXPRESSION (prog_calc_req | rd_calc_req)
             ------1------   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT16,T83,T20

 LINE       549
 EXPRESSION (prog_op_req | rd_op_req)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT16,T83,T20

 LINE       550
 EXPRESSION (prog_op_req ? ScrambleOp : DeScrambleOp)
             -----1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT16,T83,T20

 LINE       551
 EXPRESSION (prog_calc_req ? muxed_addr[(flash_phy_pkg::BusBankAddrW - 1):flash_phy_pkg::LsbAddrBit] : rd_calc_addr)
             ------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT16,T83,T20

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core
Summary for FSM :: state_q
TotalCoveredPercent
States 5 5 100.00 (Not included in score)
Transitions 7 7 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
StCtrl 340 Covered T1,T2,T3
StCtrlProg 338 Covered T1,T2,T16
StCtrlRead 336 Covered T1,T2,T3
StDisable 334 Covered T20,T11,T21
StIdle 348 Covered T1,T2,T3


transitionsLine No.CoveredTests
StCtrl->StIdle 368 Covered T1,T2,T3
StCtrlProg->StIdle 358 Covered T1,T2,T16
StCtrlRead->StIdle 348 Covered T1,T2,T3
StIdle->StCtrl 340 Covered T1,T2,T3
StIdle->StCtrlProg 338 Covered T1,T2,T16
StIdle->StCtrlRead 336 Covered T1,T2,T3
StIdle->StDisable 334 Covered T20,T11,T21



Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core
Line No.TotalCoveredPercent
Branches 46 45 97.83
TERNARY 316 2 2 100.00
TERNARY 391 2 2 100.00
TERNARY 392 2 2 100.00
TERNARY 393 2 2 100.00
TERNARY 394 2 2 100.00
TERNARY 550 2 2 100.00
TERNARY 551 2 2 100.00
TERNARY 430 2 1 50.00
IF 151 4 4 100.00
IF 164 2 2 100.00
IF 202 3 3 100.00
IF 214 4 4 100.00
IF 228 4 4 100.00
CASE 330 13 13 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 316 ((phy_req & host_req)) ?

Branches:
-1-StatusTests
1 Covered T2,T16,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 391 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T2,T16,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 392 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T2,T16,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 393 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T2,T16,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 394 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T2,T16,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 550 (prog_op_req) ?

Branches:
-1-StatusTests
1 Covered T16,T83,T20
0 Covered T1,T2,T3


LineNo. Expression -1-: 551 (prog_calc_req) ?

Branches:
-1-StatusTests
1 Covered T16,T83,T20
0 Covered T1,T2,T3


LineNo. Expression -1-: 430 (arb_host_gnt_err) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 151 if ((!rst_ni)) -2-: 153 if (ctrl_rsp_vld) -3-: 155 if (inc_arb_cnt)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T16,T5,T17
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 164 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 202 if ((!rst_ni)) -2-: 204 if ((host_gnt_err_event | host_outstanding_err_event))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T18,T171,T22
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 214 if ((!rst_ni)) -2-: 216 if ((host_outstanding == '0)) -3-: 218 if (host_gnt_err_event)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T18,T22,T23
0 0 0 Covered T2,T16,T4


LineNo. Expression -1-: 228 if ((!rst_ni)) -2-: 230 if (((host_outstanding == '0) && ctrl_fsm_idle)) -3-: 232 if (host_outstanding_err_event)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T18,T22,T23
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 330 case (state_q) -2-: 333 if (prim_mubi_pkg::mubi4_test_true_loose(flash_disable[FsmDisableIdx])) -3-: 335 if ((ctrl_gnt && rd_i)) -4-: 337 if ((ctrl_gnt && prog_i)) -5-: 339 if (ctrl_gnt) -6-: 346 if (rd_stage_data_valid) -7-: 356 if (prog_ack) -8-: 366 if (erase_ack)

Branches:
-1--2--3--4--5--6--7--8-StatusTests
StIdle 1 - - - - - - Covered T20,T11,T21
StIdle 0 1 - - - - - Covered T1,T2,T3
StIdle 0 0 1 - - - - Covered T1,T2,T16
StIdle 0 0 0 1 - - - Covered T1,T2,T3
StIdle 0 0 0 0 - - - Covered T1,T2,T3
StCtrlRead - - - - 1 - - Covered T1,T2,T3
StCtrlRead - - - - 0 - - Covered T1,T2,T3
StCtrlProg - - - - - 1 - Covered T1,T2,T16
StCtrlProg - - - - - 0 - Covered T1,T2,T16
StCtrl - - - - - - 1 Covered T1,T2,T3
StCtrl - - - - - - 0 Covered T1,T2,T3
StDisable - - - - - - - Covered T20,T11,T21
default - - - - - - - Covered T18,T22,T23


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 8 8 100.00 8 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 8 8 100.00 8 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
ArbCntMax_A 369205635 2000448 0 0
CtrlPrio_A 369205635 2000448 0 0
HostTransIdleChk_A 369205635 20395831 0 0
NoRemainder_A 879 879 0 0
OneHotReqs_A 369205635 368536966 0 0
Pow2Multiple_A 879 879 0 0
RdTxnCheck_A 369205635 368536966 0 0
u_state_regs_A 369205635 368536966 0 0


ArbCntMax_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 369205635 2000448 0 0
T4 25989 0 0 0
T5 835385 31312 0 0
T14 131577 4770 0 0
T15 108103 2175 0 0
T16 439758 9319 0 0
T17 59335 867 0 0
T25 1206 0 0 0
T42 0 890 0 0
T44 164173 0 0 0
T60 0 32960 0 0
T82 1229 0 0 0
T83 712 0 0 0
T84 0 1323 0 0
T100 0 1286 0 0
T130 0 1076 0 0

CtrlPrio_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 369205635 2000448 0 0
T4 25989 0 0 0
T5 835385 31312 0 0
T14 131577 4770 0 0
T15 108103 2175 0 0
T16 439758 9319 0 0
T17 59335 867 0 0
T25 1206 0 0 0
T42 0 890 0 0
T44 164173 0 0 0
T60 0 32960 0 0
T82 1229 0 0 0
T83 712 0 0 0
T84 0 1323 0 0
T100 0 1286 0 0
T130 0 1076 0 0

HostTransIdleChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 369205635 20395831 0 0
T2 70426 162 0 0
T3 231244 0 0 0
T4 25989 45 0 0
T5 835385 397341 0 0
T6 2278 0 0 0
T10 1656 0 0 0
T14 0 27492 0 0
T15 0 26547 0 0
T16 439758 84023 0 0
T17 59335 18036 0 0
T25 1206 0 0 0
T42 0 16808 0 0
T44 164173 0 0 0
T58 0 174 0 0
T84 0 16099 0 0

NoRemainder_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 879 879 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T10 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T25 1 1 0 0

OneHotReqs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 369205635 368536966 0 0
T1 422125 422067 0 0
T2 70426 70363 0 0
T3 231244 231081 0 0
T4 25989 24686 0 0
T5 835385 835232 0 0
T6 2278 2215 0 0
T10 1656 1598 0 0
T16 439758 439702 0 0
T17 59335 59262 0 0
T25 1206 1154 0 0

Pow2Multiple_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 879 879 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T10 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T25 1 1 0 0

RdTxnCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 369205635 368536966 0 0
T1 422125 422067 0 0
T2 70426 70363 0 0
T3 231244 231081 0 0
T4 25989 24686 0 0
T5 835385 835232 0 0
T6 2278 2215 0 0
T10 1656 1598 0 0
T16 439758 439702 0 0
T17 59335 59262 0 0
T25 1206 1154 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 369205635 368536966 0 0
T1 422125 422067 0 0
T2 70426 70363 0 0
T3 231244 231081 0 0
T4 25989 24686 0 0
T5 835385 835232 0 0
T6 2278 2215 0 0
T10 1656 1598 0 0
T16 439758 439702 0 0
T17 59335 59262 0 0
T25 1206 1154 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%