Module Definition
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Module : flash_phy
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.56 97.67 86.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_eflash 94.56 97.67 86.00 100.00


Module Instance : tb.dut.u_eflash

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.56 97.67 86.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.30 98.50 92.57 93.72 96.43 99.07 97.49


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
85.05 97.12 88.00 98.44 100.00 41.67 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flash_cores[0].u_core 97.26 97.92 92.71 96.12 100.00 98.86 97.94
gen_flash_cores[0].u_host_rsp_fifo 88.08 100.00 78.72 70.00 91.67 100.00
gen_flash_cores[1].u_core 96.61 97.92 91.93 93.02 100.00 98.86 97.94
gen_flash_cores[1].u_host_rsp_fifo 87.23 100.00 74.47 70.00 91.67 100.00
u_bank_sequence_fifo 96.53 100.00 86.11 100.00 100.00
u_disable_buf 100.00 100.00 100.00
u_flash 95.48 98.80 94.49 89.59 90.62 99.37 100.00
u_lc_nvm_debug_en_sync 100.00 100.00 100.00 100.00
u_region_sel 100.00 100.00 100.00 100.00
u_scramble 97.55 100.00 93.80 100.00 100.00 93.94

Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : flash_phy
Line No.TotalCoveredPercent
TOTAL434297.67
CONT_ASSIGN12011100.00
CONT_ASSIGN12111100.00
CONT_ASSIGN12411100.00
CONT_ASSIGN12711100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12911100.00
CONT_ASSIGN13200
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13511100.00
CONT_ASSIGN13611100.00
CONT_ASSIGN13711100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14111100.00
CONT_ASSIGN14211100.00
CONT_ASSIGN14311100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN17711100.00
CONT_ASSIGN17711100.00
CONT_ASSIGN17711100.00
CONT_ASSIGN17711100.00
CONT_ASSIGN17711100.00
CONT_ASSIGN17711100.00
CONT_ASSIGN17711100.00
CONT_ASSIGN17711100.00
CONT_ASSIGN17711100.00
CONT_ASSIGN19211100.00
CONT_ASSIGN19811100.00
CONT_ASSIGN20011100.00
CONT_ASSIGN21011100.00
CONT_ASSIGN21111100.00
CONT_ASSIGN22911100.00
CONT_ASSIGN22911100.00
CONT_ASSIGN25311100.00
CONT_ASSIGN25311100.00
CONT_ASSIGN25411100.00
CONT_ASSIGN25411100.00
CONT_ASSIGN33100
CONT_ASSIGN34711100.00
CONT_ASSIGN38711100.00
CONT_ASSIGN390100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
120 1 1
121 1 1
124 1 1
127 1 1
128 1 1
129 1 1
132 unreachable
133 1 1
134 1 1
135 1 1
136 1 1
137 1 1
138 1 1
139 1 1
140 1 1
141 1 1
142 1 1
143 1 1
144 1 1
145 1 1
146 1 1
177 9 9
192 1 1
198 1 1
200 1 1
210 1 1
211 1 1
229 2 2
253 2 2
254 2 2
331 unreachable
347 1 1
387 1 1
390 0 1

Cond Coverage for Module : flash_phy
TotalCoveredPercent
Conditions504386.00
Logical504386.00
Non-Logical00
Event00

 LINE       120
 EXPRESSION (host_req_i ? host_addr_i[(flash_ctrl_pkg::BusAddrW - 1)-:flash_ctrl_pkg::BankW] : '0)
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T16,T4 

 LINE       124
 EXPRESSION (host_req_rdy[host_bank_sel] & host_rsp_avail[host_bank_sel] & seq_fifo_rdy)
             -------------1-------------   --------------2--------------   ------3-----
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT2,T16,T4 

 LINE       127
 EXPRESSION (seq_fifo_pending & host_rsp_vld[rsp_bank_sel])
             --------1-------   -------------2------------
-1--2-StatusTests
01CoveredT98
10CoveredT2,T16,T4
11CoveredT2,T16,T4 

 LINE       144
 EXPRESSION (((|arb_err)) | scramble_arb_err)
             ------1-----   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT134
10CoveredT135,T136,T137 

 LINE       154
 EXPRESSION (host_req_i & host_req_rdy_o)
             -----1----   -------2------
-1--2-StatusTests
01Not Covered
10CoveredT16,T5,T17
11CoveredT2,T16,T4 

 LINE       229
 EXPRESSION (host_req_done_o & (rsp_bank_sel == 0))
             -------1-------   ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT16,T5,T17
11CoveredT2,T16,T4 

 LINE       229
 SUB-EXPRESSION (rsp_bank_sel == 0)
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       229
 EXPRESSION (host_req_done_o & (rsp_bank_sel == 1))
             -------1-------   ---------2---------
-1--2-StatusTests
01CoveredT16,T5,T17
10CoveredT2,T16,T4
11CoveredT16,T5,T17 

 LINE       229
 SUB-EXPRESSION (rsp_bank_sel == 1)
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT16,T5,T17 

 LINE       253
 EXPRESSION (host_req_i & (host_bank_sel == 0) & host_rsp_avail[0])
             -----1----   ----------2---------   --------3--------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT16,T5,T17
110CoveredT16,T14,T15
111CoveredT2,T16,T4 

 LINE       253
 SUB-EXPRESSION (host_bank_sel == 0)
                ----------1---------
-1-StatusTests
0CoveredT2,T6,T10
1CoveredT1,T2,T3 

 LINE       253
 EXPRESSION (host_req_i & (host_bank_sel == 1) & host_rsp_avail[1])
             -----1----   ----------2---------   --------3--------
-1--2--3-StatusTests
011Not Covered
101CoveredT2,T16,T4
110CoveredT16,T102,T29
111CoveredT16,T5,T17 

 LINE       253
 SUB-EXPRESSION (host_bank_sel == 1)
                ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT16,T5,T17 

 LINE       254
 EXPRESSION (flash_ctrl_i.req & (ctrl_bank_sel == 0))
             --------1-------   ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T6,T10
11CoveredT1,T2,T3 

 LINE       254
 SUB-EXPRESSION (ctrl_bank_sel == 0)
                ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       254
 EXPRESSION (flash_ctrl_i.req & (ctrl_bank_sel == 1))
             --------1-------   ----------2---------
-1--2-StatusTests
01CoveredT1,T6,T10
10CoveredT1,T2,T3
11CoveredT1,T6,T10 

 LINE       254
 SUB-EXPRESSION (ctrl_bank_sel == 1)
                ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T6,T10 

 LINE       387
 EXPRESSION (flash_ctrl_i.alert_trig & flash_ctrl_i.alert_ack)
             -----------1-----------   -----------2----------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered
Branch Coverage for Module : flash_phy
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 120 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	120	(host_req_i) ?

Branches:
-1-StatusTests
1 Covered T2,T16,T4
0 Covered T1,T2,T3

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