Assertions
dashboard | hierarchy | modlist | groups | tests | asserts
Assertions by Category
ASSERTPROPERTIESSEQUENCES
Total992010
Category 0992010

Assertions by Severity
ASSERTPROPERTIESSEQUENCES
Total992010
Severity 0992010

Summary for Assertions
NUMBERPERCENT
Total Number992100.00
Uncovered505.04
Success94294.96
Failure00.00
Incomplete151.51
Without Attempts00.00

Summary for Cover Sequences
NUMBERPERCENT
Total Number10100.00
Uncovered330.00
All Matches770.00
First Matches770.00
Go previous page
ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETE
tb.dut.u_tl_adapter_eflash.u_err.dataWidthOnly32_A 0087387300
tb.dut.u_tl_adapter_eflash.u_reqfifo.DataKnown_A 003625008153134046600
tb.dut.u_tl_adapter_eflash.u_reqfifo.DepthKnown_A 0036250081536174423100
tb.dut.u_tl_adapter_eflash.u_reqfifo.RvalidKnown_A 0036250081536174423100
tb.dut.u_tl_adapter_eflash.u_reqfifo.WreadyKnown_A 0036250081536174423100
tb.dut.u_tl_adapter_eflash.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth 003625008153134046600
tb.dut.u_tl_adapter_eflash.u_rsp_gen.DataWidthCheck_A 0087387300
tb.dut.u_tl_adapter_eflash.u_rsp_gen.PayLoadWidthCheck 0087387300
tb.dut.u_tl_adapter_eflash.u_rspfifo.DataKnown_A 00362500815455118100
tb.dut.u_tl_adapter_eflash.u_rspfifo.DepthKnown_A 0036250081536174423100
tb.dut.u_tl_adapter_eflash.u_rspfifo.RvalidKnown_A 0036250081536174423100
tb.dut.u_tl_adapter_eflash.u_rspfifo.WreadyKnown_A 0036250081536174423100
tb.dut.u_tl_adapter_eflash.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth 00362500815455118100
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.DataKnown_A 003625008153022246600
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.DepthKnown_A 0036250081536174423100
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.RvalidKnown_A 0036250081536174423100
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.WreadyKnown_A 0036250081536174423100
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth 003625008153022246600
tb.dut.u_tl_gate.u_err_en_sync.NumCopiesMustBeGreaterZero_A 0087387300
tb.dut.u_tl_gate.u_err_en_sync.OutputsKnown_A 0035577690335502031900
tb.dut.u_tl_gate.u_err_en_sync.gen_no_flops.OutputDelay_A 0035577690335502031900
tb.dut.u_tl_gate.u_state_regs.AssertConnected_A 0087387300
tb.dut.u_tl_gate.u_state_regs_A 0036250081536174423100
tb.dut.u_tl_gate.u_tlul_err_resp.u_intg_gen.DataWidthCheck_A 0087387300
tb.dut.u_tl_gate.u_tlul_err_resp.u_intg_gen.PayLoadWidthCheck 0087387300
tb.dut.u_to_prog_fifo.AddrOutKnown_A 0036250081536174423100
tb.dut.u_to_prog_fifo.DataIntgOptions_A 0087387300
tb.dut.u_to_prog_fifo.ReqOutKnown_A 0036250081536174423100
tb.dut.u_to_prog_fifo.SramDwHasByteGranularity_A 0087387300
tb.dut.u_to_prog_fifo.SramDwIsMultipleOfTlulWidth_A 0087387300
tb.dut.u_to_prog_fifo.TlOutKnownIfFifoKnown_A 0036250081536174423100
tb.dut.u_to_prog_fifo.TlOutValidKnown_A 0036250081536174423100
tb.dut.u_to_prog_fifo.WdataOutKnown_A 0036250081536174423100
tb.dut.u_to_prog_fifo.WeOutKnown_A 0036250081536174423100
tb.dut.u_to_prog_fifo.WmaskOutKnown_A 0036250081536174423100
tb.dut.u_to_prog_fifo.adapterNoReadOrWrite 0087387300
tb.dut.u_to_prog_fifo.u_err.dataWidthOnly32_A 0087387300
tb.dut.u_to_prog_fifo.u_reqfifo.DataKnown_A 00362500815268616500
tb.dut.u_to_prog_fifo.u_reqfifo.DepthKnown_A 0036250081536174423100
tb.dut.u_to_prog_fifo.u_reqfifo.RvalidKnown_A 0036250081536174423100
tb.dut.u_to_prog_fifo.u_reqfifo.WreadyKnown_A 0036250081536174423100
tb.dut.u_to_prog_fifo.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth 00362500815268616500
tb.dut.u_to_prog_fifo.u_rsp_gen.DataWidthCheck_A 0087387300
tb.dut.u_to_prog_fifo.u_rsp_gen.PayLoadWidthCheck 0087387300
tb.dut.u_to_prog_fifo.u_rspfifo.DepthKnown_A 0036250081536174423100
tb.dut.u_to_prog_fifo.u_rspfifo.RvalidKnown_A 0036250081536174423100
tb.dut.u_to_prog_fifo.u_rspfifo.WreadyKnown_A 0036250081536174423100
tb.dut.u_to_prog_fifo.u_sramreqfifo.DepthKnown_A 0036250081536174423100
tb.dut.u_to_prog_fifo.u_sramreqfifo.RvalidKnown_A 0036250081536174423100
tb.dut.u_to_prog_fifo.u_sramreqfifo.WreadyKnown_A 0036250081536174423100
tb.dut.u_to_rd_fifo.AddrOutKnown_A 0036250081536174423100
tb.dut.u_to_rd_fifo.DataIntgOptions_A 0087387300
tb.dut.u_to_rd_fifo.ReqOutKnown_A 0036250081536174423100
tb.dut.u_to_rd_fifo.SramDwHasByteGranularity_A 0087387300
tb.dut.u_to_rd_fifo.SramDwIsMultipleOfTlulWidth_A 0087387300
tb.dut.u_to_rd_fifo.TlOutKnownIfFifoKnown_A 0036250081536174423100
tb.dut.u_to_rd_fifo.TlOutValidKnown_A 0036250081536174423100
tb.dut.u_to_rd_fifo.WdataOutKnown_A 0036250081536174423100
tb.dut.u_to_rd_fifo.WeOutKnown_A 0036250081536174423100
tb.dut.u_to_rd_fifo.WmaskOutKnown_A 0036250081536174423100
tb.dut.u_to_rd_fifo.adapterNoReadOrWrite 0087387300
tb.dut.u_to_rd_fifo.rvalidHighReqFifoEmpty 00362500815327133200
tb.dut.u_to_rd_fifo.rvalidHighWhenRspFifoFull 00362500815327133200
tb.dut.u_to_rd_fifo.u_err.dataWidthOnly32_A 0087387300
tb.dut.u_to_rd_fifo.u_reqfifo.DataKnown_A 00362500815434908000
tb.dut.u_to_rd_fifo.u_reqfifo.DepthKnown_A 0036250081536174423100
tb.dut.u_to_rd_fifo.u_reqfifo.RvalidKnown_A 0036250081536174423100
tb.dut.u_to_rd_fifo.u_reqfifo.WreadyKnown_A 0036250081536174423100
tb.dut.u_to_rd_fifo.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth 00362500815434908000
tb.dut.u_to_rd_fifo.u_rsp_gen.DataWidthCheck_A 0087387300
tb.dut.u_to_rd_fifo.u_rsp_gen.PayLoadWidthCheck 0087387300
tb.dut.u_to_rd_fifo.u_rspfifo.DataKnown_A 00362500815434908000
tb.dut.u_to_rd_fifo.u_rspfifo.DepthKnown_A 0036250081536174423100
tb.dut.u_to_rd_fifo.u_rspfifo.RvalidKnown_A 0036250081536174423100
tb.dut.u_to_rd_fifo.u_rspfifo.WreadyKnown_A 0036250081536174423100
tb.dut.u_to_rd_fifo.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth 00362500815434908000
tb.dut.u_to_rd_fifo.u_sramreqfifo.DataKnown_A 00362500815327133200
tb.dut.u_to_rd_fifo.u_sramreqfifo.DepthKnown_A 0036250081536174423100
tb.dut.u_to_rd_fifo.u_sramreqfifo.RvalidKnown_A 0036250081536174423100
tb.dut.u_to_rd_fifo.u_sramreqfifo.WreadyKnown_A 0036250081536174423100
tb.dut.u_to_rd_fifo.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth 00362500815327133200

Assertions Incomplete:
ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETESRC
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.RoundRobin_A 0036250081582850868
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.RoundRobin_A 0036250081543650868
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_flops.OutputDelay_A 0035577690335499062202214
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.RoundRobin_A 00362500815390868
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.RoundRobin_A 0036250081500868
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.RoundRobin_A 0036250081500868
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.RoundRobin_A 0036250081500868
tb.dut.u_flash_hw_if.DisableChk_A 003490104246512719028
tb.dut.u_flash_hw_if.u_sync_rma_req.gen_flops.OutputDelay_A 0035577693735499064102214
tb.dut.u_lc_escalation_en_sync.gen_flops.OutputDelay_A 0035576430335497809702124
tb.dut.u_lc_seed_hw_rd_en_sync.gen_flops.OutputDelay_A 0035577693735499064102214
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_flops.OutputDelay_A 0035577693735499064102214
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_flops.OutputDelay_A 0035577693735499064102214
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_flops.OutputDelay_A 0035577693735499064102214
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_flops.OutputDelay_A 0035577693735499064102214

Detail Report for Cover Sequences

Cover Sequences Uncovered:
COVER SEQUENCESCATEGORYSEVERITYATTEMPTSALL MATCHESFIRST MATCHESINCOMPLETESRC
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C 00365105420000
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C 00365105420000
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C 00365105420000

Cover Sequences All Matches:
COVER SEQUENCESCATEGORYSEVERITYATTEMPTSALL MATCHESFIRST MATCHESINCOMPLETESRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C 0036510542058578585780
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C 0036510542018180
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C 00365105420990
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C 0036510542011110
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C 0036510542010631106310
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C 0036510542096878968780
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C 0036510542020850948208509481063

Cover Sequences First Matches:
COVER SEQUENCESCATEGORYSEVERITYATTEMPTSALL MATCHESFIRST MATCHESINCOMPLETESRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C 0036510542058578585780
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C 0036510542018180
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C 00365105420990
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C 0036510542011110
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C 0036510542010631106310
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C 0036510542096878968780
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C 0036510542020850948208509481063