Unified Coverage Report :: Module :: tlul_adapter_sram

Module : tlul_adapter_sram

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.54	98.07	75.55			96.55	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_to_prog_fifo	83.89	100.00	65.22			85.71	84.62
tb.dut.u_to_rd_fifo	87.52	94.20	73.11			82.76	100.00
tb.dut.u_tl_adapter_eflash	96.22	100.00	88.33			96.55	100.00

---

Module Instance : tb.dut.u_to_prog_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.89	100.00	65.22			85.71	84.62

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.55	89.52	65.48			82.56	80.65

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
84.89	97.12	87.20	98.44		100.00	41.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_err	87.32	100.00	74.29			75.00	100.00
u_reqfifo	92.36	100.00	75.00			94.44	100.00
u_rsp_gen	91.67	83.33					100.00
u_rspfifo	69.33	91.43	57.14			68.75	60.00
u_sram_byte	100.00	100.00
u_sramreqfifo	72.63	94.44	54.84			81.25	60.00
u_tlul_data_integ_enc_data	0.00	0.00
u_tlul_data_integ_enc_instr	0.00	0.00

---

Module Instance : tb.dut.u_to_rd_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.52	94.20	73.11			82.76	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.39	85.59	72.53	70.00		78.82	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
84.89	97.12	87.20	98.44		100.00	41.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_err	66.91	76.92	65.71			25.00	100.00
u_reqfifo	88.33	95.00	75.00			83.33	100.00
u_rsp_gen	91.67	83.33					100.00
u_rspfifo	87.23	100.00	74.47	70.00		91.67	100.00
u_sram_byte	100.00	100.00
u_sramreqfifo	87.64	95.00	72.22			83.33	100.00
u_tlul_data_integ_enc_data	0.00	0.00
u_tlul_data_integ_enc_instr	0.00	0.00

---

Module Instance : tb.dut.u_tl_adapter_eflash

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.22	100.00	88.33			96.55	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.16	91.63	85.61	100.00		93.55	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
84.89	97.12	87.20	98.44		100.00	41.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_cmd_intg_check.u_cmd_intg_chk	100.00	100.00		100.00			100.00
u_err	74.35	88.46	71.43			37.50	100.00
u_reqfifo	96.53	100.00	86.11			100.00	100.00
u_rsp_gen	100.00	100.00					100.00
u_rspfifo	97.16	100.00	88.64			100.00	100.00
u_sram_byte	100.00	100.00
u_sramreqfifo	96.53	100.00	86.11			100.00	100.00
u_tlul_data_integ_enc_data	0.00	0.00
u_tlul_data_integ_enc_instr	0.00	0.00

Line Coverage for Module : tlul_adapter_sram ( parameter SramAw=1,SramDw=32,Outstanding=1,ByteAccess=0,ErrOnWrite=0,ErrOnRead=1,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=0,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Line Coverage for Module self-instances :

SCORE	LINE
83.89	100.00

tb.dut.u_to_prog_fifo

	Line No.	Total	Covered	Percent
TOTAL		65	65	100.00
ALWAYS	94	3	3	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	115	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	152	1	1	100.00
CONT_ASSIGN	224	1	1	100.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	226	1	1	100.00
ALWAYS	231	8	8	100.00
ALWAYS	251	6	6	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
CONT_ASSIGN	288	1	1	100.00
CONT_ASSIGN	293	1	1	100.00
CONT_ASSIGN	299	1	1	100.00
CONT_ASSIGN	311	1	1	100.00
ALWAYS	314	3	3	100.00
CONT_ASSIGN	321	1	1	100.00
CONT_ASSIGN	341	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	343	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
ALWAYS	374	6	6	100.00
ALWAYS	386	5	5	100.00
CONT_ASSIGN	397	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	407	1	1	100.00
CONT_ASSIGN	408	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	425	1	1	100.00
CONT_ASSIGN	426	0	0
CONT_ASSIGN	428	0	0
CONT_ASSIGN	435	0	0
ALWAYS	441	3	3	100.00
CONT_ASSIGN	462	1	1	100.00
CONT_ASSIGN	467	1	1	100.00
CONT_ASSIGN	472	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
94	1	1
95	1	1
96	1	1
97		unreachable
			MISSING_ELSE
103	1	1
108	1	1
115	1	1
126	1	1
140	1	1
152	1	1
224	1	1
225	1	1
226	1	1
231	1	1
233	1	1
234	1	1
236	1	1
237	1	1
238	1	1
241	1	1
244	1	1
251	1	1
253	1	1
254	1	1
255	1	1
257	1	1
260	1	1
265	1	1
269	1	1
288	1	1
293	1	1
299	1	1
311	1	1
314	1	1
315	1	1
317	1	1
321	1	1
341	1	1
342	1	1
343	1	1
344	1	1
374	1	1
375	1	1
377	1	1
378	1	1
379	1	1
380	1	1
			MISSING_ELSE
386	1	1
387	1	1
389	1	1
390	1	1
391	1	1
			MISSING_ELSE
397	1	1
398	1	1
407	1	1
408	1	1
410	1	1
411	1	1
418	1	1
421	1	1
425	1	1
426		unreachable
428		unreachable
435		unreachable
441	1	1
445	1	1
447	1	1
			MISSING_ELSE
462	1	1
467	1	1
472		unreachable

---

Line Coverage for Module : tlul_adapter_sram ( parameter SramAw=1,SramDw=32,Outstanding=1,ByteAccess=0,ErrOnWrite=1,ErrOnRead=0,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=1,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Line Coverage for Module self-instances :

SCORE	LINE
87.52	94.20

tb.dut.u_to_rd_fifo

	Line No.	Total	Covered	Percent
TOTAL		69	65	94.20
ALWAYS	94	4	3	75.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	115	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	152	1	1	100.00
CONT_ASSIGN	224	1	1	100.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	226	1	1	100.00
ALWAYS	231	8	6	75.00
ALWAYS	251	6	5	83.33
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
CONT_ASSIGN	288	1	1	100.00
CONT_ASSIGN	293	1	1	100.00
CONT_ASSIGN	299	1	1	100.00
CONT_ASSIGN	311	1	1	100.00
ALWAYS	314	3	3	100.00
CONT_ASSIGN	321	1	1	100.00
CONT_ASSIGN	341	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	343	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
ALWAYS	374	6	6	100.00
ALWAYS	386	5	5	100.00
CONT_ASSIGN	397	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	407	1	1	100.00
CONT_ASSIGN	408	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	425	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	435	1	1	100.00
ALWAYS	441	3	3	100.00
CONT_ASSIGN	462	1	1	100.00
CONT_ASSIGN	467	1	1	100.00
CONT_ASSIGN	472	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
94	1	1
95	1	1
96	1	1
97	0	1
			MISSING_ELSE
103	1	1
108	1	1
115	1	1
120	1	1
140	1	1
152	1	1
224	1	1
225	1	1
226	1	1
231	1	1
233	1	1
234	1	1
236	0	1
237	1	1
238	1	1
241	0	1
244	1	1
251	1	1
253	1	1
254	1	1
255	1	1
257	0	1
260	1	1
265	1	1
269	1	1
288	1	1
293	1	1
299	1	1
311	1	1
314	1	1
315	1	1
317	1	1
321	1	1
341	1	1
342	1	1
343	1	1
344	1	1
374	1	1
375	1	1
377	1	1
378	1	1
379	1	1
380	1	1
			MISSING_ELSE
386	1	1
387	1	1
389	1	1
390	1	1
391	1	1
			MISSING_ELSE
397	1	1
398	1	1
407	1	1
408	1	1
410	1	1
411	1	1
418	1	1
421	1	1
425	1	1
426	1	1
428	1	1
435	1	1
441	1	1
445	1	1
447	1	1
			MISSING_ELSE
462	1	1
467	1	1
472		unreachable

---

Line Coverage for Module : tlul_adapter_sram ( parameter SramAw=18,SramDw=32,Outstanding=2,ByteAccess=0,ErrOnWrite=1,ErrOnRead=0,CmdIntgCheck=1,EnableRspIntgGen=1,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=0,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Line Coverage for Module self-instances :

SCORE	LINE
96.22	100.00

tb.dut.u_tl_adapter_eflash

	Line No.	Total	Covered	Percent
TOTAL		69	69	100.00
ALWAYS	94	4	4	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	115	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	152	1	1	100.00
CONT_ASSIGN	224	1	1	100.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	226	1	1	100.00
ALWAYS	231	8	8	100.00
ALWAYS	251	6	6	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
CONT_ASSIGN	288	1	1	100.00
CONT_ASSIGN	293	1	1	100.00
CONT_ASSIGN	299	1	1	100.00
CONT_ASSIGN	311	1	1	100.00
ALWAYS	314	3	3	100.00
CONT_ASSIGN	321	1	1	100.00
CONT_ASSIGN	341	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	343	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
ALWAYS	374	6	6	100.00
ALWAYS	386	5	5	100.00
CONT_ASSIGN	397	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	407	1	1	100.00
CONT_ASSIGN	408	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	425	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	435	1	1	100.00
ALWAYS	441	3	3	100.00
CONT_ASSIGN	462	1	1	100.00
CONT_ASSIGN	467	1	1	100.00
CONT_ASSIGN	472	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
94	1	1
95	1	1
96	1	1
97	1	1
			MISSING_ELSE
103	1	1
108	1	1
115	1	1
120	1	1
140	1	1
152	1	1
224	1	1
225	1	1
226	1	1
231	1	1
233	1	1
234	1	1
236	1	1
237	1	1
238	1	1
241	1	1
244	1	1
251	1	1
253	1	1
254	1	1
255	1	1
257	1	1
260	1	1
265	1	1
269	1	1
288	1	1
293	1	1
299	1	1
311	1	1
314	1	1
315	1	1
317	1	1
321	1	1
341	1	1
342	1	1
343	1	1
344	1	1
374	1	1
375	1	1
377	1	1
378	1	1
379	1	1
380	1	1
			MISSING_ELSE
386	1	1
387	1	1
389	1	1
390	1	1
391	1	1
			MISSING_ELSE
397	1	1
398	1	1
407	1	1
408	1	1
410	1	1
411	1	1
418	1	1
421	1	1
425	1	1
426	1	1
428	1	1
435	1	1
441	1	1
445	1	1
447	1	1
			MISSING_ELSE
462	1	1
467	1	1
472		unreachable

---

Cond Coverage for Module : tlul_adapter_sram ( parameter SramAw=1,SramDw=32,Outstanding=1,ByteAccess=0,ErrOnWrite=0,ErrOnRead=1,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=0,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Cond Coverage for Module self-instances :

SCORE	COND
83.89	65.22

tb.dut.u_to_prog_fifo

	Total	Covered	Percent
Conditions	115	75	65.22
Logical	115	75	65.22
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (intg_error || rsp_fifo_error)
             -----1----    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Unreachable

 LINE       103
 EXPRESSION (intg_error | rsp_fifo_error | intg_error_q)
             -----1----   -------2------   ------3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Unreachable
1	0	0	Unreachable

 LINE       108
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       108
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       108
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T15,T17
1	0	Covered	T2,T3,T4

 LINE       108
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       126
 EXPRESSION (tl_i.a_opcode == Get)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       140
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Covered	T2,T3,T4
0	0	0	0	0	1	Unreachable
0	0	0	0	1	0	Covered	T1,T2,T3
0	0	0	1	0	0	Not Covered
0	0	1	0	0	0	Not Covered
0	1	0	0	0	0	Unreachable
1	0	0	0	0	0	Not Covered

 LINE       224
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       225
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T15,T16
1	1	Covered	T2,T3,T4

 LINE       226
 EXPRESSION (req_o & gnt_i)
             --1--   --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T15,T16,T86
1	1	Covered	T2,T3,T4

 LINE       237
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Not Covered

 LINE       254
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Not Covered

 LINE       255
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       265
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Not Covered
1	1	1	0	Not Covered
1	1	1	1	Not Covered

 LINE       265
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       293
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       293
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       299
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       299
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       299
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       311
 EXPRESSION (error_internal & tl_i_int.a_valid & ((~tl_o_int.a_ready)))
             -------1------   --------2-------   ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       321
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       321
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       321
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       321
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       321
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       321
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T4
1	1	Not Covered

 LINE       321
 EXPRESSION ((gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready)
             -------------1------------   -------2------   ---------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       321
 SUB-EXPRESSION (gnt_i | missed_err_gnt_q)
                 --1--   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       341
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       343
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       344
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       380
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------

-1-	Status	Tests
0	Covered	T20
1	Covered	T2,T3,T4

 LINE       380
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       411
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       411
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       425
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Not Covered

 LINE       428
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Unreachable
1	1	Unreachable

 LINE       467
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       467
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       467
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Cond Coverage for Module : tlul_adapter_sram ( parameter SramAw=1,SramDw=32,Outstanding=1,ByteAccess=0,ErrOnWrite=1,ErrOnRead=0,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=1,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Cond Coverage for Module self-instances :

SCORE	COND
87.52	73.11

tb.dut.u_to_rd_fifo

	Total	Covered	Percent
Conditions	119	87	73.11
Logical	119	87	73.11
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (intg_error || rsp_fifo_error)
             -----1----    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Unreachable

 LINE       103
 EXPRESSION (intg_error | rsp_fifo_error | intg_error_q)
             -----1----   -------2------   ------3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Unreachable

 LINE       108
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       108
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       108
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T15,T17
1	0	Covered	T2,T3,T4

 LINE       108
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T25

 LINE       108
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T25

 LINE       120
 EXPRESSION (tl_i.a_opcode != Get)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       140
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Covered	T4,T6,T7
0	0	0	0	0	1	Unreachable
0	0	0	0	1	0	Covered	T1,T2,T3
0	0	0	1	0	0	Not Covered
0	0	1	0	0	0	Unreachable
0	1	0	0	0	0	Not Covered
1	0	0	0	0	0	Not Covered

 LINE       224
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Covered	T4,T6,T7
1	1	Covered	T4,T6,T7

 LINE       225
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T15,T17
1	1	Covered	T4,T6,T7

 LINE       226
 EXPRESSION (req_o & gnt_i)
             --1--   --2--

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Covered	T4,T7,T11
1	1	Covered	T4,T6,T7

 LINE       237
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Not Covered
1	Covered	T4,T6,T7

 LINE       254
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Not Covered
1	Covered	T4,T6,T7

 LINE       255
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Not Covered
1	0	Covered	T36,T37,T38

 LINE       265
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Not Covered
1	1	1	0	Not Covered
1	1	1	1	Covered	T4,T6,T7

 LINE       265
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T7

 LINE       293
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T7

 LINE       293
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T36,T37,T38
1	1	Covered	T4,T6,T7

 LINE       299
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       299
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T6,T7
1	1	Not Covered

 LINE       299
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T7

 LINE       311
 EXPRESSION (error_internal & tl_i_int.a_valid & ((~tl_o_int.a_ready)))
             -------1------   --------2-------   ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       321
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       321
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T7
1	1	Not Covered

 LINE       321
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       321
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T7

 LINE       321
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T7

 LINE       321
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T6,T7
1	1	Covered	T36,T37,T38

 LINE       321
 EXPRESSION ((gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready)
             -------------1------------   -------2------   ---------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T39,T96,T88
1	1	0	Not Covered
1	1	1	Covered	T4,T6,T7

 LINE       321
 SUB-EXPRESSION (gnt_i | missed_err_gnt_q)
                 --1--   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T4,T6,T7

 LINE       341
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T6,T7
1	1	0	Not Covered
1	1	1	Covered	T4,T6,T7

 LINE       343
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T7
1	1	Not Covered

 LINE       344
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T7

 LINE       380
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------

-1-	Status	Tests
0	Covered	T4,T6,T7
1	Not Covered

 LINE       380
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T6,T7
1	1	Not Covered

 LINE       411
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       411
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       425
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T6,T7

 LINE       428
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T39,T96,T88
1	0	Not Covered
1	1	Covered	T4,T6,T7

 LINE       467
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T7

 LINE       467
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T6,T7

 LINE       467
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T7

---

Cond Coverage for Module : tlul_adapter_sram ( parameter SramAw=18,SramDw=32,Outstanding=2,ByteAccess=0,ErrOnWrite=1,ErrOnRead=0,CmdIntgCheck=1,EnableRspIntgGen=1,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=0,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Cond Coverage for Module self-instances :

SCORE	COND
96.22	88.33

tb.dut.u_tl_adapter_eflash

	Total	Covered	Percent
Conditions	120	106	88.33
Logical	120	106	88.33
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (intg_error || rsp_fifo_error)
             -----1----    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T19

 LINE       103
 EXPRESSION (intg_error | rsp_fifo_error | intg_error_q)
             -----1----   -------2------   ------3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T19
0	1	0	Unreachable
1	0	0	Covered	T19

 LINE       108
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)

-1-	Status	Tests
0	Covered	T2,T4,T7
1	Covered	T1,T2,T3

 LINE       108
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T7
0	1	Covered	T2,T6,T13
1	0	Covered	T1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T13

 LINE       108
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T13,T27,T77
0	1	Covered	T2,T13,T97
1	0	Covered	T2,T13,T12

 LINE       108
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------

-1-	Status	Tests
0	Covered	T2,T13,T97
1	Covered	T1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------

-1-	Status	Tests
0	Covered	T2,T16,T13
1	Covered	T1,T2,T3

 LINE       120
 EXPRESSION (tl_i.a_opcode != Get)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       140
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Covered	T4,T7,T17
0	0	0	0	0	1	Not Covered
0	0	0	0	1	0	Covered	T2,T13,T69
0	0	0	1	0	0	Covered	T98,T99,T100
0	0	1	0	0	0	Unreachable
0	1	0	0	0	0	Not Covered
1	0	0	0	0	0	Not Covered

 LINE       224
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T98,T101,T102
1	0	Covered	T4,T7,T17
1	1	Covered	T4,T7,T17

 LINE       225
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T27,T28
1	1	Covered	T4,T7,T17

 LINE       226
 EXPRESSION (req_o & gnt_i)
             --1--   --2--

-1-	-2-	Status	Tests
0	1	Covered	T103
1	0	Covered	T4,T7,T17
1	1	Covered	T4,T7,T17

 LINE       237
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Covered	T20
1	Covered	T4,T7,T17

 LINE       254
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Covered	T19,T20
1	Covered	T4,T7,T17

 LINE       255
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T7,T17
0	1	Covered	T98,T99,T100
1	0	Covered	T75,T45,T46

 LINE       265
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T98,T99,T100
1	1	1	0	Not Covered
1	1	1	1	Covered	T4,T7,T17

 LINE       265
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T17

 LINE       293
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T17

 LINE       293
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T75,T45,T46
1	1	Covered	T4,T7,T17

 LINE       299
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       299
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T98,T99,T100
1	0	Covered	T4,T7,T17
1	1	Not Covered

 LINE       299
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T17

 LINE       311
 EXPRESSION (error_internal & tl_i_int.a_valid & ((~tl_o_int.a_ready)))
             -------1------   --------2-------   ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T7,T17
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T98,T99,T100
1	1	1	Covered	T98,T99,T100

 LINE       321
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T19

 LINE       321
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T7,T17
1	1	Covered	T19

 LINE       321
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       321
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T17

 LINE       321
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T17

 LINE       321
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T7,T17
1	1	Covered	T75,T45,T46

 LINE       321
 EXPRESSION ((gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready)
             -------------1------------   -------2------   ---------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T98,T100,T104
1	1	0	Not Covered
1	1	1	Covered	T4,T7,T17

 LINE       321
 SUB-EXPRESSION (gnt_i | missed_err_gnt_q)
                 --1--   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T98,T99,T100
1	0	Covered	T4,T7,T17

 LINE       341
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T7,T17
1	1	0	Covered	T98,T99,T100
1	1	1	Covered	T4,T7,T17

 LINE       343
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T7,T17
1	1	Covered	T19

 LINE       344
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T17

 LINE       380
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------

-1-	Status	Tests
0	Covered	T4,T7,T17
1	Covered	T19

 LINE       380
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T7,T17
1	1	Covered	T19

 LINE       411
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------

-1-	Status	Tests
0	Covered	T2,T4,T7
1	Covered	T1,T2,T3

 LINE       411
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       425
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T7,T17

 LINE       428
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T17
1	0	Not Covered
1	1	Covered	T4,T7,T17

 LINE       467
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T17

 LINE       467
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T98,T99,T100
1	1	Covered	T4,T7,T17

 LINE       467
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T17

---

Branch Coverage for Module : tlul_adapter_sram

	Line No.	Total	Covered	Percent
Branches		29	28	96.55
TERNARY	108	2	2	100.00
TERNARY	293	2	2	100.00
TERNARY	299	3	2	66.67
TERNARY	344	2	2	100.00
TERNARY	467	2	2	100.00
IF	94	3	3	100.00
IF	233	4	4	100.00
IF	253	3	3	100.00
IF	314	2	2	100.00
IF	377	2	2	100.00
IF	389	2	2	100.00
IF	445	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	108	(((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	293	((vld_rd_rsp & (~d_error))) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	299	((vld_rd_rsp && reqfifo_rdata.error)) ? 
-2-:	299	(vld_rd_rsp) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T4,T6,T7
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	344	(tl_i_int.a_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	467	(((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	94	if ((!rst_ni))
-2-:	96	if ((intg_error || rsp_fifo_error))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T19,T20
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	233	if (reqfifo_rvalid)
-2-:	234	if (reqfifo_rdata.error)
-3-:	237	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T98,T99,T100
1	0	1	Covered	T4,T6,T7
1	0	0	Covered	T2,T3,T4
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	253	if (reqfifo_rvalid)
-2-:	254	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T4,T6,T7
1	0	Covered	T2,T3,T4
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	314	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	377	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	389	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	445	if ((|sramreqfifo_rdata.mask))

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Module : tlul_adapter_sram

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AddrOutKnown_A	1087502445	1085232693	0	0
DataIntgOptions_A	2619	2619	0	0
ReqOutKnown_A	1087502445	1085232693	0	0
SramDwHasByteGranularity_A	2619	2619	0	0
SramDwIsMultipleOfTlulWidth_A	2619	2619	0	0
TlOutKnownIfFifoKnown_A	1087502445	1085232693	0	0
TlOutValidKnown_A	1087502445	1085232693	0	0
WdataOutKnown_A	1087502445	1085232693	0	0
WeOutKnown_A	1087502445	1085232693	0	0
WmaskOutKnown_A	1087502445	1085232693	0	0
adapterNoReadOrWrite	2619	2619	0	0
rvalidHighReqFifoEmpty	1087502445	6708883	0	0
rvalidHighWhenRspFifoFull	1087502445	6708883	0	0

AddrOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1087502445	1085232693	0	0
T1	4377	4098	0	0
T2	136191	133080	0	0
T3	878079	877809	0	0
T4	62280	61716	0	0
T6	2276256	2275956	0	0
T7	1018437	1018284	0	0
T11	5862	5571	0	0
T15	7185	7002	0	0
T17	210576	210381	0	0
T25	3150	2886	0	0

DataIntgOptions_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2619	2619	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T11	3	3	0	0
T15	3	3	0	0
T17	3	3	0	0
T25	3	3	0	0

ReqOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1087502445	1085232693	0	0
T1	4377	4098	0	0
T2	136191	133080	0	0
T3	878079	877809	0	0
T4	62280	61716	0	0
T6	2276256	2275956	0	0
T7	1018437	1018284	0	0
T11	5862	5571	0	0
T15	7185	7002	0	0
T17	210576	210381	0	0
T25	3150	2886	0	0

SramDwHasByteGranularity_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2619	2619	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T11	3	3	0	0
T15	3	3	0	0
T17	3	3	0	0
T25	3	3	0	0

SramDwIsMultipleOfTlulWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2619	2619	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T11	3	3	0	0
T15	3	3	0	0
T17	3	3	0	0
T25	3	3	0	0

TlOutKnownIfFifoKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1087502445	1085232693	0	0
T1	4377	4098	0	0
T2	136191	133080	0	0
T3	878079	877809	0	0
T4	62280	61716	0	0
T6	2276256	2275956	0	0
T7	1018437	1018284	0	0
T11	5862	5571	0	0
T15	7185	7002	0	0
T17	210576	210381	0	0
T25	3150	2886	0	0

TlOutValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1087502445	1085232693	0	0
T1	4377	4098	0	0
T2	136191	133080	0	0
T3	878079	877809	0	0
T4	62280	61716	0	0
T6	2276256	2275956	0	0
T7	1018437	1018284	0	0
T11	5862	5571	0	0
T15	7185	7002	0	0
T17	210576	210381	0	0
T25	3150	2886	0	0

WdataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1087502445	1085232693	0	0
T1	4377	4098	0	0
T2	136191	133080	0	0
T3	878079	877809	0	0
T4	62280	61716	0	0
T6	2276256	2275956	0	0
T7	1018437	1018284	0	0
T11	5862	5571	0	0
T15	7185	7002	0	0
T17	210576	210381	0	0
T25	3150	2886	0	0

WeOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1087502445	1085232693	0	0
T1	4377	4098	0	0
T2	136191	133080	0	0
T3	878079	877809	0	0
T4	62280	61716	0	0
T6	2276256	2275956	0	0
T7	1018437	1018284	0	0
T11	5862	5571	0	0
T15	7185	7002	0	0
T17	210576	210381	0	0
T25	3150	2886	0	0

WmaskOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1087502445	1085232693	0	0
T1	4377	4098	0	0
T2	136191	133080	0	0
T3	878079	877809	0	0
T4	62280	61716	0	0
T6	2276256	2275956	0	0
T7	1018437	1018284	0	0
T11	5862	5571	0	0
T15	7185	7002	0	0
T17	210576	210381	0	0
T25	3150	2886	0	0

adapterNoReadOrWrite

Name	Attempts	Real Successes	Failures	Incomplete
Total	2619	2619	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T11	3	3	0	0
T15	3	3	0	0
T17	3	3	0	0
T25	3	3	0	0

rvalidHighReqFifoEmpty

Name	Attempts	Real Successes	Failures	Incomplete
Total	1087502445	6708883	0	0
T4	41520	277	0	0
T5	1632384	28875	0	0
T6	1517504	974	0	0
T7	678958	52995	0	0
T11	3908	22	0	0
T13	0	33695	0	0
T14	0	16556	0	0
T15	4790	11	0	0
T16	5720	13	0	0
T17	140384	26779	0	0
T21	7560	0	0	0
T33	4310	0	0	0
T39	0	9096	0	0
T75	0	8	0	0
T84	0	16965	0	0
T85	0	166	0	0
T86	0	53	0	0

rvalidHighWhenRspFifoFull

Name	Attempts	Real Successes	Failures	Incomplete
Total	1087502445	6708883	0	0
T4	41520	277	0	0
T5	1632384	28875	0	0
T6	1517504	974	0	0
T7	678958	52995	0	0
T11	3908	22	0	0
T13	0	33695	0	0
T14	0	16556	0	0
T15	4790	11	0	0
T16	5720	13	0	0
T17	140384	26779	0	0
T21	7560	0	0	0
T33	4310	0	0	0
T39	0	9096	0	0
T75	0	8	0	0
T84	0	16965	0	0
T85	0	166	0	0
T86	0	53	0	0

Line Coverage for Instance : tb.dut.u_to_prog_fifo

	Line No.	Total	Covered	Percent
TOTAL		65	65	100.00
ALWAYS	94	3	3	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	115	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	152	1	1	100.00
CONT_ASSIGN	224	1	1	100.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	226	1	1	100.00
ALWAYS	231	8	8	100.00
ALWAYS	251	6	6	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
CONT_ASSIGN	288	1	1	100.00
CONT_ASSIGN	293	1	1	100.00
CONT_ASSIGN	299	1	1	100.00
CONT_ASSIGN	311	1	1	100.00
ALWAYS	314	3	3	100.00
CONT_ASSIGN	321	1	1	100.00
CONT_ASSIGN	341	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	343	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
ALWAYS	374	6	6	100.00
ALWAYS	386	5	5	100.00
CONT_ASSIGN	397	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	407	1	1	100.00
CONT_ASSIGN	408	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	425	1	1	100.00
CONT_ASSIGN	426	0	0
CONT_ASSIGN	428	0	0
CONT_ASSIGN	435	0	0
ALWAYS	441	3	3	100.00
CONT_ASSIGN	462	1	1	100.00
CONT_ASSIGN	467	1	1	100.00
CONT_ASSIGN	472	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
94	1	1
95	1	1
96	1	1
97		unreachable
			MISSING_ELSE
103	1	1
108	1	1
115	1	1
126	1	1
140	1	1
152	1	1
224	1	1
225	1	1
226	1	1
231	1	1
233	1	1
234	1	1
236	1	1
237	1	1
238	1	1
241	1	1
244	1	1
251	1	1
253	1	1
254	1	1
255	1	1
257	1	1
260	1	1
265	1	1
269	1	1
288	1	1
293	1	1
299	1	1
311	1	1
314	1	1
315	1	1
317	1	1
321	1	1
341	1	1
342	1	1
343	1	1
344	1	1
374	1	1
375	1	1
377	1	1
378	1	1
379	1	1
380	1	1
			MISSING_ELSE
386	1	1
387	1	1
389	1	1
390	1	1
391	1	1
			MISSING_ELSE
397	1	1
398	1	1
407	1	1
408	1	1
410	1	1
411	1	1
418	1	1
421	1	1
425	1	1
426		unreachable
428		unreachable
435		unreachable
441	1	1
445	1	1
447	1	1
			MISSING_ELSE
462	1	1
467	1	1
472		unreachable

---

Cond Coverage for Instance : tb.dut.u_to_prog_fifo

	Total	Covered	Percent
Conditions	115	75	65.22
Logical	115	75	65.22
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (intg_error || rsp_fifo_error)
             -----1----    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Unreachable

 LINE       103
 EXPRESSION (intg_error | rsp_fifo_error | intg_error_q)
             -----1----   -------2------   ------3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Unreachable
1	0	0	Unreachable

 LINE       108
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       108
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       108
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T15,T17
1	0	Covered	T2,T3,T4

 LINE       108
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       126
 EXPRESSION (tl_i.a_opcode == Get)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       140
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Covered	T2,T3,T4
0	0	0	0	0	1	Unreachable
0	0	0	0	1	0	Covered	T1,T2,T3
0	0	0	1	0	0	Not Covered
0	0	1	0	0	0	Not Covered
0	1	0	0	0	0	Unreachable
1	0	0	0	0	0	Not Covered

 LINE       224
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       225
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T15,T16
1	1	Covered	T2,T3,T4

 LINE       226
 EXPRESSION (req_o & gnt_i)
             --1--   --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T15,T16,T86
1	1	Covered	T2,T3,T4

 LINE       237
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Not Covered

 LINE       254
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Not Covered

 LINE       255
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       265
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Not Covered
1	1	1	0	Not Covered
1	1	1	1	Not Covered

 LINE       265
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       293
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       293
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       299
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       299
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       299
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       311
 EXPRESSION (error_internal & tl_i_int.a_valid & ((~tl_o_int.a_ready)))
             -------1------   --------2-------   ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       321
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       321
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       321
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       321
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       321
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       321
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T4
1	1	Not Covered

 LINE       321
 EXPRESSION ((gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready)
             -------------1------------   -------2------   ---------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       321
 SUB-EXPRESSION (gnt_i | missed_err_gnt_q)
                 --1--   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       341
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       343
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       344
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       380
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------

-1-	Status	Tests
0	Covered	T20
1	Covered	T2,T3,T4

 LINE       380
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       411
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       411
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       425
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Not Covered

 LINE       428
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Unreachable
1	1	Unreachable

 LINE       467
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       467
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       467
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.u_to_prog_fifo

	Line No.	Total	Covered	Percent
Branches		28	24	85.71
TERNARY	108	2	2	100.00
TERNARY	293	2	1	50.00
TERNARY	299	3	1	33.33
TERNARY	344	2	2	100.00
TERNARY	467	2	1	50.00
IF	94	2	2	100.00
IF	233	4	4	100.00
IF	253	3	3	100.00
IF	314	2	2	100.00
IF	377	2	2	100.00
IF	389	2	2	100.00
IF	445	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	108	(((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	293	((vld_rd_rsp & (~d_error))) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	299	((vld_rd_rsp && reqfifo_rdata.error)) ? 
-2-:	299	(vld_rd_rsp) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	344	(tl_i_int.a_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	467	(((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	94	if ((!rst_ni))
-2-:	96	if ((intg_error || rsp_fifo_error))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Unreachable
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	233	if (reqfifo_rvalid)
-2-:	234	if (reqfifo_rdata.error)
-3-:	237	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T20
1	0	1	Covered	T20
1	0	0	Covered	T2,T3,T4
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	253	if (reqfifo_rvalid)
-2-:	254	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T20
1	0	Covered	T2,T3,T4
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	314	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	377	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	389	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	445	if ((|sramreqfifo_rdata.mask))

Branches:

-1-	Status	Tests
1	Covered	T20
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_to_prog_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	11	84.62
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	11	84.62

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AddrOutKnown_A	362500815	361744231	0	0
DataIntgOptions_A	873	873	0	0
ReqOutKnown_A	362500815	361744231	0	0
SramDwHasByteGranularity_A	873	873	0	0
SramDwIsMultipleOfTlulWidth_A	873	873	0	0
TlOutKnownIfFifoKnown_A	362500815	361744231	0	0
TlOutValidKnown_A	362500815	361744231	0	0
WdataOutKnown_A	362500815	361744231	0	0
WeOutKnown_A	362500815	361744231	0	0
WmaskOutKnown_A	362500815	361744231	0	0
adapterNoReadOrWrite	873	873	0	0
rvalidHighReqFifoEmpty	362500815	0	0	0
rvalidHighWhenRspFifoFull	362500815	0	0	0

AddrOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362500815	361744231	0	0
T1	1459	1366	0	0
T2	45397	44360	0	0
T3	292693	292603	0	0
T4	20760	20572	0	0
T6	758752	758652	0	0
T7	339479	339428	0	0
T11	1954	1857	0	0
T15	2395	2334	0	0
T17	70192	70127	0	0
T25	1050	962	0	0

DataIntgOptions_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	873	873	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T25	1	1	0	0

ReqOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362500815	361744231	0	0
T1	1459	1366	0	0
T2	45397	44360	0	0
T3	292693	292603	0	0
T4	20760	20572	0	0
T6	758752	758652	0	0
T7	339479	339428	0	0
T11	1954	1857	0	0
T15	2395	2334	0	0
T17	70192	70127	0	0
T25	1050	962	0	0

SramDwHasByteGranularity_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	873	873	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T25	1	1	0	0

SramDwIsMultipleOfTlulWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	873	873	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T25	1	1	0	0

TlOutKnownIfFifoKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362500815	361744231	0	0
T1	1459	1366	0	0
T2	45397	44360	0	0
T3	292693	292603	0	0
T4	20760	20572	0	0
T6	758752	758652	0	0
T7	339479	339428	0	0
T11	1954	1857	0	0
T15	2395	2334	0	0
T17	70192	70127	0	0
T25	1050	962	0	0

TlOutValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362500815	361744231	0	0
T1	1459	1366	0	0
T2	45397	44360	0	0
T3	292693	292603	0	0
T4	20760	20572	0	0
T6	758752	758652	0	0
T7	339479	339428	0	0
T11	1954	1857	0	0
T15	2395	2334	0	0
T17	70192	70127	0	0
T25	1050	962	0	0

WdataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362500815	361744231	0	0
T1	1459	1366	0	0
T2	45397	44360	0	0
T3	292693	292603	0	0
T4	20760	20572	0	0
T6	758752	758652	0	0
T7	339479	339428	0	0
T11	1954	1857	0	0
T15	2395	2334	0	0
T17	70192	70127	0	0
T25	1050	962	0	0

WeOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362500815	361744231	0	0
T1	1459	1366	0	0
T2	45397	44360	0	0
T3	292693	292603	0	0
T4	20760	20572	0	0
T6	758752	758652	0	0
T7	339479	339428	0	0
T11	1954	1857	0	0
T15	2395	2334	0	0
T17	70192	70127	0	0
T25	1050	962	0	0

WmaskOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362500815	361744231	0	0
T1	1459	1366	0	0
T2	45397	44360	0	0
T3	292693	292603	0	0
T4	20760	20572	0	0
T6	758752	758652	0	0
T7	339479	339428	0	0
T11	1954	1857	0	0
T15	2395	2334	0	0
T17	70192	70127	0	0
T25	1050	962	0	0

adapterNoReadOrWrite

Name	Attempts	Real Successes	Failures	Incomplete
Total	873	873	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T25	1	1	0	0

rvalidHighReqFifoEmpty

Name	Attempts	Real Successes	Failures	Incomplete
Total	362500815	0	0	0

rvalidHighWhenRspFifoFull

Name	Attempts	Real Successes	Failures	Incomplete
Total	362500815	0	0	0

Line Coverage for Instance : tb.dut.u_to_rd_fifo

	Line No.	Total	Covered	Percent
TOTAL		69	65	94.20
ALWAYS	94	4	3	75.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	115	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	152	1	1	100.00
CONT_ASSIGN	224	1	1	100.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	226	1	1	100.00
ALWAYS	231	8	6	75.00
ALWAYS	251	6	5	83.33
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
CONT_ASSIGN	288	1	1	100.00
CONT_ASSIGN	293	1	1	100.00
CONT_ASSIGN	299	1	1	100.00
CONT_ASSIGN	311	1	1	100.00
ALWAYS	314	3	3	100.00
CONT_ASSIGN	321	1	1	100.00
CONT_ASSIGN	341	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	343	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
ALWAYS	374	6	6	100.00
ALWAYS	386	5	5	100.00
CONT_ASSIGN	397	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	407	1	1	100.00
CONT_ASSIGN	408	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	425	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	435	1	1	100.00
ALWAYS	441	3	3	100.00
CONT_ASSIGN	462	1	1	100.00
CONT_ASSIGN	467	1	1	100.00
CONT_ASSIGN	472	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
94	1	1
95	1	1
96	1	1
97	0	1
			MISSING_ELSE
103	1	1
108	1	1
115	1	1
120	1	1
140	1	1
152	1	1
224	1	1
225	1	1
226	1	1
231	1	1
233	1	1
234	1	1
236	0	1
237	1	1
238	1	1
241	0	1
244	1	1
251	1	1
253	1	1
254	1	1
255	1	1
257	0	1
260	1	1
265	1	1
269	1	1
288	1	1
293	1	1
299	1	1
311	1	1
314	1	1
315	1	1
317	1	1
321	1	1
341	1	1
342	1	1
343	1	1
344	1	1
374	1	1
375	1	1
377	1	1
378	1	1
379	1	1
380	1	1
			MISSING_ELSE
386	1	1
387	1	1
389	1	1
390	1	1
391	1	1
			MISSING_ELSE
397	1	1
398	1	1
407	1	1
408	1	1
410	1	1
411	1	1
418	1	1
421	1	1
425	1	1
426	1	1
428	1	1
435	1	1
441	1	1
445	1	1
447	1	1
			MISSING_ELSE
462	1	1
467	1	1
472		unreachable

---

Cond Coverage for Instance : tb.dut.u_to_rd_fifo

	Total	Covered	Percent
Conditions	119	87	73.11
Logical	119	87	73.11
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (intg_error || rsp_fifo_error)
             -----1----    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Unreachable

 LINE       103
 EXPRESSION (intg_error | rsp_fifo_error | intg_error_q)
             -----1----   -------2------   ------3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Unreachable

 LINE       108
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       108
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       108
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T15,T17
1	0	Covered	T2,T3,T4

 LINE       108
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T25

 LINE       108
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T25

 LINE       120
 EXPRESSION (tl_i.a_opcode != Get)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       140
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Covered	T4,T6,T7
0	0	0	0	0	1	Unreachable
0	0	0	0	1	0	Covered	T1,T2,T3
0	0	0	1	0	0	Not Covered
0	0	1	0	0	0	Unreachable
0	1	0	0	0	0	Not Covered
1	0	0	0	0	0	Not Covered

 LINE       224
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Covered	T4,T6,T7
1	1	Covered	T4,T6,T7

 LINE       225
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T15,T17
1	1	Covered	T4,T6,T7

 LINE       226
 EXPRESSION (req_o & gnt_i)
             --1--   --2--

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Covered	T4,T7,T11
1	1	Covered	T4,T6,T7

 LINE       237
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Not Covered
1	Covered	T4,T6,T7

 LINE       254
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Not Covered
1	Covered	T4,T6,T7

 LINE       255
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Not Covered
1	0	Covered	T36,T37,T38

 LINE       265
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Not Covered
1	1	1	0	Not Covered
1	1	1	1	Covered	T4,T6,T7

 LINE       265
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T7

 LINE       293
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T7

 LINE       293
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T36,T37,T38
1	1	Covered	T4,T6,T7

 LINE       299
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       299
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T6,T7
1	1	Not Covered

 LINE       299
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T7

 LINE       311
 EXPRESSION (error_internal & tl_i_int.a_valid & ((~tl_o_int.a_ready)))
             -------1------   --------2-------   ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       321
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       321
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T7
1	1	Not Covered

 LINE       321
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       321
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T7

 LINE       321
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T7

 LINE       321
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T6,T7
1	1	Covered	T36,T37,T38

 LINE       321
 EXPRESSION ((gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready)
             -------------1------------   -------2------   ---------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T39,T96,T88
1	1	0	Not Covered
1	1	1	Covered	T4,T6,T7

 LINE       321
 SUB-EXPRESSION (gnt_i | missed_err_gnt_q)
                 --1--   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T4,T6,T7

 LINE       341
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T6,T7
1	1	0	Not Covered
1	1	1	Covered	T4,T6,T7

 LINE       343
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T7
1	1	Not Covered

 LINE       344
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T7

 LINE       380
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------

-1-	Status	Tests
0	Covered	T4,T6,T7
1	Not Covered

 LINE       380
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T6,T7
1	1	Not Covered

 LINE       411
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       411
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       425
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T6,T7

 LINE       428
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T39,T96,T88
1	0	Not Covered
1	1	Covered	T4,T6,T7

 LINE       467
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T7

 LINE       467
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T6,T7

 LINE       467
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T7

---

Branch Coverage for Instance : tb.dut.u_to_rd_fifo

	Line No.	Total	Covered	Percent
Branches		29	24	82.76
TERNARY	108	2	2	100.00
TERNARY	293	2	2	100.00
TERNARY	299	3	2	66.67
TERNARY	344	2	2	100.00
TERNARY	467	2	2	100.00
IF	94	3	2	66.67
IF	233	4	2	50.00
IF	253	3	2	66.67
IF	314	2	2	100.00
IF	377	2	2	100.00
IF	389	2	2	100.00
IF	445	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	108	(((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	293	((vld_rd_rsp & (~d_error))) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	299	((vld_rd_rsp && reqfifo_rdata.error)) ? 
-2-:	299	(vld_rd_rsp) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T4,T6,T7
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	344	(tl_i_int.a_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	467	(((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	94	if ((!rst_ni))
-2-:	96	if ((intg_error || rsp_fifo_error))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	233	if (reqfifo_rvalid)
-2-:	234	if (reqfifo_rdata.error)
-3-:	237	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Not Covered
1	0	1	Covered	T4,T6,T7
1	0	0	Not Covered
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	253	if (reqfifo_rvalid)
-2-:	254	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T4,T6,T7
1	0	Not Covered
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	314	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	377	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	389	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	445	if ((|sramreqfifo_rdata.mask))

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_to_rd_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AddrOutKnown_A	362500815	361744231	0	0
DataIntgOptions_A	873	873	0	0
ReqOutKnown_A	362500815	361744231	0	0
SramDwHasByteGranularity_A	873	873	0	0
SramDwIsMultipleOfTlulWidth_A	873	873	0	0
TlOutKnownIfFifoKnown_A	362500815	361744231	0	0
TlOutValidKnown_A	362500815	361744231	0	0
WdataOutKnown_A	362500815	361744231	0	0
WeOutKnown_A	362500815	361744231	0	0
WmaskOutKnown_A	362500815	361744231	0	0
adapterNoReadOrWrite	873	873	0	0
rvalidHighReqFifoEmpty	362500815	3271332	0	0
rvalidHighWhenRspFifoFull	362500815	3271332	0	0

AddrOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362500815	361744231	0	0
T1	1459	1366	0	0
T2	45397	44360	0	0
T3	292693	292603	0	0
T4	20760	20572	0	0
T6	758752	758652	0	0
T7	339479	339428	0	0
T11	1954	1857	0	0
T15	2395	2334	0	0
T17	70192	70127	0	0
T25	1050	962	0	0

DataIntgOptions_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	873	873	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T25	1	1	0	0

ReqOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362500815	361744231	0	0
T1	1459	1366	0	0
T2	45397	44360	0	0
T3	292693	292603	0	0
T4	20760	20572	0	0
T6	758752	758652	0	0
T7	339479	339428	0	0
T11	1954	1857	0	0
T15	2395	2334	0	0
T17	70192	70127	0	0
T25	1050	962	0	0

SramDwHasByteGranularity_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	873	873	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T25	1	1	0	0

SramDwIsMultipleOfTlulWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	873	873	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T25	1	1	0	0

TlOutKnownIfFifoKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362500815	361744231	0	0
T1	1459	1366	0	0
T2	45397	44360	0	0
T3	292693	292603	0	0
T4	20760	20572	0	0
T6	758752	758652	0	0
T7	339479	339428	0	0
T11	1954	1857	0	0
T15	2395	2334	0	0
T17	70192	70127	0	0
T25	1050	962	0	0

TlOutValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362500815	361744231	0	0
T1	1459	1366	0	0
T2	45397	44360	0	0
T3	292693	292603	0	0
T4	20760	20572	0	0
T6	758752	758652	0	0
T7	339479	339428	0	0
T11	1954	1857	0	0
T15	2395	2334	0	0
T17	70192	70127	0	0
T25	1050	962	0	0

WdataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362500815	361744231	0	0
T1	1459	1366	0	0
T2	45397	44360	0	0
T3	292693	292603	0	0
T4	20760	20572	0	0
T6	758752	758652	0	0
T7	339479	339428	0	0
T11	1954	1857	0	0
T15	2395	2334	0	0
T17	70192	70127	0	0
T25	1050	962	0	0

WeOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362500815	361744231	0	0
T1	1459	1366	0	0
T2	45397	44360	0	0
T3	292693	292603	0	0
T4	20760	20572	0	0
T6	758752	758652	0	0
T7	339479	339428	0	0
T11	1954	1857	0	0
T15	2395	2334	0	0
T17	70192	70127	0	0
T25	1050	962	0	0

WmaskOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362500815	361744231	0	0
T1	1459	1366	0	0
T2	45397	44360	0	0
T3	292693	292603	0	0
T4	20760	20572	0	0
T6	758752	758652	0	0
T7	339479	339428	0	0
T11	1954	1857	0	0
T15	2395	2334	0	0
T17	70192	70127	0	0
T25	1050	962	0	0

adapterNoReadOrWrite

Name	Attempts	Real Successes	Failures	Incomplete
Total	873	873	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T25	1	1	0	0

rvalidHighReqFifoEmpty

Name	Attempts	Real Successes	Failures	Incomplete
Total	362500815	3271332	0	0
T4	20760	146	0	0
T5	816192	12512	0	0
T6	758752	974	0	0
T7	339479	11522	0	0
T11	1954	22	0	0
T13	0	17296	0	0
T15	2395	11	0	0
T16	2860	13	0	0
T17	70192	10278	0	0
T21	3780	0	0	0
T33	2155	0	0	0
T39	0	9096	0	0

rvalidHighWhenRspFifoFull

Name	Attempts	Real Successes	Failures	Incomplete
Total	362500815	3271332	0	0
T4	20760	146	0	0
T5	816192	12512	0	0
T6	758752	974	0	0
T7	339479	11522	0	0
T11	1954	22	0	0
T13	0	17296	0	0
T15	2395	11	0	0
T16	2860	13	0	0
T17	70192	10278	0	0
T21	3780	0	0	0
T33	2155	0	0	0
T39	0	9096	0	0

Line Coverage for Instance : tb.dut.u_tl_adapter_eflash

	Line No.	Total	Covered	Percent
TOTAL		69	69	100.00
ALWAYS	94	4	4	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	115	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	152	1	1	100.00
CONT_ASSIGN	224	1	1	100.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	226	1	1	100.00
ALWAYS	231	8	8	100.00
ALWAYS	251	6	6	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
CONT_ASSIGN	288	1	1	100.00
CONT_ASSIGN	293	1	1	100.00
CONT_ASSIGN	299	1	1	100.00
CONT_ASSIGN	311	1	1	100.00
ALWAYS	314	3	3	100.00
CONT_ASSIGN	321	1	1	100.00
CONT_ASSIGN	341	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	343	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
ALWAYS	374	6	6	100.00
ALWAYS	386	5	5	100.00
CONT_ASSIGN	397	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	407	1	1	100.00
CONT_ASSIGN	408	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	425	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	435	1	1	100.00
ALWAYS	441	3	3	100.00
CONT_ASSIGN	462	1	1	100.00
CONT_ASSIGN	467	1	1	100.00
CONT_ASSIGN	472	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
94	1	1
95	1	1
96	1	1
97	1	1
			MISSING_ELSE
103	1	1
108	1	1
115	1	1
120	1	1
140	1	1
152	1	1
224	1	1
225	1	1
226	1	1
231	1	1
233	1	1
234	1	1
236	1	1
237	1	1
238	1	1
241	1	1
244	1	1
251	1	1
253	1	1
254	1	1
255	1	1
257	1	1
260	1	1
265	1	1
269	1	1
288	1	1
293	1	1
299	1	1
311	1	1
314	1	1
315	1	1
317	1	1
321	1	1
341	1	1
342	1	1
343	1	1
344	1	1
374	1	1
375	1	1
377	1	1
378	1	1
379	1	1
380	1	1
			MISSING_ELSE
386	1	1
387	1	1
389	1	1
390	1	1
391	1	1
			MISSING_ELSE
397	1	1
398	1	1
407	1	1
408	1	1
410	1	1
411	1	1
418	1	1
421	1	1
425	1	1
426	1	1
428	1	1
435	1	1
441	1	1
445	1	1
447	1	1
			MISSING_ELSE
462	1	1
467	1	1
472		unreachable

---

Cond Coverage for Instance : tb.dut.u_tl_adapter_eflash

	Total	Covered	Percent
Conditions	120	106	88.33
Logical	120	106	88.33
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (intg_error || rsp_fifo_error)
             -----1----    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T19

 LINE       103
 EXPRESSION (intg_error | rsp_fifo_error | intg_error_q)
             -----1----   -------2------   ------3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T19
0	1	0	Unreachable
1	0	0	Covered	T19

 LINE       108
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)

-1-	Status	Tests
0	Covered	T2,T4,T7
1	Covered	T1,T2,T3

 LINE       108
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T7
0	1	Covered	T2,T6,T13
1	0	Covered	T1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T13

 LINE       108
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T13,T27,T77
0	1	Covered	T2,T13,T97
1	0	Covered	T2,T13,T12

 LINE       108
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------

-1-	Status	Tests
0	Covered	T2,T13,T97
1	Covered	T1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------

-1-	Status	Tests
0	Covered	T2,T16,T13
1	Covered	T1,T2,T3

 LINE       120
 EXPRESSION (tl_i.a_opcode != Get)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       140
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Covered	T4,T7,T17
0	0	0	0	0	1	Not Covered
0	0	0	0	1	0	Covered	T2,T13,T69
0	0	0	1	0	0	Covered	T98,T99,T100
0	0	1	0	0	0	Unreachable
0	1	0	0	0	0	Not Covered
1	0	0	0	0	0	Not Covered

 LINE       224
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T98,T101,T102
1	0	Covered	T4,T7,T17
1	1	Covered	T4,T7,T17

 LINE       225
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T27,T28
1	1	Covered	T4,T7,T17

 LINE       226
 EXPRESSION (req_o & gnt_i)
             --1--   --2--

-1-	-2-	Status	Tests
0	1	Covered	T103
1	0	Covered	T4,T7,T17
1	1	Covered	T4,T7,T17

 LINE       237
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Covered	T20
1	Covered	T4,T7,T17

 LINE       254
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Covered	T19,T20
1	Covered	T4,T7,T17

 LINE       255
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T7,T17
0	1	Covered	T98,T99,T100
1	0	Covered	T75,T45,T46

 LINE       265
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T98,T99,T100
1	1	1	0	Not Covered
1	1	1	1	Covered	T4,T7,T17

 LINE       265
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T17

 LINE       293
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T17

 LINE       293
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T75,T45,T46
1	1	Covered	T4,T7,T17

 LINE       299
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       299
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T98,T99,T100
1	0	Covered	T4,T7,T17
1	1	Not Covered

 LINE       299
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T17

 LINE       311
 EXPRESSION (error_internal & tl_i_int.a_valid & ((~tl_o_int.a_ready)))
             -------1------   --------2-------   ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T7,T17
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T98,T99,T100
1	1	1	Covered	T98,T99,T100

 LINE       321
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T19

 LINE       321
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T7,T17
1	1	Covered	T19

 LINE       321
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       321
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T17

 LINE       321
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T17

 LINE       321
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T7,T17
1	1	Covered	T75,T45,T46

 LINE       321
 EXPRESSION ((gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready)
             -------------1------------   -------2------   ---------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T98,T100,T104
1	1	0	Not Covered
1	1	1	Covered	T4,T7,T17

 LINE       321
 SUB-EXPRESSION (gnt_i | missed_err_gnt_q)
                 --1--   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T98,T99,T100
1	0	Covered	T4,T7,T17

 LINE       341
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T7,T17
1	1	0	Covered	T98,T99,T100
1	1	1	Covered	T4,T7,T17

 LINE       343
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T7,T17
1	1	Covered	T19

 LINE       344
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T17

 LINE       380
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------

-1-	Status	Tests
0	Covered	T4,T7,T17
1	Covered	T19

 LINE       380
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T7,T17
1	1	Covered	T19

 LINE       411
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------

-1-	Status	Tests
0	Covered	T2,T4,T7
1	Covered	T1,T2,T3

 LINE       411
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       425
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T7,T17

 LINE       428
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T17
1	0	Not Covered
1	1	Covered	T4,T7,T17

 LINE       467
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T17

 LINE       467
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T98,T99,T100
1	1	Covered	T4,T7,T17

 LINE       467
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T17

---

Branch Coverage for Instance : tb.dut.u_tl_adapter_eflash

	Line No.	Total	Covered	Percent
Branches		29	28	96.55
TERNARY	108	2	2	100.00
TERNARY	293	2	2	100.00
TERNARY	299	3	2	66.67
TERNARY	344	2	2	100.00
TERNARY	467	2	2	100.00
IF	94	3	3	100.00
IF	233	4	4	100.00
IF	253	3	3	100.00
IF	314	2	2	100.00
IF	377	2	2	100.00
IF	389	2	2	100.00
IF	445	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	108	(((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T7

	LineNo.	Expression
-1-:	293	((vld_rd_rsp & (~d_error))) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	299	((vld_rd_rsp && reqfifo_rdata.error)) ? 
-2-:	299	(vld_rd_rsp) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T4,T7,T17
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	344	(tl_i_int.a_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	467	(((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	94	if ((!rst_ni))
-2-:	96	if ((intg_error || rsp_fifo_error))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T19,T20
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	233	if (reqfifo_rvalid)
-2-:	234	if (reqfifo_rdata.error)
-3-:	237	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T98,T99,T100
1	0	1	Covered	T4,T7,T17
1	0	0	Covered	T20
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	253	if (reqfifo_rvalid)
-2-:	254	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T4,T7,T17
1	0	Covered	T19,T20
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	314	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	377	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	389	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	445	if ((|sramreqfifo_rdata.mask))

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T17
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tl_adapter_eflash

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AddrOutKnown_A	362500815	361744231	0	0
DataIntgOptions_A	873	873	0	0
ReqOutKnown_A	362500815	361744231	0	0
SramDwHasByteGranularity_A	873	873	0	0
SramDwIsMultipleOfTlulWidth_A	873	873	0	0
TlOutKnownIfFifoKnown_A	362500815	361744231	0	0
TlOutValidKnown_A	362500815	361744231	0	0
WdataOutKnown_A	362500815	361744231	0	0
WeOutKnown_A	362500815	361744231	0	0
WmaskOutKnown_A	362500815	361744231	0	0
adapterNoReadOrWrite	873	873	0	0
rvalidHighReqFifoEmpty	362500815	3437551	0	0
rvalidHighWhenRspFifoFull	362500815	3437551	0	0

AddrOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362500815	361744231	0	0
T1	1459	1366	0	0
T2	45397	44360	0	0
T3	292693	292603	0	0
T4	20760	20572	0	0
T6	758752	758652	0	0
T7	339479	339428	0	0
T11	1954	1857	0	0
T15	2395	2334	0	0
T17	70192	70127	0	0
T25	1050	962	0	0

DataIntgOptions_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	873	873	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T25	1	1	0	0

ReqOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362500815	361744231	0	0
T1	1459	1366	0	0
T2	45397	44360	0	0
T3	292693	292603	0	0
T4	20760	20572	0	0
T6	758752	758652	0	0
T7	339479	339428	0	0
T11	1954	1857	0	0
T15	2395	2334	0	0
T17	70192	70127	0	0
T25	1050	962	0	0

SramDwHasByteGranularity_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	873	873	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T25	1	1	0	0

SramDwIsMultipleOfTlulWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	873	873	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T25	1	1	0	0

TlOutKnownIfFifoKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362500815	361744231	0	0
T1	1459	1366	0	0
T2	45397	44360	0	0
T3	292693	292603	0	0
T4	20760	20572	0	0
T6	758752	758652	0	0
T7	339479	339428	0	0
T11	1954	1857	0	0
T15	2395	2334	0	0
T17	70192	70127	0	0
T25	1050	962	0	0

TlOutValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362500815	361744231	0	0
T1	1459	1366	0	0
T2	45397	44360	0	0
T3	292693	292603	0	0
T4	20760	20572	0	0
T6	758752	758652	0	0
T7	339479	339428	0	0
T11	1954	1857	0	0
T15	2395	2334	0	0
T17	70192	70127	0	0
T25	1050	962	0	0

WdataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362500815	361744231	0	0
T1	1459	1366	0	0
T2	45397	44360	0	0
T3	292693	292603	0	0
T4	20760	20572	0	0
T6	758752	758652	0	0
T7	339479	339428	0	0
T11	1954	1857	0	0
T15	2395	2334	0	0
T17	70192	70127	0	0
T25	1050	962	0	0

WeOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362500815	361744231	0	0
T1	1459	1366	0	0
T2	45397	44360	0	0
T3	292693	292603	0	0
T4	20760	20572	0	0
T6	758752	758652	0	0
T7	339479	339428	0	0
T11	1954	1857	0	0
T15	2395	2334	0	0
T17	70192	70127	0	0
T25	1050	962	0	0

WmaskOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362500815	361744231	0	0
T1	1459	1366	0	0
T2	45397	44360	0	0
T3	292693	292603	0	0
T4	20760	20572	0	0
T6	758752	758652	0	0
T7	339479	339428	0	0
T11	1954	1857	0	0
T15	2395	2334	0	0
T17	70192	70127	0	0
T25	1050	962	0	0

adapterNoReadOrWrite

Name	Attempts	Real Successes	Failures	Incomplete
Total	873	873	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T25	1	1	0	0

rvalidHighReqFifoEmpty

Name	Attempts	Real Successes	Failures	Incomplete
Total	362500815	3437551	0	0
T4	20760	131	0	0
T5	816192	16363	0	0
T6	758752	0	0	0
T7	339479	41473	0	0
T11	1954	0	0	0
T13	0	16399	0	0
T14	0	16556	0	0
T15	2395	0	0	0
T16	2860	0	0	0
T17	70192	16501	0	0
T21	3780	0	0	0
T33	2155	0	0	0
T75	0	8	0	0
T84	0	16965	0	0
T85	0	166	0	0
T86	0	53	0	0

rvalidHighWhenRspFifoFull

Name	Attempts	Real Successes	Failures	Incomplete
Total	362500815	3437551	0	0
T4	20760	131	0	0
T5	816192	16363	0	0
T6	758752	0	0	0
T7	339479	41473	0	0
T11	1954	0	0	0
T13	0	16399	0	0
T14	0	16556	0	0
T15	2395	0	0	0
T16	2860	0	0	0
T17	70192	16501	0	0
T21	3780	0	0	0
T33	2155	0	0	0
T75	0	8	0	0
T84	0	16965	0	0
T85	0	166	0	0
T86	0	53	0	0