Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T7,T17

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T7,T17
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T7,T17
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T7,T17

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T7,T17
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T7,T17
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T7,T17

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T7,T17

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1450003260	1446976924	0	0
CheckNGreaterZero_A	3492	3492	0	0
GntImpliesReady_A	1450003260	355019189	0	0
GntImpliesValid_A	1450003260	355019189	0	0
GrantKnown_A	1450003260	1446976924	0	0
IdxKnown_A	1450003260	1446976924	0	0
IndexIsCorrect_A	1450003260	355019189	0	0
NoReadyValidNoGrant_A	1450003260	172006721	0	0
Priority_A	1450003260	377410448	0	0
ReadyAndValidImplyGrant_A	1450003260	355019189	0	0
ReqAndReadyImplyGrant_A	1450003260	355019189	0	0
ReqImpliesValid_A	1450003260	377410448	0	0
ValidKnown_A	1450003260	1446976924	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1450003260	1446976924	0	0
T1	5836	5464	0	0
T2	181588	177440	0	0
T3	1170772	1170412	0	0
T4	83040	82288	0	0
T6	3035008	3034608	0	0
T7	1357916	1357712	0	0
T11	7816	7428	0	0
T15	9580	9336	0	0
T17	280768	280508	0	0
T25	4200	3848	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3492	3492	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T6	4	4	0	0
T7	4	4	0	0
T11	4	4	0	0
T15	4	4	0	0
T17	4	4	0	0
T25	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1450003260	355019189	0	0
T1	2918	64	0	0
T2	181588	57992	0	0
T3	1170772	508150	0	0
T4	83040	1824	0	0
T5	0	25468	0	0
T6	3035008	1499628	0	0
T7	1357916	436934	0	0
T11	7816	336	0	0
T15	9580	734	0	0
T17	280768	51216	0	0
T25	4200	64	0	0
T33	4310	676	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1450003260	355019189	0	0
T1	2918	64	0	0
T2	181588	57992	0	0
T3	1170772	508150	0	0
T4	83040	1824	0	0
T5	0	25468	0	0
T6	3035008	1499628	0	0
T7	1357916	436934	0	0
T11	7816	336	0	0
T15	9580	734	0	0
T17	280768	51216	0	0
T25	4200	64	0	0
T33	4310	676	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1450003260	1446976924	0	0
T1	5836	5464	0	0
T2	181588	177440	0	0
T3	1170772	1170412	0	0
T4	83040	82288	0	0
T6	3035008	3034608	0	0
T7	1357916	1357712	0	0
T11	7816	7428	0	0
T15	9580	9336	0	0
T17	280768	280508	0	0
T25	4200	3848	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1450003260	1446976924	0	0
T1	5836	5464	0	0
T2	181588	177440	0	0
T3	1170772	1170412	0	0
T4	83040	82288	0	0
T6	3035008	3034608	0	0
T7	1357916	1357712	0	0
T11	7816	7428	0	0
T15	9580	9336	0	0
T17	280768	280508	0	0
T25	4200	3848	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1450003260	355019189	0	0
T1	2918	64	0	0
T2	181588	57992	0	0
T3	1170772	508150	0	0
T4	83040	1824	0	0
T5	0	25468	0	0
T6	3035008	1499628	0	0
T7	1357916	436934	0	0
T11	7816	336	0	0
T15	9580	734	0	0
T17	280768	51216	0	0
T25	4200	64	0	0
T33	4310	676	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1450003260	172006721	0	0
T1	2918	256	0	0
T2	90794	256	0	0
T3	585386	256	0	0
T4	83040	1250	0	0
T5	1632384	841488	0	0
T6	3035008	2548	0	0
T7	1357916	179852	0	0
T11	7816	326	0	0
T13	0	88002	0	0
T15	9580	290	0	0
T16	5720	0	0	0
T17	280768	66362	0	0
T21	7560	0	0	0
T22	0	1048576	0	0
T24	0	1048576	0	0
T25	2100	256	0	0
T33	4310	0	0	0
T39	0	3468	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1450003260	377410448	0	0
T1	2918	64	0	0
T2	181588	57992	0	0
T3	1170772	508150	0	0
T4	83040	2104	0	0
T5	0	256468	0	0
T6	3035008	1499628	0	0
T7	1357916	530438	0	0
T11	7816	336	0	0
T15	9580	734	0	0
T17	280768	81098	0	0
T25	4200	64	0	0
T33	4310	676	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1450003260	355019189	0	0
T1	2918	64	0	0
T2	181588	57992	0	0
T3	1170772	508150	0	0
T4	83040	1824	0	0
T5	0	25468	0	0
T6	3035008	1499628	0	0
T7	1357916	436934	0	0
T11	7816	336	0	0
T15	9580	734	0	0
T17	280768	51216	0	0
T25	4200	64	0	0
T33	4310	676	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1450003260	355019189	0	0
T1	2918	64	0	0
T2	181588	57992	0	0
T3	1170772	508150	0	0
T4	83040	1824	0	0
T5	0	25468	0	0
T6	3035008	1499628	0	0
T7	1357916	436934	0	0
T11	7816	336	0	0
T15	9580	734	0	0
T17	280768	51216	0	0
T25	4200	64	0	0
T33	4310	676	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1450003260	377410448	0	0
T1	2918	64	0	0
T2	181588	57992	0	0
T3	1170772	508150	0	0
T4	83040	2104	0	0
T5	0	256468	0	0
T6	3035008	1499628	0	0
T7	1357916	530438	0	0
T11	7816	336	0	0
T15	9580	734	0	0
T17	280768	81098	0	0
T25	4200	64	0	0
T33	4310	676	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1450003260	1446976924	0	0
T1	5836	5464	0	0
T2	181588	177440	0	0
T3	1170772	1170412	0	0
T4	83040	82288	0	0
T6	3035008	3034608	0	0
T7	1357916	1357712	0	0
T11	7816	7428	0	0
T15	9580	9336	0	0
T17	280768	280508	0	0
T25	4200	3848	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T7,T17

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T7,T17
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T7,T17
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T7,T17

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T7,T17
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T7,T17
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T7,T17

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T7,T17

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	362500815	361744231	0	0
CheckNGreaterZero_A	873	873	0	0
GntImpliesReady_A	362500815	94116875	0	0
GntImpliesValid_A	362500815	94116875	0	0
GrantKnown_A	362500815	361744231	0	0
IdxKnown_A	362500815	361744231	0	0
IndexIsCorrect_A	362500815	94116875	0	0
NoReadyValidNoGrant_A	362500815	45014570	0	0
Priority_A	362500815	99992260	0	0
ReadyAndValidImplyGrant_A	362500815	94116875	0	0
ReqAndReadyImplyGrant_A	362500815	94116875	0	0
ReqImpliesValid_A	362500815	99992260	0	0
ValidKnown_A	362500815	361744231	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362500815	361744231	0	0
T1	1459	1366	0	0
T2	45397	44360	0	0
T3	292693	292603	0	0
T4	20760	20572	0	0
T6	758752	758652	0	0
T7	339479	339428	0	0
T11	1954	1857	0	0
T15	2395	2334	0	0
T17	70192	70127	0	0
T25	1050	962	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	873	873	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T25	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362500815	94116875	0	0
T1	1459	32	0	0
T2	45397	13858	0	0
T3	292693	139086	0	0
T4	20760	568	0	0
T6	758752	276484	0	0
T7	339479	117567	0	0
T11	1954	146	0	0
T15	2395	43	0	0
T17	70192	14113	0	0
T25	1050	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362500815	94116875	0	0
T1	1459	32	0	0
T2	45397	13858	0	0
T3	292693	139086	0	0
T4	20760	568	0	0
T6	758752	276484	0	0
T7	339479	117567	0	0
T11	1954	146	0	0
T15	2395	43	0	0
T17	70192	14113	0	0
T25	1050	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362500815	361744231	0	0
T1	1459	1366	0	0
T2	45397	44360	0	0
T3	292693	292603	0	0
T4	20760	20572	0	0
T6	758752	758652	0	0
T7	339479	339428	0	0
T11	1954	1857	0	0
T15	2395	2334	0	0
T17	70192	70127	0	0
T25	1050	962	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362500815	361744231	0	0
T1	1459	1366	0	0
T2	45397	44360	0	0
T3	292693	292603	0	0
T4	20760	20572	0	0
T6	758752	758652	0	0
T7	339479	339428	0	0
T11	1954	1857	0	0
T15	2395	2334	0	0
T17	70192	70127	0	0
T25	1050	962	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362500815	94116875	0	0
T1	1459	32	0	0
T2	45397	13858	0	0
T3	292693	139086	0	0
T4	20760	568	0	0
T6	758752	276484	0	0
T7	339479	117567	0	0
T11	1954	146	0	0
T15	2395	43	0	0
T17	70192	14113	0	0
T25	1050	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362500815	45014570	0	0
T1	1459	128	0	0
T2	45397	128	0	0
T3	292693	128	0	0
T4	20760	477	0	0
T6	758752	558	0	0
T7	339479	43786	0	0
T11	1954	128	0	0
T15	2395	145	0	0
T17	70192	18372	0	0
T25	1050	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362500815	99992260	0	0
T1	1459	32	0	0
T2	45397	13858	0	0
T3	292693	139086	0	0
T4	20760	598	0	0
T6	758752	276484	0	0
T7	339479	136538	0	0
T11	1954	146	0	0
T15	2395	43	0	0
T17	70192	22037	0	0
T25	1050	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362500815	94116875	0	0
T1	1459	32	0	0
T2	45397	13858	0	0
T3	292693	139086	0	0
T4	20760	568	0	0
T6	758752	276484	0	0
T7	339479	117567	0	0
T11	1954	146	0	0
T15	2395	43	0	0
T17	70192	14113	0	0
T25	1050	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362500815	94116875	0	0
T1	1459	32	0	0
T2	45397	13858	0	0
T3	292693	139086	0	0
T4	20760	568	0	0
T6	758752	276484	0	0
T7	339479	117567	0	0
T11	1954	146	0	0
T15	2395	43	0	0
T17	70192	14113	0	0
T25	1050	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362500815	99992260	0	0
T1	1459	32	0	0
T2	45397	13858	0	0
T3	292693	139086	0	0
T4	20760	598	0	0
T6	758752	276484	0	0
T7	339479	136538	0	0
T11	1954	146	0	0
T15	2395	43	0	0
T17	70192	22037	0	0
T25	1050	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362500815	361744231	0	0
T1	1459	1366	0	0
T2	45397	44360	0	0
T3	292693	292603	0	0
T4	20760	20572	0	0
T6	758752	758652	0	0
T7	339479	339428	0	0
T11	1954	1857	0	0
T15	2395	2334	0	0
T17	70192	70127	0	0
T25	1050	962	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T7,T17

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T7,T17
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T7,T17
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T7,T17

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T7,T17
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T7,T17
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T7,T17

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T7,T17

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	362500815	361744231	0	0
CheckNGreaterZero_A	873	873	0	0
GntImpliesReady_A	362500815	94116942	0	0
GntImpliesValid_A	362500815	94116942	0	0
GrantKnown_A	362500815	361744231	0	0
IdxKnown_A	362500815	361744231	0	0
IndexIsCorrect_A	362500815	94116942	0	0
NoReadyValidNoGrant_A	362500815	45014564	0	0
Priority_A	362500815	99992333	0	0
ReadyAndValidImplyGrant_A	362500815	94116942	0	0
ReqAndReadyImplyGrant_A	362500815	94116942	0	0
ReqImpliesValid_A	362500815	99992333	0	0
ValidKnown_A	362500815	361744231	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362500815	361744231	0	0
T1	1459	1366	0	0
T2	45397	44360	0	0
T3	292693	292603	0	0
T4	20760	20572	0	0
T6	758752	758652	0	0
T7	339479	339428	0	0
T11	1954	1857	0	0
T15	2395	2334	0	0
T17	70192	70127	0	0
T25	1050	962	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	873	873	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T25	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362500815	94116942	0	0
T1	1459	32	0	0
T2	45397	13858	0	0
T3	292693	139086	0	0
T4	20760	568	0	0
T6	758752	276484	0	0
T7	339479	117567	0	0
T11	1954	146	0	0
T15	2395	43	0	0
T17	70192	14113	0	0
T25	1050	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362500815	94116942	0	0
T1	1459	32	0	0
T2	45397	13858	0	0
T3	292693	139086	0	0
T4	20760	568	0	0
T6	758752	276484	0	0
T7	339479	117567	0	0
T11	1954	146	0	0
T15	2395	43	0	0
T17	70192	14113	0	0
T25	1050	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362500815	361744231	0	0
T1	1459	1366	0	0
T2	45397	44360	0	0
T3	292693	292603	0	0
T4	20760	20572	0	0
T6	758752	758652	0	0
T7	339479	339428	0	0
T11	1954	1857	0	0
T15	2395	2334	0	0
T17	70192	70127	0	0
T25	1050	962	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362500815	361744231	0	0
T1	1459	1366	0	0
T2	45397	44360	0	0
T3	292693	292603	0	0
T4	20760	20572	0	0
T6	758752	758652	0	0
T7	339479	339428	0	0
T11	1954	1857	0	0
T15	2395	2334	0	0
T17	70192	70127	0	0
T25	1050	962	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362500815	94116942	0	0
T1	1459	32	0	0
T2	45397	13858	0	0
T3	292693	139086	0	0
T4	20760	568	0	0
T6	758752	276484	0	0
T7	339479	117567	0	0
T11	1954	146	0	0
T15	2395	43	0	0
T17	70192	14113	0	0
T25	1050	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362500815	45014564	0	0
T1	1459	128	0	0
T2	45397	128	0	0
T3	292693	128	0	0
T4	20760	477	0	0
T6	758752	558	0	0
T7	339479	43786	0	0
T11	1954	128	0	0
T15	2395	145	0	0
T17	70192	18372	0	0
T25	1050	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362500815	99992333	0	0
T1	1459	32	0	0
T2	45397	13858	0	0
T3	292693	139086	0	0
T4	20760	598	0	0
T6	758752	276484	0	0
T7	339479	136538	0	0
T11	1954	146	0	0
T15	2395	43	0	0
T17	70192	22037	0	0
T25	1050	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362500815	94116942	0	0
T1	1459	32	0	0
T2	45397	13858	0	0
T3	292693	139086	0	0
T4	20760	568	0	0
T6	758752	276484	0	0
T7	339479	117567	0	0
T11	1954	146	0	0
T15	2395	43	0	0
T17	70192	14113	0	0
T25	1050	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362500815	94116942	0	0
T1	1459	32	0	0
T2	45397	13858	0	0
T3	292693	139086	0	0
T4	20760	568	0	0
T6	758752	276484	0	0
T7	339479	117567	0	0
T11	1954	146	0	0
T15	2395	43	0	0
T17	70192	14113	0	0
T25	1050	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362500815	99992333	0	0
T1	1459	32	0	0
T2	45397	13858	0	0
T3	292693	139086	0	0
T4	20760	598	0	0
T6	758752	276484	0	0
T7	339479	136538	0	0
T11	1954	146	0	0
T15	2395	43	0	0
T17	70192	22037	0	0
T25	1050	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362500815	361744231	0	0
T1	1459	1366	0	0
T2	45397	44360	0	0
T3	292693	292603	0	0
T4	20760	20572	0	0
T6	758752	758652	0	0
T7	339479	339428	0	0
T11	1954	1857	0	0
T15	2395	2334	0	0
T17	70192	70127	0	0
T25	1050	962	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T4,T7,T17

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T7,T17
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T7,T17
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T17
1	0	Covered	T2,T3,T4
1	1	Covered	T4,T7,T17

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T7,T17
1	1	Covered	T2,T3,T4

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T7,T17
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T7,T17

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T7,T17

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	362500815	361744231	0	0
CheckNGreaterZero_A	873	873	0	0
GntImpliesReady_A	362500815	83392654	0	0
GntImpliesValid_A	362500815	83392654	0	0
GrantKnown_A	362500815	361744231	0	0
IdxKnown_A	362500815	361744231	0	0
IndexIsCorrect_A	362500815	83392654	0	0
NoReadyValidNoGrant_A	362500815	40988799	0	0
Priority_A	362500815	88712890	0	0
ReadyAndValidImplyGrant_A	362500815	83392654	0	0
ReqAndReadyImplyGrant_A	362500815	83392654	0	0
ReqImpliesValid_A	362500815	88712890	0	0
ValidKnown_A	362500815	361744231	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362500815	361744231	0	0
T1	1459	1366	0	0
T2	45397	44360	0	0
T3	292693	292603	0	0
T4	20760	20572	0	0
T6	758752	758652	0	0
T7	339479	339428	0	0
T11	1954	1857	0	0
T15	2395	2334	0	0
T17	70192	70127	0	0
T25	1050	962	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	873	873	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T25	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362500815	83392654	0	0
T2	45397	15138	0	0
T3	292693	114989	0	0
T4	20760	344	0	0
T5	0	12734	0	0
T6	758752	473330	0	0
T7	339479	100900	0	0
T11	1954	22	0	0
T15	2395	324	0	0
T17	70192	11495	0	0
T25	1050	0	0	0
T33	2155	338	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362500815	83392654	0	0
T2	45397	15138	0	0
T3	292693	114989	0	0
T4	20760	344	0	0
T5	0	12734	0	0
T6	758752	473330	0	0
T7	339479	100900	0	0
T11	1954	22	0	0
T15	2395	324	0	0
T17	70192	11495	0	0
T25	1050	0	0	0
T33	2155	338	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362500815	361744231	0	0
T1	1459	1366	0	0
T2	45397	44360	0	0
T3	292693	292603	0	0
T4	20760	20572	0	0
T6	758752	758652	0	0
T7	339479	339428	0	0
T11	1954	1857	0	0
T15	2395	2334	0	0
T17	70192	70127	0	0
T25	1050	962	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362500815	361744231	0	0
T1	1459	1366	0	0
T2	45397	44360	0	0
T3	292693	292603	0	0
T4	20760	20572	0	0
T6	758752	758652	0	0
T7	339479	339428	0	0
T11	1954	1857	0	0
T15	2395	2334	0	0
T17	70192	70127	0	0
T25	1050	962	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362500815	83392654	0	0
T2	45397	15138	0	0
T3	292693	114989	0	0
T4	20760	344	0	0
T5	0	12734	0	0
T6	758752	473330	0	0
T7	339479	100900	0	0
T11	1954	22	0	0
T15	2395	324	0	0
T17	70192	11495	0	0
T25	1050	0	0	0
T33	2155	338	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362500815	40988799	0	0
T4	20760	148	0	0
T5	816192	420744	0	0
T6	758752	716	0	0
T7	339479	46140	0	0
T11	1954	35	0	0
T13	0	44001	0	0
T15	2395	0	0	0
T16	2860	0	0	0
T17	70192	14809	0	0
T21	3780	0	0	0
T22	0	524288	0	0
T24	0	524288	0	0
T33	2155	0	0	0
T39	0	1734	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362500815	88712890	0	0
T2	45397	15138	0	0
T3	292693	114989	0	0
T4	20760	454	0	0
T5	0	128234	0	0
T6	758752	473330	0	0
T7	339479	128681	0	0
T11	1954	22	0	0
T15	2395	324	0	0
T17	70192	18512	0	0
T25	1050	0	0	0
T33	2155	338	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362500815	83392654	0	0
T2	45397	15138	0	0
T3	292693	114989	0	0
T4	20760	344	0	0
T5	0	12734	0	0
T6	758752	473330	0	0
T7	339479	100900	0	0
T11	1954	22	0	0
T15	2395	324	0	0
T17	70192	11495	0	0
T25	1050	0	0	0
T33	2155	338	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362500815	83392654	0	0
T2	45397	15138	0	0
T3	292693	114989	0	0
T4	20760	344	0	0
T5	0	12734	0	0
T6	758752	473330	0	0
T7	339479	100900	0	0
T11	1954	22	0	0
T15	2395	324	0	0
T17	70192	11495	0	0
T25	1050	0	0	0
T33	2155	338	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362500815	88712890	0	0
T2	45397	15138	0	0
T3	292693	114989	0	0
T4	20760	454	0	0
T5	0	128234	0	0
T6	758752	473330	0	0
T7	339479	128681	0	0
T11	1954	22	0	0
T15	2395	324	0	0
T17	70192	18512	0	0
T25	1050	0	0	0
T33	2155	338	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362500815	361744231	0	0
T1	1459	1366	0	0
T2	45397	44360	0	0
T3	292693	292603	0	0
T4	20760	20572	0	0
T6	758752	758652	0	0
T7	339479	339428	0	0
T11	1954	1857	0	0
T15	2395	2334	0	0
T17	70192	70127	0	0
T25	1050	962	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T4,T7,T17

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T7,T17
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T7,T17
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T17
1	0	Covered	T2,T3,T4
1	1	Covered	T4,T7,T17

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T7,T17
1	1	Covered	T2,T3,T4

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T7,T17
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T7,T17

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T7,T17

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	362500815	361744231	0	0
CheckNGreaterZero_A	873	873	0	0
GntImpliesReady_A	362500815	83392718	0	0
GntImpliesValid_A	362500815	83392718	0	0
GrantKnown_A	362500815	361744231	0	0
IdxKnown_A	362500815	361744231	0	0
IndexIsCorrect_A	362500815	83392718	0	0
NoReadyValidNoGrant_A	362500815	40988788	0	0
Priority_A	362500815	88712965	0	0
ReadyAndValidImplyGrant_A	362500815	83392718	0	0
ReqAndReadyImplyGrant_A	362500815	83392718	0	0
ReqImpliesValid_A	362500815	88712965	0	0
ValidKnown_A	362500815	361744231	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362500815	361744231	0	0
T1	1459	1366	0	0
T2	45397	44360	0	0
T3	292693	292603	0	0
T4	20760	20572	0	0
T6	758752	758652	0	0
T7	339479	339428	0	0
T11	1954	1857	0	0
T15	2395	2334	0	0
T17	70192	70127	0	0
T25	1050	962	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	873	873	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T15	1	1	0	0
T17	1	1	0	0
T25	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362500815	83392718	0	0
T2	45397	15138	0	0
T3	292693	114989	0	0
T4	20760	344	0	0
T5	0	12734	0	0
T6	758752	473330	0	0
T7	339479	100900	0	0
T11	1954	22	0	0
T15	2395	324	0	0
T17	70192	11495	0	0
T25	1050	0	0	0
T33	2155	338	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362500815	83392718	0	0
T2	45397	15138	0	0
T3	292693	114989	0	0
T4	20760	344	0	0
T5	0	12734	0	0
T6	758752	473330	0	0
T7	339479	100900	0	0
T11	1954	22	0	0
T15	2395	324	0	0
T17	70192	11495	0	0
T25	1050	0	0	0
T33	2155	338	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362500815	361744231	0	0
T1	1459	1366	0	0
T2	45397	44360	0	0
T3	292693	292603	0	0
T4	20760	20572	0	0
T6	758752	758652	0	0
T7	339479	339428	0	0
T11	1954	1857	0	0
T15	2395	2334	0	0
T17	70192	70127	0	0
T25	1050	962	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362500815	361744231	0	0
T1	1459	1366	0	0
T2	45397	44360	0	0
T3	292693	292603	0	0
T4	20760	20572	0	0
T6	758752	758652	0	0
T7	339479	339428	0	0
T11	1954	1857	0	0
T15	2395	2334	0	0
T17	70192	70127	0	0
T25	1050	962	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362500815	83392718	0	0
T2	45397	15138	0	0
T3	292693	114989	0	0
T4	20760	344	0	0
T5	0	12734	0	0
T6	758752	473330	0	0
T7	339479	100900	0	0
T11	1954	22	0	0
T15	2395	324	0	0
T17	70192	11495	0	0
T25	1050	0	0	0
T33	2155	338	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362500815	40988788	0	0
T4	20760	148	0	0
T5	816192	420744	0	0
T6	758752	716	0	0
T7	339479	46140	0	0
T11	1954	35	0	0
T13	0	44001	0	0
T15	2395	0	0	0
T16	2860	0	0	0
T17	70192	14809	0	0
T21	3780	0	0	0
T22	0	524288	0	0
T24	0	524288	0	0
T33	2155	0	0	0
T39	0	1734	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362500815	88712965	0	0
T2	45397	15138	0	0
T3	292693	114989	0	0
T4	20760	454	0	0
T5	0	128234	0	0
T6	758752	473330	0	0
T7	339479	128681	0	0
T11	1954	22	0	0
T15	2395	324	0	0
T17	70192	18512	0	0
T25	1050	0	0	0
T33	2155	338	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362500815	83392718	0	0
T2	45397	15138	0	0
T3	292693	114989	0	0
T4	20760	344	0	0
T5	0	12734	0	0
T6	758752	473330	0	0
T7	339479	100900	0	0
T11	1954	22	0	0
T15	2395	324	0	0
T17	70192	11495	0	0
T25	1050	0	0	0
T33	2155	338	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362500815	83392718	0	0
T2	45397	15138	0	0
T3	292693	114989	0	0
T4	20760	344	0	0
T5	0	12734	0	0
T6	758752	473330	0	0
T7	339479	100900	0	0
T11	1954	22	0	0
T15	2395	324	0	0
T17	70192	11495	0	0
T25	1050	0	0	0
T33	2155	338	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362500815	88712965	0	0
T2	45397	15138	0	0
T3	292693	114989	0	0
T4	20760	454	0	0
T5	0	128234	0	0
T6	758752	473330	0	0
T7	339479	128681	0	0
T11	1954	22	0	0
T15	2395	324	0	0
T17	70192	18512	0	0
T25	1050	0	0	0
T33	2155	338	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	362500815	361744231	0	0
T1	1459	1366	0	0
T2	45397	44360	0	0
T3	292693	292603	0	0
T4	20760	20572	0	0
T6	758752	758652	0	0
T7	339479	339428	0	0
T11	1954	1857	0	0
T15	2395	2334	0	0
T17	70192	70127	0	0
T25	1050	962	0	0