GPIO Simulation Results

Friday May 19 2023 07:05:15 UTC

GitHub Revision: `30db5a999`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2235272161

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.460s	315.319us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.410s	142.616us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.670s	57.101us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.650s	18.294us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	3.360s	2.637ms	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.910s	66.728us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.700s	72.158us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.650s	18.294us	20	20	100.00
		gpio_csr_aliasing	0.910s	66.728us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.460s	326.133us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.330s	115.754us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	1.010s	31.448us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.500s	210.652us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.600s	700.149us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	3.620s	366.926us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	29.280s	8.846ms	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	6.850s	1.792ms	50	50	100.00
V2	full_random	gpio_full_random	1.220s	98.379us	50	50	100.00
V2	stress_all	gpio_stress_all	3.934m	21.344ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.630s	73.580us	50	50	100.00
V2	intr_test	gpio_intr_test	0.620s	20.807us	22	50	44.00
V2	tl_d_oob_addr_access	gpio_tl_errors	2.830s	273.833us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	2.830s	273.833us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.650s	18.294us	20	20	100.00
		gpio_same_csr_outstanding	0.880s	30.967us	20	20	100.00
		gpio_csr_aliasing	0.910s	66.728us	5	5	100.00
		gpio_csr_hw_reset	0.670s	57.101us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.650s	18.294us	20	20	100.00
		gpio_same_csr_outstanding	0.880s	30.967us	20	20	100.00
		gpio_csr_aliasing	0.910s	66.728us	5	5	100.00
		gpio_csr_hw_reset	0.670s	57.101us	5	5	100.00
V2		TOTAL			612	640	95.62
V2S	tl_intg_err	gpio_tl_intg_err	1.530s	1.387ms	20	20	100.00
		gpio_sec_cm	0.940s	352.378us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.530s	1.387ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	37.428m	599.644ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			842	870	96.78

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	14	14	13	92.86
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.61	99.07	99.10	100.00	--	99.80	99.68	100.00

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:455) [gpio_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRgpio_reg_block.intr_state

has 28 failures:

Test gpio_intr_test has 28 failures.

0.gpio_intr_test.683301806
Line 222, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/0.gpio_intr_test/latest/run.log

  UVM_ERROR @   4361168 ps: (cip_base_vseq.sv:455) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 4240694952 [0xfcc3dea8]) when reading the intr CSRgpio_reg_block.intr_state
  UVM_INFO @   4361168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.gpio_intr_test.4145658798
Line 222, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/3.gpio_intr_test/latest/run.log

  UVM_ERROR @   1444729 ps: (cip_base_vseq.sv:455) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 4219076586 [0xfb79ffea]) when reading the intr CSRgpio_reg_block.intr_state
  UVM_INFO @   1444729 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 26 more failures.