V1 |
smoke |
gpio_smoke |
1.420s |
168.739us |
50 |
50 |
100.00 |
|
|
gpio_smoke_no_pullup_pulldown |
1.450s |
998.427us |
50 |
50 |
100.00 |
|
|
gpio_smoke_en_cdc_prim |
1.420s |
241.740us |
50 |
50 |
100.00 |
|
|
gpio_smoke_no_pullup_pulldown_en_cdc_prim |
1.440s |
103.976us |
50 |
50 |
100.00 |
V1 |
csr_hw_reset |
gpio_csr_hw_reset |
0.680s |
20.416us |
5 |
5 |
100.00 |
V1 |
csr_rw |
gpio_csr_rw |
0.670s |
28.085us |
20 |
20 |
100.00 |
V1 |
csr_bit_bash |
gpio_csr_bit_bash |
3.370s |
1.495ms |
5 |
5 |
100.00 |
V1 |
csr_aliasing |
gpio_csr_aliasing |
0.830s |
66.718us |
5 |
5 |
100.00 |
V1 |
csr_mem_rw_with_rand_reset |
gpio_csr_mem_rw_with_rand_reset |
1.330s |
360.038us |
20 |
20 |
100.00 |
V1 |
regwen_csr_and_corresponding_lockable_csr |
gpio_csr_rw |
0.670s |
28.085us |
20 |
20 |
100.00 |
|
|
gpio_csr_aliasing |
0.830s |
66.718us |
5 |
5 |
100.00 |
V1 |
|
TOTAL |
|
|
255 |
255 |
100.00 |
V2 |
direct_and_masked_out |
gpio_random_dout_din |
1.310s |
678.286us |
50 |
50 |
100.00 |
|
|
gpio_random_dout_din_no_pullup_pulldown |
1.350s |
109.754us |
50 |
50 |
100.00 |
V2 |
out_in_regs_read_write |
gpio_dout_din_regs_random_rw |
0.950s |
48.848us |
50 |
50 |
100.00 |
V2 |
gpio_interrupt_programming |
gpio_intr_rand_pgm |
1.470s |
248.144us |
50 |
50 |
100.00 |
V2 |
random_interrupt_trigger |
gpio_rand_intr_trigger |
3.840s |
122.463us |
50 |
50 |
100.00 |
V2 |
interrupt_and_noise_filter |
gpio_intr_with_filter_rand_intr_event |
3.850s |
319.770us |
50 |
50 |
100.00 |
V2 |
noise_filter_stress |
gpio_filter_stress |
27.400s |
528.679us |
50 |
50 |
100.00 |
V2 |
regs_long_reads_and_writes |
gpio_random_long_reg_writes_reg_reads |
6.610s |
5.124ms |
50 |
50 |
100.00 |
V2 |
full_random |
gpio_full_random |
1.080s |
353.860us |
50 |
50 |
100.00 |
V2 |
stress_all |
gpio_stress_all |
3.824m |
40.887ms |
50 |
50 |
100.00 |
V2 |
alert_test |
gpio_alert_test |
0.640s |
38.172us |
50 |
50 |
100.00 |
V2 |
intr_test |
gpio_intr_test |
0.670s |
12.921us |
50 |
50 |
100.00 |
V2 |
tl_d_oob_addr_access |
gpio_tl_errors |
2.920s |
99.432us |
20 |
20 |
100.00 |
V2 |
tl_d_illegal_access |
gpio_tl_errors |
2.920s |
99.432us |
20 |
20 |
100.00 |
V2 |
tl_d_outstanding_access |
gpio_csr_rw |
0.670s |
28.085us |
20 |
20 |
100.00 |
|
|
gpio_same_csr_outstanding |
0.940s |
159.836us |
20 |
20 |
100.00 |
|
|
gpio_csr_aliasing |
0.830s |
66.718us |
5 |
5 |
100.00 |
|
|
gpio_csr_hw_reset |
0.680s |
20.416us |
5 |
5 |
100.00 |
V2 |
tl_d_partial_access |
gpio_csr_rw |
0.670s |
28.085us |
20 |
20 |
100.00 |
|
|
gpio_same_csr_outstanding |
0.940s |
159.836us |
20 |
20 |
100.00 |
|
|
gpio_csr_aliasing |
0.830s |
66.718us |
5 |
5 |
100.00 |
|
|
gpio_csr_hw_reset |
0.680s |
20.416us |
5 |
5 |
100.00 |
V2 |
|
TOTAL |
|
|
640 |
640 |
100.00 |
V2S |
tl_intg_err |
gpio_tl_intg_err |
1.630s |
691.531us |
20 |
20 |
100.00 |
|
|
gpio_sec_cm |
1.010s |
650.251us |
5 |
5 |
100.00 |
V2S |
sec_cm_bus_integrity |
gpio_tl_intg_err |
1.630s |
691.531us |
20 |
20 |
100.00 |
V2S |
|
TOTAL |
|
|
25 |
25 |
100.00 |
V3 |
stress_all_with_rand_reset |
gpio_stress_all_with_rand_reset |
41.919m |
108.994ms |
50 |
50 |
100.00 |
V3 |
|
TOTAL |
|
|
50 |
50 |
100.00 |
|
|
TOTAL |
|
|
970 |
970 |
100.00 |