SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_reg.u_masked_out_lower_mask | 66.67 | 66.67 | |||||
tb.dut.u_reg.u_masked_out_upper_mask | 66.67 | 66.67 | |||||
tb.dut.u_reg.u_masked_oe_lower_mask | 75.00 | 75.00 | |||||
tb.dut.u_reg.u_masked_oe_upper_mask | 75.00 | 75.00 | |||||
tb.dut.u_reg.u_intr_test | 100.00 | 100.00 | |||||
tb.dut.u_reg.u_alert_test | 100.00 | 100.00 | |||||
tb.dut.u_reg.u_direct_out | 100.00 | 100.00 | |||||
tb.dut.u_reg.u_masked_out_lower_data | 100.00 | 100.00 | |||||
tb.dut.u_reg.u_masked_out_upper_data | 100.00 | 100.00 | |||||
tb.dut.u_reg.u_direct_oe | 100.00 | 100.00 | |||||
tb.dut.u_reg.u_masked_oe_lower_data | 100.00 | 100.00 | |||||
tb.dut.u_reg.u_masked_oe_upper_data | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
66.67 | 66.67 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
66.67 | 66.67 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.75 | 100.00 | 99.01 | 100.00 | 100.00 | u_reg |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
66.67 | 66.67 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
66.67 | 66.67 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.75 | 100.00 | 99.01 | 100.00 | 100.00 | u_reg |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
75.00 | 75.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
75.00 | 75.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.75 | 100.00 | 99.01 | 100.00 | 100.00 | u_reg |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
75.00 | 75.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
75.00 | 75.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.75 | 100.00 | 99.01 | 100.00 | 100.00 | u_reg |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.75 | 100.00 | 99.01 | 100.00 | 100.00 | u_reg |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.75 | 100.00 | 99.01 | 100.00 | 100.00 | u_reg |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.75 | 100.00 | 99.01 | 100.00 | 100.00 | u_reg |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.75 | 100.00 | 99.01 | 100.00 | 100.00 | u_reg |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.75 | 100.00 | 99.01 | 100.00 | 100.00 | u_reg |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.75 | 100.00 | 99.01 | 100.00 | 100.00 | u_reg |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.75 | 100.00 | 99.01 | 100.00 | 100.00 | u_reg |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.75 | 100.00 | 99.01 | 100.00 | 100.00 | u_reg |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 5 | 5 | 100.00 | |
CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
25 // between qs and ds 26 1/1 assign ds = d; Tests: T25 T26 T27 27 1/1 assign qs = d; Tests: T25 T26 T27 28 1/1 assign q = wd; Tests: T25 T26 T27 29 1/1 assign qe = we; Tests: T25 T30 T1 30 1/1 assign qre = re; Tests: T25 T30 T1
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 2 | 66.67 | |
CONT_ASSIGN | 26 | 1 | 0 | 0.00 |
CONT_ASSIGN | 27 | 0 | 0 | |
CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 0 | 0 |
25 // between qs and ds 26 0/1 ==> assign ds = d; 27 excluded assign qs = d; Exclude Annotation: [UNR] 28 1/1 assign q = wd; Tests: T25 T26 T27 29 1/1 assign qe = we; Tests: T25 T26 T29 30 unreachable assign qre = re;
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 2 | 66.67 | |
CONT_ASSIGN | 26 | 1 | 0 | 0.00 |
CONT_ASSIGN | 27 | 0 | 0 | |
CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 0 | 0 |
25 // between qs and ds 26 0/1 ==> assign ds = d; 27 excluded assign qs = d; Exclude Annotation: [UNR] 28 1/1 assign q = wd; Tests: T25 T26 T27 29 1/1 assign qe = we; Tests: T25 T26 T29 30 unreachable assign qre = re;
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 3 | 75.00 | |
CONT_ASSIGN | 26 | 1 | 0 | 0.00 |
CONT_ASSIGN | 27 | 0 | 0 | |
CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
25 // between qs and ds 26 0/1 ==> assign ds = d; 27 excluded assign qs = d; Exclude Annotation: [UNR] 28 1/1 assign q = wd; Tests: T25 T26 T27 29 1/1 assign qe = we; Tests: T25 T26 T29 30 1/1 assign qre = re; Tests: T25 T30 T1
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 3 | 75.00 | |
CONT_ASSIGN | 26 | 1 | 0 | 0.00 |
CONT_ASSIGN | 27 | 0 | 0 | |
CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
25 // between qs and ds 26 0/1 ==> assign ds = d; 27 excluded assign qs = d; Exclude Annotation: [UNR] 28 1/1 assign q = wd; Tests: T25 T26 T27 29 1/1 assign qe = we; Tests: T25 T26 T29 30 1/1 assign qre = re; Tests: T25 T1 T14
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 26 | 0 | 0 | |
CONT_ASSIGN | 27 | 0 | 0 | |
CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 0 | 0 |
25 // between qs and ds 26 unreachable assign ds = d; 27 unreachable assign qs = d; 28 1/1 assign q = wd; Tests: T25 T26 T27 29 1/1 assign qe = we; Tests: T30 T1 T19 30 unreachable assign qre = re;
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 26 | 0 | 0 | |
CONT_ASSIGN | 27 | 0 | 0 | |
CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 0 | 0 |
25 // between qs and ds 26 unreachable assign ds = d; 27 unreachable assign qs = d; 28 1/1 assign q = wd; Tests: T25 T26 T27 29 1/1 assign qe = we; Tests: T11 T17 T45 30 unreachable assign qre = re;
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 5 | 5 | 100.00 | |
CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
25 // between qs and ds 26 1/1 assign ds = d; Tests: T25 T26 T27 27 1/1 assign qs = d; Tests: T25 T26 T27 28 1/1 assign q = wd; Tests: T25 T26 T27 29 1/1 assign qe = we; Tests: T25 T26 T27 30 1/1 assign qre = re; Tests: T25 T30 T1
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 5 | 5 | 100.00 | |
CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
25 // between qs and ds 26 1/1 assign ds = d; Tests: T25 T26 T27 27 1/1 assign qs = d; Tests: T25 T26 T27 28 1/1 assign q = wd; Tests: T25 T26 T27 29 1/1 assign qe = we; Tests: T25 T26 T29 30 1/1 assign qre = re; Tests: T25 T1 T14
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 5 | 5 | 100.00 | |
CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
25 // between qs and ds 26 1/1 assign ds = d; Tests: T25 T26 T27 27 1/1 assign qs = d; Tests: T25 T26 T27 28 1/1 assign q = wd; Tests: T25 T26 T27 29 1/1 assign qe = we; Tests: T25 T26 T29 30 1/1 assign qre = re; Tests: T25 T1 T14
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 5 | 5 | 100.00 | |
CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
25 // between qs and ds 26 1/1 assign ds = d; Tests: T25 T26 T27 27 1/1 assign qs = d; Tests: T25 T26 T27 28 1/1 assign q = wd; Tests: T25 T26 T27 29 1/1 assign qe = we; Tests: T25 T26 T27 30 1/1 assign qre = re; Tests: T25 T30 T1
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 5 | 5 | 100.00 | |
CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
25 // between qs and ds 26 1/1 assign ds = d; Tests: T25 T26 T27 27 1/1 assign qs = d; Tests: T25 T26 T27 28 1/1 assign q = wd; Tests: T25 T26 T27 29 1/1 assign qe = we; Tests: T25 T26 T29 30 1/1 assign qre = re; Tests: T25 T30 T1
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 5 | 5 | 100.00 | |
CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
25 // between qs and ds 26 1/1 assign ds = d; Tests: T25 T26 T27 27 1/1 assign qs = d; Tests: T25 T26 T27 28 1/1 assign q = wd; Tests: T25 T26 T27 29 1/1 assign qe = we; Tests: T25 T26 T29 30 1/1 assign qre = re; Tests: T25 T1 T14
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |