HMAC Simulation Results

Saturday May 20 2023 07:05:26 UTC

GitHub Revision: `e3fb01b5e`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2781625531

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	4.560s	406.574us	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	0.760s	39.103us	5	5	100.00
V1	csr_rw	hmac_csr_rw	0.760s	25.694us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	7.990s	203.094us	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	1.910s	420.738us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	7.966m	153.216ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.760s	25.694us	20	20	100.00
		hmac_csr_aliasing	1.910s	420.738us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	1.996m	15.338ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	53.240s	1.561ms	50	50	100.00
V2	test_vectors	hmac_test_sha_vectors	8.462m	46.122ms	47	50	94.00
		hmac_test_hmac_vectors	1.260s	65.159us	50	50	100.00
V2	burst_wr	hmac_burst_wr	1.236m	5.626ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	2.682m	3.105ms	50	50	100.00
V2	error	hmac_error	3.371m	130.544ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	1.326m	57.415ms	50	50	100.00
V2	stress_all	hmac_stress_all	50.795m	266.962ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.630s	37.857us	50	50	100.00
V2	intr_test	hmac_intr_test	0.640s	16.251us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	2.830s	52.465us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	2.830s	52.465us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	0.760s	39.103us	5	5	100.00
		hmac_csr_rw	0.760s	25.694us	20	20	100.00
		hmac_csr_aliasing	1.910s	420.738us	5	5	100.00
		hmac_same_csr_outstanding	1.410s	234.762us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	0.760s	39.103us	5	5	100.00
		hmac_csr_rw	0.760s	25.694us	20	20	100.00
		hmac_csr_aliasing	1.910s	420.738us	5	5	100.00
		hmac_same_csr_outstanding	1.410s	234.762us	20	20	100.00
V2		TOTAL			587	590	99.49
V2S	tl_intg_err	hmac_sec_cm	0.940s	85.654us	5	5	100.00
		hmac_tl_intg_err	2.510s	162.692us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	2.510s	162.692us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	4.560s	406.574us	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	1.531h	369.808ms	191	200	95.50
V3		TOTAL			191	200	95.50
		TOTAL			908	920	98.70

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	13	13	12	92.31
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.57	99.54	98.47	100.00	100.00	99.76	99.49	99.72

Failure Buckets

UVM_ERROR (hmac_base_vseq.sv:37) [hmac_stress_all_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 5 failures:

Test hmac_stress_all_with_rand_reset has 5 failures.

5.hmac_stress_all_with_rand_reset.2383627829
Line 1432, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/5.hmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 96254386209 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_stress_all_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 96254386209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

14.hmac_stress_all_with_rand_reset.1206900580
Line 1236, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/14.hmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 34159055120 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_stress_all_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 34159055120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:

Test hmac_test_sha_vectors has 3 failures.

3.hmac_test_sha_vectors.1509383272
Line 215, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/3.hmac_test_sha_vectors/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.hmac_test_sha_vectors.1591404251
Line 215, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/4.hmac_test_sha_vectors/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (hmac_base_vseq.sv:37) [hmac_datapath_stress_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:
- Test hmac_stress_all_with_rand_reset has 1 failures.
  - 71.hmac_stress_all_with_rand_reset.3446120259
    Line 441, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/71.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 14708264405 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_datapath_stress_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 14708264405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (hmac_base_vseq.sv:37) [hmac_burst_wr_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:
- Test hmac_stress_all_with_rand_reset has 1 failures.
  - 87.hmac_stress_all_with_rand_reset.911296003
    Line 578, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/87.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 24499842776 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_burst_wr_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 24499842776 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (hmac_base_vseq.sv:37) [hmac_common_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:
- Test hmac_stress_all_with_rand_reset has 1 failures.
  - 111.hmac_stress_all_with_rand_reset.2388654430
    Line 715, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/111.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 29797489740 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 29797489740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (hmac_base_vseq.sv:37) [hmac_long_msg_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:
- Test hmac_stress_all_with_rand_reset has 1 failures.
  - 178.hmac_stress_all_with_rand_reset.3550901547
    Line 1225, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/178.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 90539190212 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_long_msg_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 90539190212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```