Testbench Group List
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Total Groups Coverage Summary 
COVEREDEXPECTEDSCORECOVEREDEXPECTEDINST SCOREWEIGHT
725 727 99.72 725 727 99.72 1


Total groups in report: 16
NAMECOVEREDEXPECTEDSCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSINGCOMMENT
cip_base_pkg::tl_errors_cg_wrap::tl_errors_cg 13 15 86.67 100.00 1 100 1 1 64 64
hmac_env_pkg::hmac_env_cov::msg_len_cg 228 230 99.13 1 100 1 0 64 64
alert_esc_agent_pkg::alert_handshake_complete_cg 3 3 100.00 100.00 1 100 1 1 64 64
cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2} 19 19 100.00 1 100 1 0 64 64
cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2} 19 19 100.00 1 100 1 0 64 64
cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2} 27 27 100.00 1 100 1 0 64 64
cip_base_pkg::tl_intg_err_cg_wrap::tl_intg_err_cg 14 14 100.00 100.00 1 100 1 1 64 64
cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg 24 24 100.00 100.00 1 100 1 1 64 64
dv_lib_pkg::bit_toggle_cg_wrap::bit_toggle_cg 4 4 100.00 100.00 1 100 1 1 64 64
hmac_env_pkg::hmac_env_cov::cfg_cg 14 14 100.00 1 100 1 0 64 64
hmac_env_pkg::hmac_env_cov::err_code_cg 5 5 100.00 1 100 1 0 64 64
hmac_env_pkg::hmac_env_cov::status_cg 195 195 100.00 1 100 1 0 64 64
tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check.u_prim_onehot_check_if::prim_onehot_check_if_proxy::onehot_fault_cg 3 3 100.00 100.00 1 100 1 1 64 64
tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=1} 1 1 100.00 100.00 1 100 1 1 64 64
tl_agent_pkg::pending_req_on_rst_cg 2 2 100.00 100.00 1 100 1 1 64 64
tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128} 137 137 100.00 100.00 1 100 1 1 64 64
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%