HMAC Simulation Results

Sunday December 24 2023 20:02:26 UTC

GitHub Revision: 671f2b57e2

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 96716765175854174075659971574604807242747408006700796360560480210023744343645

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	4.560s	1.225ms	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	0.710s	17.191us	5	5	100.00
V1	csr_rw	hmac_csr_rw	0.730s	48.257us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	6.450s	2.160ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	2.630s	186.923us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	15.302m	413.078ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.730s	48.257us	20	20	100.00
		hmac_csr_aliasing	2.630s	186.923us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	2.160m	9.335ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	1.088m	1.763ms	50	50	100.00
V2	test_vectors	hmac_test_sha_vectors	8.672m	122.036ms	46	50	92.00
		hmac_test_hmac_vectors	1.270s	215.661us	50	50	100.00
V2	burst_wr	hmac_burst_wr	1.133m	1.532ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	2.405m	2.770ms	50	50	100.00
V2	error	hmac_error	4.225m	15.860ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	1.535m	8.806ms	50	50	100.00
V2	stress_all	hmac_stress_all	42.312m	1.400s	50	50	100.00
V2	alert_test	hmac_alert_test	0.640s	21.567us	50	50	100.00
V2	intr_test	hmac_intr_test	0.640s	16.526us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	3.350s	193.975us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	3.350s	193.975us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	0.710s	17.191us	5	5	100.00
		hmac_csr_rw	0.730s	48.257us	20	20	100.00
		hmac_csr_aliasing	2.630s	186.923us	5	5	100.00
		hmac_same_csr_outstanding	1.440s	152.196us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	0.710s	17.191us	5	5	100.00
		hmac_csr_rw	0.730s	48.257us	20	20	100.00
		hmac_csr_aliasing	2.630s	186.923us	5	5	100.00
		hmac_same_csr_outstanding	1.440s	152.196us	20	20	100.00
V2		TOTAL			586	590	99.32
V2S	tl_intg_err	hmac_sec_cm	1.030s	143.357us	5	5	100.00
		hmac_tl_intg_err	2.540s	334.496us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	2.540s	334.496us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	4.560s	1.225ms	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	1.551h	549.302ms	193	200	96.50
V3		TOTAL			193	200	96.50
		TOTAL			909	920	98.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	13	13	12	92.31
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.62	99.53	98.58	100.00	100.00	99.76	99.49	100.00

Failure Buckets

• UVM_ERROR (hmac_base_vseq.sv:37) [hmac_stress_all_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 7 failures:
  • Test hmac_stress_all_with_rand_reset has 7 failures.

    • 38.hmac_stress_all_with_rand_reset.76162561017861128413015779595416411189330895767480752879216902829842764412482
      Line 913, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/38.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 285726742364 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_stress_all_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 285726742364 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 49.hmac_stress_all_with_rand_reset.96717631544491446217203777527845313273512188815255126649507750079689990610500
      Line 305, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/49.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4943122720 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_stress_all_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 4943122720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 5 more failures.

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:
  • Test hmac_test_sha_vectors has 4 failures.

    • 5.hmac_test_sha_vectors.94636336721465992501835971606659526237167307351714377407939789081129894115680
      Line 248, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/5.hmac_test_sha_vectors/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 36.hmac_test_sha_vectors.19701323005255195262523856176936005189489881994530881408994608948528249344281
      Line 248, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/36.hmac_test_sha_vectors/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 2 more failures.

Past Results

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