Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	121562104	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

135231968

1

T13

586

T14

104

T15

338

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	101794855	1			T13	297		T14	77		T15	181
values[0x0]	71991048	1			T13	123		T14	37		T15	77
values[0x1]	83008169	1			T13	166		T14	30		T15	80

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	88927326	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

167866746

1

T13

586

T14

120

T15

338

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	963835	1			T15	4		T17	86		T18	2
valid_sources[0x01]	955810	1			T14	4		T15	4		T17	87
valid_sources[0x02]	960736	1			T15	1		T17	88		T18	16
valid_sources[0x03]	1318437	1			T15	1		T17	85		T18	1
valid_sources[0x04]	1009645	1			T17	78		T32	1		T33	5
valid_sources[0x05]	962905	1			T13	4		T15	1		T16	2
valid_sources[0x06]	1045168	1			T14	1		T15	3		T17	98
valid_sources[0x07]	978173	1			T13	17		T15	2		T17	82
valid_sources[0x08]	947730	1			T14	1		T15	2		T17	84
valid_sources[0x09]	977979	1			T14	3		T15	1		T17	78
valid_sources[0x0a]	921786	1			T13	2		T15	1		T17	86
valid_sources[0x0b]	980240	1			T15	3		T17	98		T18	9
valid_sources[0x0c]	947748	1			T15	1		T17	65		T32	3
valid_sources[0x0d]	952056	1			T15	3		T17	83		T32	9
valid_sources[0x0e]	945994	1			T17	80		T18	2		T32	3
valid_sources[0x0f]	1021632	1			T13	9		T15	1		T17	83
valid_sources[0x10]	996066	1			T14	1		T15	1		T17	86
valid_sources[0x11]	959225	1			T13	28		T15	1		T17	85
valid_sources[0x12]	966611	1			T13	5		T14	1		T15	2
valid_sources[0x13]	964235	1			T14	1		T15	3		T17	78
valid_sources[0x14]	973195	1			T15	1		T17	77		T32	1
valid_sources[0x15]	942404	1			T14	2		T17	74		T32	14
valid_sources[0x16]	997039	1			T17	85		T20	1		T32	2
valid_sources[0x17]	958234	1			T13	12		T15	5		T17	83
valid_sources[0x18]	938529	1			T17	93		T32	7		T25	7
valid_sources[0x19]	1007095	1			T15	1		T17	75		T18	1
valid_sources[0x1a]	959937	1			T15	3		T17	77		T32	13
valid_sources[0x1b]	956815	1			T15	1		T17	79		T32	5
valid_sources[0x1c]	964624	1			T17	75		T32	4		T33	11
valid_sources[0x1d]	987169	1			T14	1		T15	1		T17	86
valid_sources[0x1e]	940665	1			T15	1		T17	68		T24	2
valid_sources[0x1f]	1741568	1			T15	2		T17	90		T18	1
valid_sources[0x20]	977093	1			T15	1		T17	69		T32	3
valid_sources[0x21]	1000744	1			T15	1		T17	79		T32	2
valid_sources[0x22]	1044580	1			T15	1		T17	80		T20	1
valid_sources[0x23]	926826	1			T13	19		T15	2		T17	91
valid_sources[0x24]	1004853	1			T17	79		T20	18		T21	3
valid_sources[0x25]	988857	1			T13	19		T14	1		T15	2
valid_sources[0x26]	988811	1			T13	4		T14	1		T15	5
valid_sources[0x27]	955641	1			T13	15		T15	4		T17	74
valid_sources[0x28]	973505	1			T14	1		T15	1		T17	84
valid_sources[0x29]	965651	1			T13	5		T17	72		T32	6
valid_sources[0x2a]	960440	1			T15	1		T17	72		T20	62
valid_sources[0x2b]	982802	1			T14	1		T17	106		T32	4
valid_sources[0x2c]	949863	1			T14	2		T15	1		T17	71
valid_sources[0x2d]	1004092	1			T17	69		T20	9		T32	6
valid_sources[0x2e]	1319246	1			T15	1		T17	84		T22	38
valid_sources[0x2f]	1003273	1			T15	1		T17	95		T26	7
valid_sources[0x30]	972876	1			T15	1		T17	76		T20	1
valid_sources[0x31]	960818	1			T13	13		T14	2		T15	1
valid_sources[0x32]	939021	1			T15	1		T17	79		T32	3
valid_sources[0x33]	955027	1			T15	1		T17	82		T20	1
valid_sources[0x34]	966896	1			T15	1		T17	95		T18	3
valid_sources[0x35]	1308245	1			T15	2		T17	96		T18	4
valid_sources[0x36]	961232	1			T15	1		T17	74		T20	54
valid_sources[0x37]	951952	1			T17	86		T18	2		T20	8
valid_sources[0x38]	960476	1			T13	1		T15	3		T17	80
valid_sources[0x39]	1005110	1			T15	2		T17	93		T18	4
valid_sources[0x3a]	964260	1			T13	10		T14	1		T15	2
valid_sources[0x3b]	998430	1			T13	18		T17	72		T32	11
valid_sources[0x3c]	952575	1			T15	2		T17	77		T18	1
valid_sources[0x3d]	952041	1			T14	2		T15	1		T17	91
valid_sources[0x3e]	970924	1			T14	1		T17	72		T18	1
valid_sources[0x3f]	985970	1			T13	16		T14	1		T15	2
valid_sources[0x40]	975939	1			T14	2		T15	2		T17	91
valid_sources[0x41]	960127	1			T14	2		T15	1		T17	81
valid_sources[0x42]	1024054	1			T13	2		T17	72		T32	1
valid_sources[0x43]	953560	1			T15	3		T16	5		T17	79
valid_sources[0x44]	962009	1			T14	1		T15	1		T17	87
valid_sources[0x45]	963369	1			T15	1		T17	70		T18	1
valid_sources[0x46]	992137	1			T17	86		T32	4		T33	9
valid_sources[0x47]	1279207	1			T17	89		T32	2		T46	1
valid_sources[0x48]	983463	1			T14	2		T15	2		T17	82
valid_sources[0x49]	965202	1			T13	23		T15	2		T17	90
valid_sources[0x4a]	960448	1			T16	3		T17	82		T32	9
valid_sources[0x4b]	955782	1			T15	1		T17	71		T20	15
valid_sources[0x4c]	957624	1			T15	1		T17	76		T32	4
valid_sources[0x4d]	963548	1			T15	1		T17	87		T32	4
valid_sources[0x4e]	1310225	1			T13	21		T15	1		T17	81
valid_sources[0x4f]	960489	1			T14	1		T15	2		T17	70
valid_sources[0x50]	1001155	1			T15	1		T17	91		T32	6
valid_sources[0x51]	1060061	1			T14	1		T15	3		T17	61
valid_sources[0x52]	974878	1			T15	1		T16	1		T17	83
valid_sources[0x53]	960592	1			T14	1		T15	3		T17	94
valid_sources[0x54]	984107	1			T17	92		T32	3		T26	10
valid_sources[0x55]	953703	1			T15	3		T17	72		T18	6
valid_sources[0x56]	955977	1			T13	20		T14	1		T15	2
valid_sources[0x57]	941582	1			T13	21		T17	76		T32	6
valid_sources[0x58]	959800	1			T13	1		T15	2		T17	85
valid_sources[0x59]	997313	1			T14	1		T15	1		T17	81
valid_sources[0x5a]	977602	1			T15	1		T17	81		T20	20
valid_sources[0x5b]	957882	1			T15	3		T17	86		T32	3
valid_sources[0x5c]	934454	1			T15	1		T17	93		T19	1
valid_sources[0x5d]	992944	1			T17	77		T32	8		T25	2
valid_sources[0x5e]	1002823	1			T15	2		T17	88		T32	5
valid_sources[0x5f]	950136	1			T15	1		T17	72		T32	5
valid_sources[0x60]	951744	1			T14	2		T15	1		T17	83
valid_sources[0x61]	988646	1			T15	2		T17	80		T32	6
valid_sources[0x62]	970072	1			T14	1		T15	2		T16	6
valid_sources[0x63]	989274	1			T13	2		T14	3		T17	89
valid_sources[0x64]	966020	1			T15	4		T17	76		T18	5
valid_sources[0x65]	970168	1			T14	1		T15	1		T17	74
valid_sources[0x66]	963789	1			T17	95		T20	6		T32	2
valid_sources[0x67]	1340913	1			T15	4		T17	77		T32	3
valid_sources[0x68]	930324	1			T15	1		T17	81		T32	8
valid_sources[0x69]	931420	1			T15	1		T17	84		T18	5
valid_sources[0x6a]	947501	1			T13	6		T15	2		T17	98
valid_sources[0x6b]	971608	1			T17	86		T20	18		T32	13
valid_sources[0x6c]	1027195	1			T15	1		T17	65		T32	6
valid_sources[0x6d]	978610	1			T15	1		T17	80		T19	1
valid_sources[0x6e]	925833	1			T14	1		T17	97		T21	1
valid_sources[0x6f]	971275	1			T14	1		T17	92		T32	3
valid_sources[0x70]	940260	1			T15	3		T17	75		T32	13
valid_sources[0x71]	993048	1			T14	1		T17	65		T32	4
valid_sources[0x72]	963821	1			T14	1		T15	1		T17	75
valid_sources[0x73]	960509	1			T16	1		T17	98		T18	1
valid_sources[0x74]	956780	1			T15	3		T17	77		T18	1
valid_sources[0x75]	932976	1			T15	1		T17	92		T18	1
valid_sources[0x76]	956899	1			T14	2		T15	1		T17	92
valid_sources[0x77]	997931	1			T15	2		T17	68		T20	6
valid_sources[0x78]	979495	1			T13	5		T15	3		T17	81
valid_sources[0x79]	1025610	1			T15	2		T17	86		T18	3
valid_sources[0x7a]	1030059	1			T14	2		T15	1		T17	82
valid_sources[0x7b]	1007814	1			T15	1		T17	86		T32	3
valid_sources[0x7c]	986704	1			T14	2		T15	1		T17	84
valid_sources[0x7d]	952667	1			T14	1		T15	3		T17	87
valid_sources[0x7e]	963707	1			T14	1		T15	3		T17	75
valid_sources[0x7f]	946717	1			T17	75		T32	2		T33	6
valid_sources[0x80]	953077	1			T15	1		T17	76		T32	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

48978003

1

T13

297

T14

43

T15

181

values[0x0]

all_enables

biggest_size

44960113

1

T13

123

T14

34

T15

77

values[0x1]

all_enables

biggest_size

41293852

1

T13

166

T14

27

T15

80