Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

178580252

1

T14

40

T16

26

T17

47724

full_word

139538609

1

T13

586

T14

104

T15

338

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	318118481	1			T13	586		T14	144		T15	338
auto[TlIntgErrCmd]	125	1			T61	3		T62	4		T63	7
auto[TlIntgErrData]	127	1			T61	3		T62	3		T129	11
auto[TlIntgErrBoth]	128	1			T61	4		T62	3		T63	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

124339595

1

T13

297

T14

77

T15

181

auto[1]

193779266

1

T13

289

T14

67

T15

157

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	73645804	1			T14	34		T16	11		T17	18684
auto[TlIntgErrNone]	partial	auto[1]	104934093	1			T14	6		T16	15		T17	29040
auto[TlIntgErrNone]	full_word	auto[0]	50693627	1			T13	297		T14	43		T15	181
auto[TlIntgErrNone]	full_word	auto[1]	88844957	1			T13	289		T14	61		T15	157
auto[TlIntgErrCmd]	partial	auto[0]	45	1			T61	1		T62	3		T63	1
auto[TlIntgErrCmd]	partial	auto[1]	72	1			T61	2		T62	1		T63	6
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T135	1		T136	1		T132	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T130	1		T135	1		T134	1
auto[TlIntgErrData]	partial	auto[0]	56	1			T61	1		T62	2		T129	2
auto[TlIntgErrData]	partial	auto[1]	58	1			T61	1		T62	1		T129	8
auto[TlIntgErrData]	full_word	auto[0]	6	1			T61	1		T130	1		T135	2
auto[TlIntgErrData]	full_word	auto[1]	7	1			T129	1		T135	1		T131	1
auto[TlIntgErrBoth]	partial	auto[0]	52	1			T62	1		T63	2		T129	5
auto[TlIntgErrBoth]	partial	auto[1]	72	1			T61	4		T62	1		T63	1
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T137	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T62	1		T130	1		T136	1