Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.06	100.00	95.31	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1453903241	37280477	0	0
intr_enable_rd_A	1453903241	11946	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1453903241	37280477	0	0
T17	103192	28787	0	0
T18	1287	0	0	0
T19	1129	0	0	0
T20	4585	631	0	0
T21	1441	0	0	0
T22	1592	0	0	0
T23	5012	314	0	0
T24	1455	0	0	0
T25	0	128	0	0
T26	0	4	0	0
T27	0	1	0	0
T28	0	403128	0	0
T29	0	698	0	0
T32	10447	0	0	0
T33	1498	0	0	0
T62	0	3	0	0
T63	0	3	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1453903241	11946	0	0
T14	1917	12	0	0
T15	2896	0	0	0
T16	1062	0	0	0
T17	103192	32	0	0
T18	1287	0	0	0
T19	1129	0	0	0
T20	4585	0	0	0
T21	1441	0	0	0
T22	1592	0	0	0
T24	1455	0	0	0
T28	0	272	0	0
T32	0	136	0	0
T46	0	7	0	0
T61	0	83	0	0
T63	0	74	0	0
T64	0	397	0	0
T65	0	38	0	0
T66	0	15	0	0