Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.06	100.00	95.31	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1410016874	35194669	0	0
intr_enable_rd_A	1410016874	15372	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1410016874	35194669	0	0
T13	3370	4	0	0
T14	1033	0	0	0
T15	14889	7	0	0
T16	1317	0	0	0
T17	1724	0	0	0
T18	185799	84606	0	0
T19	14725	6	0	0
T20	1135	0	0	0
T21	983	0	0	0
T22	0	1	0	0
T23	1515	0	0	0
T24	0	1	0	0
T25	0	1	0	0
T26	0	281	0	0
T60	0	7	0	0
T61	0	8	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1410016874	15372	0	0
T17	1724	6	0	0
T18	185799	0	0	0
T19	14725	0	0	0
T20	1135	0	0	0
T21	983	9	0	0
T23	1515	2	0	0
T44	13025	0	0	0
T59	1159	0	0	0
T64	2025	40	0	0
T65	1877	7	0	0
T66	0	11	0	0
T67	0	16	0	0
T68	0	55	0	0
T69	0	4	0	0
T70	0	13	0	0