Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

38705521

1

T1

3903

T2

350

T3

172950

full_word

36204554

1

T1

3287

T2

2518

T3

167342

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	74909705	1			T1	7190		T2	2868		T3	340292
auto[TlIntgErrCmd]	119	1			T52	11		T53	2		T54	2
auto[TlIntgErrData]	117	1			T52	10		T53	3		T54	4
auto[TlIntgErrBoth]	134	1			T52	9		T53	5		T54	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29853472

1

T1

2907

T2

110

T3

136677

auto[1]

45056603

1

T1

4283

T2

2758

T3

203615

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	16120906	1			T1	1440		T2	62		T3	68308
auto[TlIntgErrNone]	partial	auto[1]	22584268	1			T1	2463		T2	288		T3	104642
auto[TlIntgErrNone]	full_word	auto[0]	13732407	1			T1	1467		T2	48		T3	68369
auto[TlIntgErrNone]	full_word	auto[1]	22472124	1			T1	1820		T2	2470		T3	98973
auto[TlIntgErrCmd]	partial	auto[0]	45	1			T52	1		T53	1		T54	1
auto[TlIntgErrCmd]	partial	auto[1]	66	1			T52	6		T53	1		T54	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T52	1		T133	1		T134	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T52	3		T132	2		-	-
auto[TlIntgErrData]	partial	auto[0]	51	1			T52	4		T54	1		T59	2
auto[TlIntgErrData]	partial	auto[1]	57	1			T52	6		T53	3		T54	2
auto[TlIntgErrData]	full_word	auto[0]	2	1			T135	1		T134	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	7	1			T54	1		T133	1		T136	1
auto[TlIntgErrBoth]	partial	auto[0]	55	1			T52	4		T53	1		T54	2
auto[TlIntgErrBoth]	partial	auto[1]	73	1			T52	5		T53	4		T54	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T131	1		T135	1		T137	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T138	1		T133	1		T139	1