Unified Coverage Report :: Module :: prim_sha2_pad

Module : prim_sha2_pad

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.26	95.37	90.70		66.67	84.31

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_sha2_0/rtl/prim_sha2_pad.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_prim_sha2_256.gen_sha256_logic.u_prim_sha2_256.u_pad	92.54	99.04	95.12		90.00	86.00

---

Module Instance : tb.dut.u_prim_sha2_256.gen_sha256_logic.u_prim_sha2_256.u_pad

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.54	99.04	95.12		90.00	86.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.54	99.04	95.12		90.00	86.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.23	94.48	95.89		100.00	98.53		gen_sha256_logic.u_prim_sha2_256

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_sha2_pad

	Line No.	Total	Covered	Percent
TOTAL		108	103	95.37
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	50	0	0
CONT_ASSIGN	53	1	1	100.00
CONT_ASSIGN	57	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
ALWAYS	68	3	3	100.00
ALWAYS	83	13	13	100.00
ALWAYS	172	3	3	100.00
ALWAYS	178	69	65	94.20
ALWAYS	322	8	7	87.50
ALWAYS	340	3	3	100.00
CONT_ASSIGN	344	1	1	100.00
ALWAYS	349	3	3	100.00
CONT_ASSIGN	354	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sha2_0/rtl/prim_sha2_pad.sv' or '../src/lowrisc_prim_sha2_0/rtl/prim_sha2_pad.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
50		unreachable
53	1	1
57	1	1
63	1	1
68	2	2
69	1	1
83	1	1
85	1	1
94	1	1
95	1	1
96	1	1
97	1	1
98	1	1
99	1	1
102		unreachable
103		unreachable
104		unreachable
105		unreachable
106		unreachable
107		unreachable
108		unreachable
109		unreachable
110		unreachable
111		unreachable
115		unreachable
119	1	1
123	1	1
130	1	1
141	2	2
			==> MISSING_ELSE
172	2	2
173	1	1
178	1	1
179	1	1
180	1	1
181	1	1
182	1	1
184	1	1
186	1	1
187	1	1
188	1	1
189	1	1
190	1	1
192	1	1
197	1	1
198	1	1
200	1	1
201	1	1
202	1	1
203	1	1
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
212	1	1
213	1	1
214	1	1
215	1	1
217	1	1
218	1	1
219	1	1
220	1	1
225	1	1
226	1	1
227	1	1
233	1	1
234	1	1
235	1	1
239	1	1
240	1	1
241	1	1
243	1	1
244	1	1
273	1	1
274	1	1
276	1	1
277	1	1
278	2	2
279	1	1
281	1	1
286	1	1
287	1	1
289	1	1
290	1	1
291	1	1
293	0	1
294	0	1
299	1	1
300	1	1
302	1	1
303	1	1
304	1	1
306	0	1
307	0	1
316	2	2
317	2	2
			MISSING_ELSE
322	1	1
324	1	1
326	1	1
327	1	1
329	0	1
330	1	1
331	1	1
332	1	1
333		unreachable
334		unreachable
			==> MISSING_ELSE
			MISSING_ELSE
340	2	2
341	1	1
344	1	1
349	2	2
350	1	1
354	1	1

---

Cond Coverage for Module : prim_sha2_pad

	Total	Covered	Percent
Conditions	43	39	90.70
Logical	43	39	90.70
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (hash_start_i | hash_continue_i)
             ------1-----   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T2,T3,T4

 LINE       57
 SUB-EXPRESSION (tx_count[8:0] == 9'h1a0)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       57
 SUB-EXPRESSION (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ? (tx_count[9:0] == 10'h340) : '0)
                 -----------------------------------1----------------------------------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       57
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
                 ----------------1---------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Unreachable
0	1	Unreachable
1	0	Unreachable

 LINE       57
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       57
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       57
 SUB-EXPRESSION (tx_count[9:0] == 10'h340)
                -------------1------------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       63
 EXPRESSION ((((~sha_en_i)) || hash_go || hash_done_o) ? 1'b0 : (hash_process_i ? 1'b1 : hash_process_flag_q))
             --------------------1--------------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       63
 SUB-EXPRESSION (((~sha_en_i)) || hash_go || hash_done_o)
                 ------1------    ---2---    -----3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T2,T3,T4
0	0	1	Covered	T2,T3,T4
0	1	0	Covered	T2,T3,T4
1	0	0	Covered	T1,T2,T3

 LINE       63
 SUB-EXPRESSION (hash_process_i ? 1'b1 : hash_process_flag_q)
                 -------1------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       102
 EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
             ----------------1---------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Unreachable
0	1	Unreachable
1	0	Unreachable

 LINE       102
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       102
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       188
 EXPRESSION (sha_en_i && hash_go)
             ----1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       198
 EXPRESSION (fifo_partial && fifo_rvalid_i)
             ------1-----    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       209
 EXPRESSION ((((tx_count == message_length_i) & MultimodeEn)) || ((tx_count[63:0] == message_length_i[63:0]) & ((!MultimodeEn))))
             ------------------------1-----------------------    -------------------------------2-------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
1	0	Unreachable

 LINE       209
 SUB-EXPRESSION ((tx_count[63:0] == message_length_i[63:0]) & ((!MultimodeEn)))
                 ---------------------1--------------------   --------2-------

-1-	-2-	Status	Tests
0	-	Covered	T2,T3,T4
1	-	Covered	T2,T3,T4

 LINE       209
 SUB-EXPRESSION (tx_count[63:0] == message_length_i[63:0])
                ---------------------1--------------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       227
 SUB-EXPRESSION (shaf_rready_i && ((|message_length_i[4:3])))
                 ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       227
 SUB-EXPRESSION (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ? (shaf_rready_i && ((|message_length_i[5:3]))) : '0)
                 -----------------------------------1----------------------------------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       227
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
                 ----------------1---------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Unreachable
0	1	Unreachable
1	0	Unreachable

 LINE       227
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       227
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       227
 SUB-EXPRESSION (shaf_rready_i && ((|message_length_i[5:3])))
                 ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Unreachable
1	1	Unreachable

 LINE       233
 EXPRESSION (shaf_rready_i && txcnt_eq_1a0)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       239
 EXPRESSION (shaf_rready_i && ((!txcnt_eq_1a0)))
             ------1------    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       333
 EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
             ----------------1---------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Unreachable
0	1	Unreachable
1	0	Unreachable

 LINE       333
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       333
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       344
 EXPRESSION (hash_start_i ? digest_mode_i : (hash_done_o ? None : digest_mode_flag_q))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       344
 SUB-EXPRESSION (hash_done_o ? None : digest_mode_flag_q)
                 -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       354
 EXPRESSION (hash_process_flag_q && (st_q == StIdle))
             ---------1---------    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       354
 SUB-EXPRESSION (st_q == StIdle)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Module : prim_sha2_pad

Summary for FSM :: st_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	15	10	66.67
Sequences	0	0

State, Transition and Sequence Details for FSM :: st_q

---

states	Line No.	Covered	Tests
StFifoReceive	190	Covered	T2,T3,T4
StIdle	182	Covered	T1,T2,T3
StLenHi	234	Covered	T2,T3,T4
StLenLo	290	Covered	T2,T3,T4
StPad00	240	Covered	T2,T3,T4
StPad80	203	Covered	T2,T3,T4

transitions	Line No.	Covered	Tests
StFifoReceive->StIdle	182	Covered	T33,T34,T35
StFifoReceive->StPad80	203	Covered	T2,T3,T4
StIdle->StFifoReceive	190	Covered	T2,T3,T4
StLenHi->StFifoReceive	317	Not Covered
StLenHi->StIdle	182	Covered	T33,T36
StLenHi->StLenLo	290	Covered	T2,T3,T4
StLenLo->StFifoReceive	317	Not Covered
StLenLo->StIdle	182	Covered	T2,T3,T4
StPad00->StFifoReceive	317	Not Covered
StPad00->StIdle	182	Covered	T35
StPad00->StLenHi	278	Covered	T2,T3,T4
StPad80->StFifoReceive	317	Not Covered
StPad80->StIdle	182	Not Covered
StPad80->StLenHi	234	Covered	T2,T3,T4
StPad80->StPad00	240	Covered	T2,T3,T4

---

Branch Coverage for Module : prim_sha2_pad

	Line No.	Total	Covered	Percent
Branches		51	43	84.31
TERNARY	63	3	3	100.00
TERNARY	344	3	3	100.00
IF	68	2	2	100.00
CASE	83	10	8	80.00
IF	141	2	1	50.00
IF	172	2	2	100.00
CASE	184	17	14	82.35
IF	316	3	3	100.00
IF	324	5	3	60.00
IF	340	2	2	100.00
IF	349	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_sha2_0/rtl/prim_sha2_pad.sv' or '../src/lowrisc_prim_sha2_0/rtl/prim_sha2_pad.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	63	((((~sha_en_i) || hash_go) || hash_done_o)) ? 
-2-:	63	(hash_process_i) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	344	(hash_start_i) ? 
-2-:	344	(hash_done_o) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	68	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	83	case (sel_data)
-2-:	94	if (((digest_mode_flag_q == SHA2_256) || (~MultimodeEn)))
-3-:	95	case (message_length_i[4:3])
-4-:	102	if (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)))
-5-:	103	case (message_length_i[5:3])

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
FifoIn	-	-	-	-	Covered	T1,T2,T3
Pad80	1	2'b00	-	-	Covered	T2,T3,T4
Pad80	1	2'b01	-	-	Covered	T2,T3,T4
Pad80	1	2'b10	-	-	Covered	T2,T3,T4
Pad80	1	2'b11	-	-	Covered	T2,T3,T4
Pad80	1	default	-	-	Not Covered
Pad80	0	-	1	3'b000	Unreachable
Pad80	0	-	1	3'b001	Unreachable
Pad80	0	-	1	3'b010	Unreachable
Pad80	0	-	1	3'b011	Unreachable
Pad80	0	-	1	3'b100	Unreachable
Pad80	0	-	1	3'b101	Unreachable
Pad80	0	-	1	3'b110	Unreachable
Pad80	0	-	1	3'b111	Unreachable
Pad80	0	-	1	default	Unreachable
Pad80	0	-	0	-	Unreachable
Pad00	-	-	-	-	Covered	T2,T3,T4
LenHi	-	-	-	-	Covered	T2,T3,T4
LenLo	-	-	-	-	Covered	T2,T3,T4
default	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	141	if ((!MultimodeEn))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	172	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	184	case (st_q)
-2-:	188	if ((sha_en_i && hash_go))
-3-:	198	if ((fifo_partial && fifo_rvalid_i))
-4-:	204	if ((!hash_process_flag_q))
-5-:	209	if ((((tx_count == message_length_i) & MultimodeEn) || ((tx_count[63:0] == message_length_i[63:0]) & (!MultimodeEn))))
-6-:	233	if ((shaf_rready_i && txcnt_eq_1a0))
-7-:	239	if ((shaf_rready_i && (!txcnt_eq_1a0)))
-8-:	276	if (shaf_rready_i)
-9-:	278	if (txcnt_eq_1a0)
-10-:	289	if (shaf_rready_i)
-11-:	302	if (shaf_rready_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
StIdle	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StFifoReceive	-	1	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
StFifoReceive	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T4
StFifoReceive	-	0	0	1	-	-	-	-	-	-	Covered	T2,T3,T4
StFifoReceive	-	0	0	0	-	-	-	-	-	-	Covered	T2,T3,T4
StPad80	-	-	-	-	1	-	-	-	-	-	Covered	T2,T3,T4
StPad80	-	-	-	-	0	1	-	-	-	-	Covered	T2,T3,T4
StPad80	-	-	-	-	0	0	-	-	-	-	Covered	T2,T3,T4
StPad00	-	-	-	-	-	-	1	1	-	-	Covered	T2,T3,T4
StPad00	-	-	-	-	-	-	1	0	-	-	Covered	T2,T3,T4
StPad00	-	-	-	-	-	-	0	-	-	-	Covered	T2,T3,T4
StLenHi	-	-	-	-	-	-	-	-	1	-	Covered	T2,T3,T4
StLenHi	-	-	-	-	-	-	-	-	0	-	Not Covered
StLenLo	-	-	-	-	-	-	-	-	-	1	Covered	T2,T3,T4
StLenLo	-	-	-	-	-	-	-	-	-	0	Not Covered
default	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	316	if ((!sha_en_i))
-2-:	317	if (hash_go)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	324	if (hash_start_i)
-2-:	327	if (hash_continue_i)
-3-:	330	if (inc_txcount)
-4-:	331	if (((digest_mode_flag_q == SHA2_256) || (!MultimodeEn)))
-5-:	333	if (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T2,T3,T4
0	1	-	-	-	Not Covered
0	0	1	1	-	Covered	T2,T3,T4
0	0	1	0	1	Unreachable
0	0	1	0	0	Not Covered
0	0	0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	340	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_prim_sha2_256.gen_sha256_logic.u_prim_sha2_256.u_pad

	Line No.	Total	Covered	Percent
TOTAL		104	103	99.04
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	50	0	0
CONT_ASSIGN	53	1	1	100.00
CONT_ASSIGN	57	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
ALWAYS	68	3	3	100.00
ALWAYS	83	13	13	100.00
ALWAYS	172	3	3	100.00
ALWAYS	178	65	65	100.00
ALWAYS	322	8	7	87.50
ALWAYS	340	3	3	100.00
CONT_ASSIGN	344	1	1	100.00
ALWAYS	349	3	3	100.00
CONT_ASSIGN	354	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sha2_0/rtl/prim_sha2_pad.sv' or '../src/lowrisc_prim_sha2_0/rtl/prim_sha2_pad.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
50		unreachable
53	1	1
57	1	1
63	1	1
68	2	2
69	1	1
83	1	1
85	1	1
94	1	1
95	1	1
96	1	1
97	1	1
98	1	1
99	1	1
102		unreachable
103		unreachable
104		unreachable
105		unreachable
106		unreachable
107		unreachable
108		unreachable
109		unreachable
110		unreachable
111		unreachable
115		unreachable
119	1	1
123	1	1
130	1	1
			Exclude Annotation: VC_COV_UNR
141	2	2
			==> MISSING_ELSE
172	2	2
173	1	1
178	1	1
179	1	1
180	1	1
181	1	1
182	1	1
184	1	1
186	1	1
187	1	1
188	1	1
189	1	1
190	1	1
192	1	1
197	1	1
198	1	1
200	1	1
201	1	1
202	1	1
203	1	1
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
212	1	1
213	1	1
214	1	1
215	1	1
217	1	1
218	1	1
219	1	1
220	1	1
225	1	1
226	1	1
227	1	1
233	1	1
234	1	1
235	1	1
239	1	1
240	1	1
241	1	1
243	1	1
244	1	1
273	1	1
274	1	1
276	1	1
277	1	1
278	2	2
279	1	1
281	1	1
286	1	1
287	1	1
289	1	1
290	1	1
291	1	1
293		excluded
			Exclude Annotation: VC_COV_UNR
294		excluded
			Exclude Annotation: VC_COV_UNR
299	1	1
300	1	1
302	1	1
303	1	1
304	1	1
306		excluded
			Exclude Annotation: VC_COV_UNR
307		excluded
			Exclude Annotation: VC_COV_UNR
			Exclude Annotation: VC_COV_UNR
316	2	2
317	2	2
			MISSING_ELSE
322	1	1
324	1	1
326	1	1
327	1	1
329	0	1
330	1	1
331	1	1
332	1	1
333		unreachable
334		unreachable
			==> MISSING_ELSE
			MISSING_ELSE
340	2	2
341	1	1
344	1	1
349	2	2
350	1	1
354	1	1

---

Cond Coverage for Instance : tb.dut.u_prim_sha2_256.gen_sha256_logic.u_prim_sha2_256.u_pad

	Total	Covered	Percent
Conditions	41	39	95.12
Logical	41	39	95.12
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (hash_start_i | hash_continue_i)
             ------1-----   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T2,T3,T4

 LINE       57
 SUB-EXPRESSION (tx_count[8:0] == 9'h1a0)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       57
 SUB-EXPRESSION (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ? (tx_count[9:0] == 10'h340) : '0)
                 -----------------------------------1----------------------------------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       57
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
                 ----------------1---------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Unreachable
0	1	Unreachable
1	0	Unreachable

 LINE       57
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       57
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       57
 SUB-EXPRESSION (tx_count[9:0] == 10'h340)
                -------------1------------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       63
 EXPRESSION ((((~sha_en_i)) || hash_go || hash_done_o) ? 1'b0 : (hash_process_i ? 1'b1 : hash_process_flag_q))
             --------------------1--------------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       63
 SUB-EXPRESSION (((~sha_en_i)) || hash_go || hash_done_o)
                 ------1------    ---2---    -----3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T2,T3,T4
0	0	1	Covered	T2,T3,T4
0	1	0	Covered	T2,T3,T4
1	0	0	Covered	T1,T2,T3

 LINE       63
 SUB-EXPRESSION (hash_process_i ? 1'b1 : hash_process_flag_q)
                 -------1------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       102
 EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
             ----------------1---------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Unreachable
0	1	Unreachable
1	0	Unreachable

 LINE       102
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       102
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       188
 EXPRESSION (sha_en_i && hash_go)
             ----1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       198
 EXPRESSION (fifo_partial && fifo_rvalid_i)
             ------1-----    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       209
 EXPRESSION ((((tx_count == message_length_i) & MultimodeEn)) || ((tx_count[63:0] == message_length_i[63:0]) & ((!MultimodeEn))))
             ------------------------1-----------------------    -------------------------------2-------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
1	0	Unreachable

 LINE       209
 SUB-EXPRESSION ((tx_count[63:0] == message_length_i[63:0]) & ((!MultimodeEn)))
                 ---------------------1--------------------   --------2-------

-1-	-2-	Status	Tests
0	-	Covered	T2,T3,T4
1	-	Covered	T2,T3,T4

 LINE       209
 SUB-EXPRESSION (tx_count[63:0] == message_length_i[63:0])
                ---------------------1--------------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       227
 SUB-EXPRESSION (shaf_rready_i && ((|message_length_i[4:3])))
                 ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       227
 SUB-EXPRESSION (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ? (shaf_rready_i && ((|message_length_i[5:3]))) : '0)
                 -----------------------------------1----------------------------------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       227
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
                 ----------------1---------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Unreachable
0	1	Unreachable
1	0	Unreachable

 LINE       227
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       227
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       227
 SUB-EXPRESSION (shaf_rready_i && ((|message_length_i[5:3])))
                 ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Unreachable
1	1	Unreachable

 LINE       233
 EXPRESSION (shaf_rready_i && txcnt_eq_1a0)
             ------1------    ------2-----

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       239
 EXPRESSION (shaf_rready_i && ((!txcnt_eq_1a0)))
             ------1------    --------2--------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T2,T3,T4
1	0	Excluded		VC_COV_UNR
1	1	Covered	T2,T3,T4

 LINE       333
 EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
             ----------------1---------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Unreachable
0	1	Unreachable
1	0	Unreachable

 LINE       333
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       333
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       344
 EXPRESSION (hash_start_i ? digest_mode_i : (hash_done_o ? None : digest_mode_flag_q))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       344
 SUB-EXPRESSION (hash_done_o ? None : digest_mode_flag_q)
                 -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       354
 EXPRESSION (hash_process_flag_q && (st_q == StIdle))
             ---------1---------    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       354
 SUB-EXPRESSION (st_q == StIdle)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_prim_sha2_256.gen_sha256_logic.u_prim_sha2_256.u_pad

Summary for FSM :: st_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	10	9	90.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st_q

---

states	Line No.	Covered	Tests
StFifoReceive	190	Covered	T2,T3,T4
StIdle	182	Covered	T1,T2,T3
StLenHi	234	Covered	T2,T3,T4
StLenLo	290	Covered	T2,T3,T4
StPad00	240	Covered	T2,T3,T4
StPad80	203	Covered	T2,T3,T4

transitions	Line No.	Covered	Tests	Exclude Annotation
StFifoReceive->StIdle	182	Covered	T33,T34,T35
StFifoReceive->StPad80	203	Covered	T2,T3,T4
StIdle->StFifoReceive	190	Covered	T2,T3,T4
StLenHi->StFifoReceive	317	Excluded		VC_COV_UNR
StLenHi->StIdle	182	Excluded	T33,T36	VC_COV_UNR
StLenHi->StLenLo	290	Covered	T2,T3,T4
StLenLo->StFifoReceive	317	Excluded		VC_COV_UNR
StLenLo->StIdle	182	Covered	T2,T3,T4
StPad00->StFifoReceive	317	Excluded		VC_COV_UNR
StPad00->StIdle	182	Covered	T35
StPad00->StLenHi	278	Covered	T2,T3,T4
StPad80->StFifoReceive	317	Excluded		VC_COV_UNR
StPad80->StIdle	182	Not Covered
StPad80->StLenHi	234	Covered	T2,T3,T4
StPad80->StPad00	240	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_prim_sha2_256.gen_sha256_logic.u_prim_sha2_256.u_pad

	Line No.	Total	Covered	Percent
Branches		50	43	86.00
TERNARY	63	3	3	100.00
TERNARY	344	3	3	100.00
IF	68	2	2	100.00
CASE	83	10	8	80.00
IF	141	1	1	100.00
IF	172	2	2	100.00
CASE	184	17	14	82.35
IF	316	3	3	100.00
IF	324	5	3	60.00
IF	340	2	2	100.00
IF	349	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_sha2_0/rtl/prim_sha2_pad.sv' or '../src/lowrisc_prim_sha2_0/rtl/prim_sha2_pad.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	63	((((~sha_en_i) || hash_go) || hash_done_o)) ? 
-2-:	63	(hash_process_i) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	344	(hash_start_i) ? 
-2-:	344	(hash_done_o) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	68	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	83	case (sel_data)
-2-:	94	if (((digest_mode_flag_q == SHA2_256) || (~MultimodeEn)))
-3-:	95	case (message_length_i[4:3])
-4-:	102	if (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)))
-5-:	103	case (message_length_i[5:3])

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
FifoIn	-	-	-	-	Covered	T1,T2,T3
Pad80	1	2'b00	-	-	Covered	T2,T3,T4
Pad80	1	2'b01	-	-	Covered	T2,T3,T4
Pad80	1	2'b10	-	-	Covered	T2,T3,T4
Pad80	1	2'b11	-	-	Covered	T2,T3,T4
Pad80	1	default	-	-	Not Covered
Pad80	0	-	1	3'b000	Unreachable
Pad80	0	-	1	3'b001	Unreachable
Pad80	0	-	1	3'b010	Unreachable
Pad80	0	-	1	3'b011	Unreachable
Pad80	0	-	1	3'b100	Unreachable
Pad80	0	-	1	3'b101	Unreachable
Pad80	0	-	1	3'b110	Unreachable
Pad80	0	-	1	3'b111	Unreachable
Pad80	0	-	1	default	Unreachable
Pad80	0	-	0	-	Unreachable
Pad00	-	-	-	-	Covered	T2,T3,T4
LenHi	-	-	-	-	Covered	T2,T3,T4
LenLo	-	-	-	-	Covered	T2,T3,T4
default	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	141	if ((!MultimodeEn))

Branches:

-1-	Status	Tests	Exclude Annotation
1	Covered	T1,T2,T3
0	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	172	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	184	case (st_q)
-2-:	188	if ((sha_en_i && hash_go))
-3-:	198	if ((fifo_partial && fifo_rvalid_i))
-4-:	204	if ((!hash_process_flag_q))
-5-:	209	if ((((tx_count == message_length_i) & MultimodeEn) || ((tx_count[63:0] == message_length_i[63:0]) & (!MultimodeEn))))
-6-:	233	if ((shaf_rready_i && txcnt_eq_1a0))
-7-:	239	if ((shaf_rready_i && (!txcnt_eq_1a0)))
-8-:	276	if (shaf_rready_i)
-9-:	278	if (txcnt_eq_1a0)
-10-:	289	if (shaf_rready_i)
-11-:	302	if (shaf_rready_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
StIdle	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StFifoReceive	-	1	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
StFifoReceive	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T4
StFifoReceive	-	0	0	1	-	-	-	-	-	-	Covered	T2,T3,T4
StFifoReceive	-	0	0	0	-	-	-	-	-	-	Covered	T2,T3,T4
StPad80	-	-	-	-	1	-	-	-	-	-	Covered	T2,T3,T4
StPad80	-	-	-	-	0	1	-	-	-	-	Covered	T2,T3,T4
StPad80	-	-	-	-	0	0	-	-	-	-	Covered	T2,T3,T4
StPad00	-	-	-	-	-	-	1	1	-	-	Covered	T2,T3,T4
StPad00	-	-	-	-	-	-	1	0	-	-	Covered	T2,T3,T4
StPad00	-	-	-	-	-	-	0	-	-	-	Covered	T2,T3,T4
StLenHi	-	-	-	-	-	-	-	-	1	-	Covered	T2,T3,T4
StLenHi	-	-	-	-	-	-	-	-	0	-	Not Covered
StLenLo	-	-	-	-	-	-	-	-	-	1	Covered	T2,T3,T4
StLenLo	-	-	-	-	-	-	-	-	-	0	Not Covered
default	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	316	if ((!sha_en_i))
-2-:	317	if (hash_go)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	324	if (hash_start_i)
-2-:	327	if (hash_continue_i)
-3-:	330	if (inc_txcount)
-4-:	331	if (((digest_mode_flag_q == SHA2_256) || (!MultimodeEn)))
-5-:	333	if (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T2,T3,T4
0	1	-	-	-	Not Covered
0	0	1	1	-	Covered	T2,T3,T4
0	0	1	0	1	Unreachable
0	0	1	0	0	Not Covered
0	0	0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	340	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3