Unified Coverage Report :: Module :: prim_sha2

Module : prim_sha2

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.51	93.20	77.78		90.00	93.06

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_sha2_0/rtl/prim_sha2.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_prim_sha2_256.gen_sha256_logic.u_prim_sha2_256	97.23	94.48	95.89		100.00	98.53

---

Module Instance : tb.dut.u_prim_sha2_256.gen_sha256_logic.u_prim_sha2_256

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.23	94.48	95.89		100.00	98.53

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.99	96.39	95.61		94.74	93.22

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_prim_sha2_256

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_pad	92.54	99.04	95.12		90.00	86.00

Line Coverage for Module : prim_sha2

	Line No.	Total	Covered	Percent
TOTAL		147	137	93.20
CONT_ASSIGN	66	1	0	0.00
CONT_ASSIGN	66	1	0	0.00
CONT_ASSIGN	66	1	0	0.00
CONT_ASSIGN	66	1	0	0.00
CONT_ASSIGN	66	1	0	0.00
CONT_ASSIGN	66	1	0	0.00
CONT_ASSIGN	66	1	0	0.00
CONT_ASSIGN	66	1	0	0.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	198	1	1	100.00
ALWAYS	202	11	11	100.00
ALWAYS	222	4	4	100.00
ALWAYS	228	8	8	100.00
ALWAYS	242	3	3	100.00
ALWAYS	248	15	15	100.00
ALWAYS	272	3	3	100.00
CONT_ASSIGN	278	1	1	100.00
CONT_ASSIGN	278	1	1	100.00
CONT_ASSIGN	278	1	1	100.00
CONT_ASSIGN	278	1	1	100.00
CONT_ASSIGN	278	1	1	100.00
CONT_ASSIGN	278	1	1	100.00
CONT_ASSIGN	278	1	1	100.00
CONT_ASSIGN	278	1	1	100.00
ALWAYS	285	7	7	100.00
ALWAYS	302	3	3	100.00
CONT_ASSIGN	307	1	1	100.00
ALWAYS	312	3	3	100.00
CONT_ASSIGN	317	1	1	100.00
ALWAYS	320	3	3	100.00
ALWAYS	333	3	3	100.00
ALWAYS	338	26	26	100.00
ALWAYS	389	3	3	100.00
ALWAYS	403	3	3	100.00
ALWAYS	410	3	3	100.00
CONT_ASSIGN	414	1	1	100.00
ALWAYS	417	23	21	91.30
CONT_ASSIGN	464	1	1	100.00
CONT_ASSIGN	490	1	1	100.00
CONT_ASSIGN	493	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sha2_0/rtl/prim_sha2.sv' or '../src/lowrisc_prim_sha2_0/rtl/prim_sha2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
66	0	8
69	1	1
74	1	1
76	1	1
198	1	1
202	1	1
203	1	1
204	1	1
205	1	1
206	1	1
207	1	1
210	1	1
211	1	1
212	1	1
214	1	1
216	1	1
			MISSING_ELSE
222	2	2
223	2	2
			==> MISSING_ELSE
228	1	1
229	1	1
230	1	1
231	1	1
233	1	1
234	1	1
235	1	1
236	1	1
			MISSING_ELSE
242	2	2
243	1	1
248	1	1
249	1	1
250	1	1
251	1	1
253	1	1
254	1	1
255	1	1
257	1	1
258	1	1
259	1	1
260	1	1
261	1	1
263	1	1
264	1	1
265	1	1
			MISSING_ELSE
272	2	2
273	1	1
278	8	8
285	1	1
286	1	1
287	1	1
288	1	1
289	1	1
293	1	1
295	1	1
			MISSING_ELSE
302	2	2
303	1	1
307	1	1
312	2	2
313	1	1
317	1	1
320	2	2
321	1	1
333	2	2
334	1	1
338	1	1
339	1	1
340	1	1
342	1	1
344	2	2
345	1	1
349	1	1
351	1	1
352	1	1
353	1	1
354	1	1
356	1	1
358	1	1
359	1	1
364	1	1
365	1	1
367	1	1
368	1	1
369	1	1
371	1	1
380	1	1
381	1	1
382	1	1
383	1	1
384	1	1
			MISSING_ELSE
389	2	2
390	1	1
403	2	2
404	1	1
410	2	2
411	1	1
414	1	1
417	1	1
418	1	1
419	1	1
420	1	1
421	1	1
423	1	1
425	1	1
426	1	1
427	1	1
429	1	1
434	1	1
435	1	1
438	1	1
439	1	1
440	1	1
442	1	1
447	1	1
448	1	1
449	0	1
450	0	1
452	1	1
461	2	2
			MISSING_ELSE
464	1	1
490	1	1
493	1	1

---

Cond Coverage for Module : prim_sha2

	Total	Covered	Percent
Conditions	90	70	77.78
Logical	90	70	77.78
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (hash_start_i | hash_continue_i)
             ------1-----   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T2,T3,T4

 LINE       76
 EXPRESSION (hash_go ? digest_mode_i : (hash_done_o ? None : digest_mode_flag_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       76
 SUB-EXPRESSION (hash_done_o ? None : digest_mode_flag_q)
                 -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       205
 EXPRESSION (((!sha_en_i)) || hash_go)
             ------1------    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3

 LINE       207
 EXPRESSION (((!run_hash)) && update_w_from_fifo)
             ------1------    ---------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       261
 EXPRESSION (digest_we_i[i] ? digest_i[i][31:0] : gen_256.digest256_q[i])
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       286
 EXPRESSION (((!sha_en_i)) || hash_go)
             ------1------    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3

 LINE       307
 EXPRESSION ((((~sha_en_i)) || hash_go) ? '0 : (update_w_from_fifo ? ((w_index_q + 1)) : w_index_q))
             -------------1------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       307
 SUB-EXPRESSION (((~sha_en_i)) || hash_go)
                 ------1------    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3

 LINE       307
 SUB-EXPRESSION (update_w_from_fifo ? ((w_index_q + 1)) : w_index_q)
                 ---------1--------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       353
 EXPRESSION (w_index_q == 4'd15)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       364
 EXPRESSION (msg_feed_complete && one_chunk_done)
             --------1--------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       414
 EXPRESSION (hash_start_i | (((~sha_en_i)) & sha_en_q))
             ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T6
1	0	Covered	T2,T3,T4

 LINE       414
 SUB-EXPRESSION (((~sha_en_i)) & sha_en_q)
                 ------1------   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T5,T6

 LINE       425
 EXPRESSION (fifo_st_q == FifoWait)
            -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       435
 EXPRESSION 
 Number  Term
      1  ((((digest_mode_flag_q == SHA2_256) || (~MultimodeEn))) && (round_q < 7'h30)) || 
      2  (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q < 7'h40)))

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Not Covered
1	0	Covered	T2,T3,T4

 LINE       435
 SUB-EXPRESSION ((((digest_mode_flag_q == SHA2_256) || (~MultimodeEn))) && (round_q < 7'h30))
                 ---------------------------1--------------------------    --------2--------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       435
 SUB-EXPRESSION (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q < 7'h40))
                 -----------------------------------1----------------------------------    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Not Covered
1	1	Not Covered

 LINE       435
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
                 ----------------1---------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Not Covered
1	0	Not Covered

 LINE       435
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Not Covered

 LINE       435
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Not Covered

 LINE       448
 EXPRESSION (fifo_st_q == FifoWait)
            -----------1-----------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Not Covered

 LINE       461
 EXPRESSION (((!sha_en_i)) || hash_go)
             ------1------    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3

 LINE       464
 EXPRESSION 
 Number  Term
      1  ((((digest_mode_flag_q == SHA2_256) || (~MultimodeEn))) && (round_q == 7'd63)) ? 1'b1 : ((((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q == 7'd79)) ? 1'b1 : 1'b0))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       464
 SUB-EXPRESSION ((((digest_mode_flag_q == SHA2_256) || (~MultimodeEn))) && (round_q == 7'd63))
                 ---------------------------1--------------------------    ---------2--------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       464
 SUB-EXPRESSION (round_q == 7'd63)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       464
 SUB-EXPRESSION ((((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q == 7'd79)) ? 1'b1 : 1'b0)
                 -----------------------------------------------1----------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       464
 SUB-EXPRESSION (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q == 7'd79))
                 -----------------------------------1----------------------------------    ---------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       464
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
                 ----------------1---------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       464
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       464
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       464
 SUB-EXPRESSION (round_q == 7'd79)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       490
 EXPRESSION (init_hash | run_hash | update_digest)
             ----1----   ----2---   ------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	1	0	Covered	T2,T3,T4
1	0	0	Covered	T2,T3,T4

 LINE       493
 EXPRESSION ((fifo_st_q == FifoIdle) && (sha_st_q == ShaIdle) && ((!hash_go)))
             -----------1-----------    ----------2----------    ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T2,T3,T4
1	1	0	Covered	T2,T3,T4
1	1	1	Covered	T1,T2,T3

 LINE       493
 SUB-EXPRESSION (fifo_st_q == FifoIdle)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       493
 SUB-EXPRESSION (sha_st_q == ShaIdle)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Module : prim_sha2

Summary for FSM :: fifo_st_q

	Total	Covered	Percent
States	3	3	100.00	(Not included in score)
Transitions	5	5	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: fifo_st_q

---

states	Line No.	Covered	Tests
FifoIdle	338	Covered	T1,T2,T3
FifoLoadFromFifo	344	Covered	T2,T3,T4
FifoWait	354	Covered	T2,T3,T4

transitions	Line No.	Covered	Tests
FifoIdle->FifoLoadFromFifo	344	Covered	T2,T3,T4
FifoLoadFromFifo->FifoIdle	338	Covered	T5,T33,T35
FifoLoadFromFifo->FifoWait	354	Covered	T2,T3,T4
FifoWait->FifoIdle	338	Covered	T2,T3,T4
FifoWait->FifoLoadFromFifo	369	Covered	T2,T3,T4

Summary for FSM :: sha_st_q

	Total	Covered	Percent
States	3	3	100.00	(Not included in score)
Transitions	5	4	80.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: sha_st_q

---

states	Line No.	Covered	Tests
ShaCompress	427	Covered	T2,T3,T4
ShaIdle	429	Covered	T1,T2,T3
ShaUpdateDigest	440	Covered	T2,T3,T4

transitions	Line No.	Covered	Tests
ShaCompress->ShaIdle	461	Covered	T5,T11,T12
ShaCompress->ShaUpdateDigest	440	Covered	T2,T3,T4
ShaIdle->ShaCompress	427	Covered	T2,T3,T4
ShaUpdateDigest->ShaCompress	450	Not Covered
ShaUpdateDigest->ShaIdle	452	Covered	T2,T3,T4

---

Branch Coverage for Module : prim_sha2

	Line No.	Total	Covered	Percent
Branches		72	67	93.06
TERNARY	76	3	3	100.00
TERNARY	307	3	3	100.00
TERNARY	464	3	2	66.67
IF	286	4	4	100.00
IF	302	2	2	100.00
IF	312	2	2	100.00
IF	320	2	2	100.00
IF	333	2	2	100.00
CASE	342	9	8	88.89
IF	380	3	3	100.00
IF	389	2	2	100.00
IF	403	2	2	100.00
IF	410	2	2	100.00
CASE	423	8	6	75.00
IF	461	2	2	100.00
IF	203	6	6	100.00
IF	222	3	2	66.67
IF	229	4	4	100.00
IF	242	2	2	100.00
IF	249	6	6	100.00
IF	272	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_sha2_0/rtl/prim_sha2.sv' or '../src/lowrisc_prim_sha2_0/rtl/prim_sha2.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	(hash_go) ? 
-2-:	76	(hash_done_o) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	307	(((~sha_en_i) || hash_go)) ? 
-2-:	307	(update_w_from_fifo) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	464	((((digest_mode_flag_q == SHA2_256) || (~MultimodeEn)) && (round_q == 7'd63))) ? 
-2-:	464	((((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q == 7'd79))) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Not Covered
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	286	if (((!sha_en_i) || hash_go))
-2-:	288	if (run_hash)
-3-:	289	if ((((round_q[(RndWidth256 - 1):0] == 6'((unsigned'((prim_sha2_pkg::NumRound256 - 1))))) && ((digest_mode_flag_q == SHA2_256) || (!MultimodeEn))) || ((round_q == 7'((unsigned'((prim_sha2_pkg::NumRound512 - 1))))) && ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	1	Covered	T2,T3,T4
0	1	0	Covered	T2,T3,T4
0	0	-	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	302	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	312	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	320	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	333	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	342	case (fifo_st_q)
-2-:	344	if (hash_go)
-3-:	349	if ((!shaf_rvalid))
-4-:	353	if ((w_index_q == 4'd15))
-5-:	364	if ((msg_feed_complete && one_chunk_done))
-6-:	368	if (one_chunk_done)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
FifoIdle	1	-	-	-	-	Covered	T2,T3,T4
FifoIdle	0	-	-	-	-	Covered	T1,T2,T3
FifoLoadFromFifo	-	1	-	-	-	Covered	T2,T3,T4
FifoLoadFromFifo	-	0	1	-	-	Covered	T2,T3,T4
FifoLoadFromFifo	-	0	0	-	-	Covered	T2,T3,T4
FifoWait	-	-	-	1	-	Covered	T2,T3,T4
FifoWait	-	-	-	0	1	Covered	T2,T3,T4
FifoWait	-	-	-	0	0	Covered	T2,T3,T4
default	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	380	if ((!sha_en_i))
-2-:	383	if (hash_go)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	389	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	403	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	410	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	423	case (sha_st_q)
-2-:	425	if ((fifo_st_q == FifoWait))
-3-:	435	if (((((digest_mode_flag_q == SHA2_256) || (~MultimodeEn)) && (round_q < 7'h30)) || (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q < 7'h40))))
-4-:	439	if (one_chunk_done)
-5-:	448	if ((fifo_st_q == FifoWait))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
ShaIdle	1	-	-	-	Covered	T2,T3,T4
ShaIdle	0	-	-	-	Covered	T1,T2,T3
ShaCompress	-	1	-	-	Covered	T2,T3,T4
ShaCompress	-	0	1	-	Covered	T2,T3,T4
ShaCompress	-	0	0	-	Covered	T2,T3,T4
ShaUpdateDigest	-	-	-	1	Not Covered
ShaUpdateDigest	-	-	-	0	Covered	T2,T3,T4
default	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	461	if (((!sha_en_i) || hash_go))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	203	if (wipe_secret_i)
-2-:	205	if (((!sha_en_i) || hash_go))
-3-:	207	if (((!run_hash) && update_w_from_fifo))
-4-:	211	if (calculate_next_w)
-5-:	214	if (run_hash)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T5,T13,T14
0	1	-	-	-	Covered	T1,T2,T3
0	0	1	-	-	Covered	T2,T3,T4
0	0	0	1	-	Covered	T2,T3,T4
0	0	0	0	1	Covered	T2,T3,T4
0	0	0	0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	222	if ((!rst_ni))
-2-:	223	if ((!MultimodeEn))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

	LineNo.	Expression
-1-:	229	if (wipe_secret_i)
-2-:	233	if (init_hash)
-3-:	235	if (run_hash)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T13,T14
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	242	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	249	if (wipe_secret_i)
-2-:	253	if (hash_start_i)
-3-:	257	if (clear_digest)
-4-:	259	if ((!sha_en_i))
-5-:	263	if (update_digest)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T5,T13,T14
0	1	-	-	-	Covered	T2,T3,T4
0	0	1	-	-	Covered	T2,T5,T6
0	0	0	1	-	Covered	T1,T2,T3
0	0	0	0	1	Covered	T2,T3,T4
0	0	0	0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	272	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_prim_sha2_256.gen_sha256_logic.u_prim_sha2_256

	Line No.	Total	Covered	Percent
TOTAL		145	137	94.48
CONT_ASSIGN	66	1	0	0.00
CONT_ASSIGN	66	1	0	0.00
CONT_ASSIGN	66	1	0	0.00
CONT_ASSIGN	66	1	0	0.00
CONT_ASSIGN	66	1	0	0.00
CONT_ASSIGN	66	1	0	0.00
CONT_ASSIGN	66	1	0	0.00
CONT_ASSIGN	66	1	0	0.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	198	1	1	100.00
ALWAYS	202	11	11	100.00
ALWAYS	222	4	4	100.00
ALWAYS	228	8	8	100.00
ALWAYS	242	3	3	100.00
ALWAYS	248	15	15	100.00
ALWAYS	272	3	3	100.00
CONT_ASSIGN	278	1	1	100.00
CONT_ASSIGN	278	1	1	100.00
CONT_ASSIGN	278	1	1	100.00
CONT_ASSIGN	278	1	1	100.00
CONT_ASSIGN	278	1	1	100.00
CONT_ASSIGN	278	1	1	100.00
CONT_ASSIGN	278	1	1	100.00
CONT_ASSIGN	278	1	1	100.00
ALWAYS	285	7	7	100.00
ALWAYS	302	3	3	100.00
CONT_ASSIGN	307	1	1	100.00
ALWAYS	312	3	3	100.00
CONT_ASSIGN	317	1	1	100.00
ALWAYS	320	3	3	100.00
ALWAYS	333	3	3	100.00
ALWAYS	338	26	26	100.00
ALWAYS	389	3	3	100.00
ALWAYS	403	3	3	100.00
ALWAYS	410	3	3	100.00
CONT_ASSIGN	414	1	1	100.00
ALWAYS	417	21	21	100.00
CONT_ASSIGN	464	1	1	100.00
CONT_ASSIGN	490	1	1	100.00
CONT_ASSIGN	493	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sha2_0/rtl/prim_sha2.sv' or '../src/lowrisc_prim_sha2_0/rtl/prim_sha2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
66	0	8
69	1	1
74	1	1
76	1	1
198	1	1
202	1	1
203	1	1
204	1	1
205	1	1
206	1	1
207	1	1
210	1	1
211	1	1
212	1	1
214	1	1
216	1	1
			MISSING_ELSE
222	2	2
223	2	2
			==> MISSING_ELSE
228	1	1
229	1	1
230	1	1
231	1	1
233	1	1
234	1	1
235	1	1
236	1	1
			MISSING_ELSE
242	2	2
243	1	1
248	1	1
249	1	1
250	1	1
251	1	1
253	1	1
254	1	1
255	1	1
257	1	1
258	1	1
259	1	1
260	1	1
261	1	1
263	1	1
264	1	1
265	1	1
			MISSING_ELSE
272	2	2
273	1	1
278	8	8
285	1	1
286	1	1
287	1	1
288	1	1
289	1	1
293	1	1
295	1	1
			MISSING_ELSE
302	2	2
303	1	1
307	1	1
312	2	2
313	1	1
317	1	1
320	2	2
321	1	1
333	2	2
334	1	1
338	1	1
339	1	1
340	1	1
342	1	1
344	2	2
345	1	1
349	1	1
351	1	1
352	1	1
353	1	1
354	1	1
356	1	1
358	1	1
359	1	1
364	1	1
365	1	1
367	1	1
368	1	1
369	1	1
371	1	1
			Exclude Annotation: VC_COV_UNR
380	1	1
381	1	1
382	1	1
383	1	1
384	1	1
			MISSING_ELSE
389	2	2
390	1	1
403	2	2
404	1	1
410	2	2
411	1	1
414	1	1
417	1	1
418	1	1
419	1	1
420	1	1
421	1	1
423	1	1
425	1	1
426	1	1
427	1	1
429	1	1
434	1	1
435	1	1
438	1	1
439	1	1
440	1	1
442	1	1
447	1	1
448	1	1
449		excluded
			Exclude Annotation: VC_COV_UNR
450		excluded
			Exclude Annotation: VC_COV_UNR
452	1	1
			Exclude Annotation: VC_COV_UNR
461	2	2
			MISSING_ELSE
464	1	1
490	1	1
493	1	1

---

Cond Coverage for Instance : tb.dut.u_prim_sha2_256.gen_sha256_logic.u_prim_sha2_256

	Total	Covered	Percent
Conditions	73	70	95.89
Logical	73	70	95.89
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (hash_start_i | hash_continue_i)
             ------1-----   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T2,T3,T4

 LINE       76
 EXPRESSION (hash_go ? digest_mode_i : (hash_done_o ? None : digest_mode_flag_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       76
 SUB-EXPRESSION (hash_done_o ? None : digest_mode_flag_q)
                 -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       205
 EXPRESSION (((!sha_en_i)) || hash_go)
             ------1------    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3

 LINE       207
 EXPRESSION (((!run_hash)) && update_w_from_fifo)
             ------1------    ---------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       261
 EXPRESSION (digest_we_i[i] ? digest_i[i][31:0] : gen_256.digest256_q[i])
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       286
 EXPRESSION (((!sha_en_i)) || hash_go)
             ------1------    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3

 LINE       307
 EXPRESSION ((((~sha_en_i)) || hash_go) ? '0 : (update_w_from_fifo ? ((w_index_q + 1)) : w_index_q))
             -------------1------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       307
 SUB-EXPRESSION (((~sha_en_i)) || hash_go)
                 ------1------    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3

 LINE       307
 SUB-EXPRESSION (update_w_from_fifo ? ((w_index_q + 1)) : w_index_q)
                 ---------1--------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       353
 EXPRESSION (w_index_q == 4'd15)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       364
 EXPRESSION (msg_feed_complete && one_chunk_done)
             --------1--------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       414
 EXPRESSION (hash_start_i | (((~sha_en_i)) & sha_en_q))
             ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T6
1	0	Covered	T2,T3,T4

 LINE       414
 SUB-EXPRESSION (((~sha_en_i)) & sha_en_q)
                 ------1------   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T5,T6

 LINE       425
 EXPRESSION (fifo_st_q == FifoWait)
            -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       435
 EXPRESSION 
 Number  Term
      1  ((((digest_mode_flag_q == SHA2_256) || (~MultimodeEn))) && (round_q < 7'h30)) || 
      2  (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q < 7'h40)))

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Covered	T2,T3,T4
0	1	Excluded		VC_COV_UNR
1	0	Covered	T2,T3,T4

 LINE       435
 SUB-EXPRESSION ((((digest_mode_flag_q == SHA2_256) || (~MultimodeEn))) && (round_q < 7'h30))
                 ---------------------------1--------------------------    --------2--------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       435
 SUB-EXPRESSION (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q < 7'h40))
                 -----------------------------------1----------------------------------    --------2--------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T2,T3,T4
1	0	Excluded		VC_COV_UNR
1	1	Excluded		VC_COV_UNR

 LINE       435
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
                 ----------------1---------------    ----------------2---------------

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Covered	T2,T3,T4
0	1	Excluded		VC_COV_UNR
1	0	Excluded		VC_COV_UNR

 LINE       435
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------

-1-	Status	Tests	Exclude Annotation
0	Covered	T2,T3,T4
1	Excluded		VC_COV_UNR

 LINE       435
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------

-1-	Status	Tests	Exclude Annotation
0	Covered	T2,T3,T4
1	Excluded		VC_COV_UNR

 LINE       448
 EXPRESSION (fifo_st_q == FifoWait)
            -----------1-----------

-1-	Status	Tests	Exclude Annotation
0	Covered	T2,T3,T4
1	Excluded		VC_COV_UNR

 LINE       461
 EXPRESSION (((!sha_en_i)) || hash_go)
             ------1------    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3

 LINE       464
 EXPRESSION 
 Number  Term
      1  ((((digest_mode_flag_q == SHA2_256) || (~MultimodeEn))) && (round_q == 7'd63)) ? 1'b1 : ((((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q == 7'd79)) ? 1'b1 : 1'b0))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       464
 SUB-EXPRESSION ((((digest_mode_flag_q == SHA2_256) || (~MultimodeEn))) && (round_q == 7'd63))
                 ---------------------------1--------------------------    ---------2--------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       464
 SUB-EXPRESSION (round_q == 7'd63)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       464
 SUB-EXPRESSION ((((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q == 7'd79)) ? 1'b1 : 1'b0)
                 -----------------------------------------------1----------------------------------------------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T2,T3
1	Excluded		VC_COV_UNR

 LINE       464
 SUB-EXPRESSION (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q == 7'd79))
                 -----------------------------------1----------------------------------    ---------2--------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Excluded		VC_COV_UNR
1	1	Excluded		VC_COV_UNR

 LINE       464
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
                 ----------------1---------------    ----------------2---------------

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Covered	T1,T2,T3
0	1	Excluded		VC_COV_UNR
1	0	Excluded		VC_COV_UNR

 LINE       464
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T2,T3
1	Excluded		VC_COV_UNR

 LINE       464
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T2,T3
1	Excluded		VC_COV_UNR

 LINE       464
 SUB-EXPRESSION (round_q == 7'd79)
                ---------1--------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T2,T3
1	Excluded		VC_COV_UNR

 LINE       490
 EXPRESSION (init_hash | run_hash | update_digest)
             ----1----   ----2---   ------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	1	0	Covered	T2,T3,T4
1	0	0	Covered	T2,T3,T4

 LINE       493
 EXPRESSION ((fifo_st_q == FifoIdle) && (sha_st_q == ShaIdle) && ((!hash_go)))
             -----------1-----------    ----------2----------    ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T2,T3,T4
1	1	0	Covered	T2,T3,T4
1	1	1	Covered	T1,T2,T3

 LINE       493
 SUB-EXPRESSION (fifo_st_q == FifoIdle)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       493
 SUB-EXPRESSION (sha_st_q == ShaIdle)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_prim_sha2_256.gen_sha256_logic.u_prim_sha2_256

Summary for FSM :: fifo_st_q

	Total	Covered	Percent
States	3	3	100.00	(Not included in score)
Transitions	5	5	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: fifo_st_q

---

states	Line No.	Covered	Tests
FifoIdle	338	Covered	T1,T2,T3
FifoLoadFromFifo	344	Covered	T2,T3,T4
FifoWait	354	Covered	T2,T3,T4

transitions	Line No.	Covered	Tests
FifoIdle->FifoLoadFromFifo	344	Covered	T2,T3,T4
FifoLoadFromFifo->FifoIdle	338	Covered	T5,T33,T35
FifoLoadFromFifo->FifoWait	354	Covered	T2,T3,T4
FifoWait->FifoIdle	338	Covered	T2,T3,T4
FifoWait->FifoLoadFromFifo	369	Covered	T2,T3,T4

Summary for FSM :: sha_st_q

	Total	Covered	Percent
States	3	3	100.00	(Not included in score)
Transitions	4	4	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: sha_st_q

---

states	Line No.	Covered	Tests
ShaCompress	427	Covered	T2,T3,T4
ShaIdle	429	Covered	T1,T2,T3
ShaUpdateDigest	440	Covered	T2,T3,T4

transitions	Line No.	Covered	Tests	Exclude Annotation
ShaCompress->ShaIdle	461	Covered	T5,T11,T12
ShaCompress->ShaUpdateDigest	440	Covered	T2,T3,T4
ShaIdle->ShaCompress	427	Covered	T2,T3,T4
ShaUpdateDigest->ShaCompress	450	Excluded		VC_COV_UNR
ShaUpdateDigest->ShaIdle	452	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_prim_sha2_256.gen_sha256_logic.u_prim_sha2_256

	Line No.	Total	Covered	Percent
Branches		68	67	98.53
TERNARY	76	3	3	100.00
TERNARY	307	3	3	100.00
TERNARY	464	2	2	100.00
IF	286	4	4	100.00
IF	302	2	2	100.00
IF	312	2	2	100.00
IF	320	2	2	100.00
IF	333	2	2	100.00
CASE	342	9	8	88.89
IF	380	3	3	100.00
IF	389	2	2	100.00
IF	403	2	2	100.00
IF	410	2	2	100.00
CASE	423	6	6	100.00
IF	461	2	2	100.00
IF	203	6	6	100.00
IF	222	2	2	100.00
IF	229	4	4	100.00
IF	242	2	2	100.00
IF	249	6	6	100.00
IF	272	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_sha2_0/rtl/prim_sha2.sv' or '../src/lowrisc_prim_sha2_0/rtl/prim_sha2.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	(hash_go) ? 
-2-:	76	(hash_done_o) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	307	(((~sha_en_i) || hash_go)) ? 
-2-:	307	(update_w_from_fifo) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	464	((((digest_mode_flag_q == SHA2_256) || (~MultimodeEn)) && (round_q == 7'd63))) ? 
-2-:	464	((((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q == 7'd79))) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T3,T4
0	1	Excluded		VC_COV_UNR
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	286	if (((!sha_en_i) || hash_go))
-2-:	288	if (run_hash)
-3-:	289	if ((((round_q[(RndWidth256 - 1):0] == 6'((unsigned'((prim_sha2_pkg::NumRound256 - 1))))) && ((digest_mode_flag_q == SHA2_256) || (!MultimodeEn))) || ((round_q == 7'((unsigned'((prim_sha2_pkg::NumRound512 - 1))))) && ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	1	Covered	T2,T3,T4
0	1	0	Covered	T2,T3,T4
0	0	-	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	302	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	312	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	320	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	333	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	342	case (fifo_st_q)
-2-:	344	if (hash_go)
-3-:	349	if ((!shaf_rvalid))
-4-:	353	if ((w_index_q == 4'd15))
-5-:	364	if ((msg_feed_complete && one_chunk_done))
-6-:	368	if (one_chunk_done)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
FifoIdle	1	-	-	-	-	Covered	T2,T3,T4
FifoIdle	0	-	-	-	-	Covered	T1,T2,T3
FifoLoadFromFifo	-	1	-	-	-	Covered	T2,T3,T4
FifoLoadFromFifo	-	0	1	-	-	Covered	T2,T3,T4
FifoLoadFromFifo	-	0	0	-	-	Covered	T2,T3,T4
FifoWait	-	-	-	1	-	Covered	T2,T3,T4
FifoWait	-	-	-	0	1	Covered	T2,T3,T4
FifoWait	-	-	-	0	0	Covered	T2,T3,T4
default	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	380	if ((!sha_en_i))
-2-:	383	if (hash_go)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	389	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	403	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	410	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	423	case (sha_st_q)
-2-:	425	if ((fifo_st_q == FifoWait))
-3-:	435	if (((((digest_mode_flag_q == SHA2_256) || (~MultimodeEn)) && (round_q < 7'h30)) || (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q < 7'h40))))
-4-:	439	if (one_chunk_done)
-5-:	448	if ((fifo_st_q == FifoWait))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests	Exclude Annotation
ShaIdle	1	-	-	-	Covered	T2,T3,T4
ShaIdle	0	-	-	-	Covered	T1,T2,T3
ShaCompress	-	1	-	-	Covered	T2,T3,T4
ShaCompress	-	0	1	-	Covered	T2,T3,T4
ShaCompress	-	0	0	-	Covered	T2,T3,T4
ShaUpdateDigest	-	-	-	1	Excluded		VC_COV_UNR
ShaUpdateDigest	-	-	-	0	Covered	T2,T3,T4
default	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	461	if (((!sha_en_i) || hash_go))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	203	if (wipe_secret_i)
-2-:	205	if (((!sha_en_i) || hash_go))
-3-:	207	if (((!run_hash) && update_w_from_fifo))
-4-:	211	if (calculate_next_w)
-5-:	214	if (run_hash)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T5,T13,T14
0	1	-	-	-	Covered	T1,T2,T3
0	0	1	-	-	Covered	T2,T3,T4
0	0	0	1	-	Covered	T2,T3,T4
0	0	0	0	1	Covered	T2,T3,T4
0	0	0	0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	222	if ((!rst_ni))
-2-:	223	if ((!MultimodeEn))

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	229	if (wipe_secret_i)
-2-:	233	if (init_hash)
-3-:	235	if (run_hash)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T13,T14
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	242	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	249	if (wipe_secret_i)
-2-:	253	if (hash_start_i)
-3-:	257	if (clear_digest)
-4-:	259	if ((!sha_en_i))
-5-:	263	if (update_digest)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T5,T13,T14
0	1	-	-	-	Covered	T2,T3,T4
0	0	1	-	-	Covered	T2,T5,T6
0	0	0	1	-	Covered	T1,T2,T3
0	0	0	0	1	Covered	T2,T3,T4
0	0	0	0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	272	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3