Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
84.84	95.88	84.97	100.00	40.00	88.17	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	433581682	1562857	0	0
intr_enable_rd_A	433581682	4425	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433581682	1562857	0	0
T7	0	268507	0	0
T8	0	18163	0	0
T9	0	74664	0	0
T10	367806	151618	0	0
T11	0	94773	0	0
T12	0	222371	0	0
T25	0	121851	0	0
T38	0	8	0	0
T48	0	25	0	0
T49	0	92282	0	0
T50	760340	0	0	0
T51	723	0	0	0
T52	34069	0	0	0
T53	100035	0	0	0
T54	4333	0	0	0
T55	218846	0	0	0
T56	822851	0	0	0
T57	377263	0	0	0
T58	128529	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433581682	4425	0	0
T19	900	0	0	0
T26	1877	17	0	0
T27	177015	0	0	0
T44	271231	0	0	0
T45	9854	0	0	0
T46	166470	0	0	0
T59	0	28	0	0
T60	0	31	0	0
T61	0	25	0	0
T62	0	53	0	0
T63	0	14	0	0
T64	0	72	0	0
T65	0	10	0	0
T66	0	45	0	0
T67	0	44	0	0
T68	6611	0	0	0
T69	16370	0	0	0
T70	2518	0	0	0
T71	855072	0	0	0