Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	6843273	1			T1	36		T3	32342		T4	16432
all_values[1]	6843273	1			T1	36		T3	32342		T4	16432
all_values[2]	6843273	1			T1	36		T3	32342		T4	16432

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

54350

1

T3

11

T7

177

T14

772

auto[1]

20475469

1

T1

108

T3

97015

T4

49296

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18694581

1

T1

104

T3

82658

T4

38938

auto[1]

1835238

1

T1

4

T3

14368

T4

10358

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	20460	1			T3	7		T7	175		T84	436
all_values[0]	auto[0]	auto[1]	207	1			T7	2		T22	2		T110	2
all_values[0]	auto[1]	auto[0]	6805329	1			T1	32		T3	32313		T4	16417
all_values[0]	auto[1]	auto[1]	17277	1			T1	4		T3	22		T4	15
all_values[1]	auto[0]	auto[0]	10155	1			T14	772		T16	12		T108	383
all_values[1]	auto[0]	auto[1]	108	1			T10	1		T53	2		T11	6
all_values[1]	auto[1]	auto[0]	6832872	1			T1	36		T3	32342		T4	16432
all_values[1]	auto[1]	auto[1]	138	1			T33	2		T123	1		T124	2
all_values[2]	auto[0]	auto[0]	13529	1			T3	2		T15	32		T16	12
all_values[2]	auto[0]	auto[1]	9891	1			T3	2		T28	278		T84	435
all_values[2]	auto[1]	auto[0]	5012236	1			T1	36		T3	17994		T4	6089
all_values[2]	auto[1]	auto[1]	1807617	1			T3	14344		T4	10343		T5	17