Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	16956249	1			T3	1044		T4	1937		T5	137
all_values[1]	16956249	1			T3	1044		T4	1937		T5	137
all_values[2]	16956249	1			T3	1044		T4	1937		T5	137

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Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

233877

1

T3

89

T4

102

T13

135

auto[1]

50634870

1

T3

3043

T4

5709

T5

411

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Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

43458889

1

T3

2693

T4

5031

T5

357

auto[1]

7409858

1

T3

439

T4

780

T5

54

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Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	99454	1			T3	87		T4	102		T13	79
all_values[0]	auto[0]	auto[1]	320	1			T3	2		T13	2		T12	2
all_values[0]	auto[1]	auto[0]	16837836	1			T3	943		T4	1805		T5	135
all_values[0]	auto[1]	auto[1]	18639	1			T3	12		T4	30		T5	2
all_values[1]	auto[0]	auto[0]	51837	1			T13	54		T8	1650		T45	55
all_values[1]	auto[0]	auto[1]	165	1			T20	3		T31	4		T65	4
all_values[1]	auto[1]	auto[0]	16903990	1			T3	1044		T4	1937		T5	137
all_values[1]	auto[1]	auto[1]	257	1			T6	2		T49	3		T46	2
all_values[2]	auto[0]	auto[0]	40383	1			T14	1		T30	557		T12	626
all_values[2]	auto[0]	auto[1]	41718	1			T14	4		T30	547		T133	44
all_values[2]	auto[1]	auto[0]	9525389	1			T3	619		T4	1187		T5	85
all_values[2]	auto[1]	auto[1]	7348759	1			T3	425		T4	750		T5	52