Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	20637835	1			T1	90		T3	27		T4	895
all_values[1]	20637835	1			T1	90		T3	27		T4	895
all_values[2]	20637835	1			T1	90		T3	27		T4	895

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Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

323758

1

T1

90

T4

90

T5

192

auto[1]

61589747

1

T1

180

T3

81

T4

2595

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

52781587

1

T1

268

T3

57

T4

2416

auto[1]

9131918

1

T1

2

T3

24

T4

269

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Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	96159	1			T1	88		T24	972		T75	863
all_values[0]	auto[0]	auto[1]	450	1			T1	2		T147	6		T12	1
all_values[0]	auto[1]	auto[0]	20518885	1			T3	27		T4	882		T5	1978
all_values[0]	auto[1]	auto[1]	22341	1			T4	13		T5	2		T6	23
all_values[1]	auto[0]	auto[0]	122791	1			T4	90		T24	972		T34	93
all_values[1]	auto[0]	auto[1]	241	1			T12	1		T40	1		T13	3
all_values[1]	auto[1]	auto[0]	20514377	1			T1	90		T3	27		T4	805
all_values[1]	auto[1]	auto[1]	426	1			T12	2		T39	2		T40	1
all_values[2]	auto[0]	auto[0]	51792	1			T5	1		T140	4655		T34	93
all_values[2]	auto[0]	auto[1]	52325	1			T5	191		T146	561		T12	1
all_values[2]	auto[1]	auto[0]	11477583	1			T1	90		T3	3		T4	639
all_values[2]	auto[1]	auto[1]	9056135	1			T3	24		T4	256		T5	1370