Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.03 95.40 97.17 100.00 97.06 98.27 98.48 99.85


Total tests in report: 660
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
86.20 86.20 93.41 93.41 88.93 88.93 95.80 95.80 82.35 82.35 94.19 94.19 93.16 93.16 55.56 55.56 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/0.hmac_smoke.1792267734
90.74 4.54 94.26 0.85 95.03 6.10 97.50 1.70 88.24 5.88 95.29 1.10 94.68 1.52 70.18 14.62 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/0.hmac_stress_all_with_rand_reset.981833871
92.76 2.02 94.45 0.19 95.19 0.16 97.50 0.00 91.18 2.94 95.76 0.47 94.68 0.00 80.56 10.38 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/2.hmac_long_msg.1020489591
93.74 0.98 94.88 0.43 95.35 0.16 97.73 0.23 91.18 0.00 96.70 0.94 94.94 0.25 85.38 4.82 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/0.hmac_wipe_secret.3535608584
94.62 0.88 94.88 0.00 95.35 0.00 97.73 0.00 97.06 5.88 96.70 0.00 94.94 0.00 85.67 0.29 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/8.hmac_stress_all_with_rand_reset.813962682
95.22 0.60 94.97 0.09 95.56 0.21 98.41 0.68 97.06 0.00 97.02 0.31 94.94 0.00 88.60 2.92 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_tl_intg_err.3275366556
95.66 0.44 94.97 0.00 95.99 0.43 98.41 0.00 97.06 0.00 97.33 0.31 94.94 0.00 90.94 2.34 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/12.hmac_stress_all.1846015974
96.09 0.43 95.12 0.14 96.20 0.21 98.41 0.00 97.06 0.00 97.65 0.31 94.94 0.00 93.27 2.34 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/2.hmac_error.4045288471
96.47 0.37 95.12 0.00 96.31 0.11 99.77 1.36 97.06 0.00 97.80 0.16 95.19 0.25 94.01 0.73 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/3.hmac_sec_cm.3394861044
96.74 0.28 95.12 0.00 96.36 0.05 99.77 0.00 97.06 0.00 97.80 0.00 95.19 0.00 95.91 1.90 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/5.hmac_smoke.142900346
97.00 0.25 95.26 0.14 96.58 0.21 99.77 0.00 97.06 0.00 97.96 0.16 96.46 1.27 95.91 0.00 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/18.hmac_back_pressure.1587477292
97.22 0.22 95.26 0.00 96.58 0.00 99.77 0.00 97.06 0.00 97.96 0.00 97.97 1.52 95.91 0.00 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_aliasing.2374928608
97.38 0.16 95.26 0.00 96.68 0.11 99.77 0.00 97.06 0.00 97.96 0.00 97.97 0.00 96.93 1.02 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/21.hmac_burst_wr.358746863
97.50 0.13 95.26 0.00 96.84 0.16 99.77 0.00 97.06 0.00 97.96 0.00 97.97 0.00 97.66 0.73 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/0.hmac_test_hmac512_vectors.1699645871
97.60 0.09 95.31 0.05 97.01 0.16 99.77 0.00 97.06 0.00 98.12 0.16 97.97 0.00 97.95 0.29 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/0.hmac_error.1889339520
97.69 0.09 95.35 0.05 97.01 0.00 99.77 0.00 97.06 0.00 98.27 0.16 97.97 0.00 98.39 0.44 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/8.hmac_back_pressure.763379555
97.75 0.06 95.35 0.00 97.01 0.00 99.77 0.00 97.06 0.00 98.27 0.00 97.97 0.00 98.83 0.44 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_tl_intg_err.2794014547
97.81 0.06 95.35 0.00 97.01 0.00 99.77 0.00 97.06 0.00 98.27 0.00 98.23 0.25 98.98 0.15 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/11.hmac_stress_all.3577210655
97.87 0.06 95.35 0.00 97.17 0.16 100.00 0.23 97.06 0.00 98.27 0.00 98.23 0.00 98.98 0.00 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/2.hmac_alert_test.2103678868
97.91 0.04 95.35 0.00 97.17 0.00 100.00 0.00 97.06 0.00 98.27 0.00 98.23 0.00 99.27 0.29 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/1.hmac_long_msg.837389975
97.95 0.04 95.35 0.00 97.17 0.00 100.00 0.00 97.06 0.00 98.27 0.00 98.23 0.00 99.56 0.29 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/2.hmac_wipe_secret.414264623
97.98 0.04 95.35 0.00 97.17 0.00 100.00 0.00 97.06 0.00 98.27 0.00 98.48 0.25 99.56 0.00 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_rw.1209751565
98.01 0.02 95.35 0.00 97.17 0.00 100.00 0.00 97.06 0.00 98.27 0.00 98.48 0.00 99.71 0.15 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_tl_intg_err.879073526
98.03 0.02 95.35 0.00 97.17 0.00 100.00 0.00 97.06 0.00 98.27 0.00 98.48 0.00 99.85 0.15 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/11.hmac_burst_wr.2096737222
98.03 0.01 95.40 0.05 97.17 0.00 100.00 0.00 97.06 0.00 98.27 0.00 98.48 0.00 99.85 0.00 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/0.hmac_alert_test.123151696


Tests that do not contribute to grading

Name   
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_aliasing.784490676
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_bit_bash.2567897376
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_hw_reset.2844291648
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.26408637
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_intr_test.849151325
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_same_csr_outstanding.1702366893
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_tl_errors.3287741721
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_bit_bash.4141689266
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_hw_reset.2577792571
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2557741876
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_rw.1456730248
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_intr_test.1234282180
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_same_csr_outstanding.2885144719
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_tl_errors.4148276546
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_tl_intg_err.999798325
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.2158649939
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_csr_rw.1976133345
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_intr_test.245511589
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_same_csr_outstanding.1263406200
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_tl_errors.1136331309
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_tl_intg_err.1454733855
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.1138886863
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_csr_rw.30971634
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_intr_test.1074903466
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_same_csr_outstanding.4003154626
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_tl_errors.205464800
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_tl_intg_err.917418564
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.3650022882
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_csr_rw.3648048777
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_intr_test.114469407
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_same_csr_outstanding.270034348
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_tl_errors.2448386412
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.476668119
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_csr_rw.1186856201
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_intr_test.1230163676
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_same_csr_outstanding.381435623
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_tl_errors.3018832712
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_tl_intg_err.3740020761
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.1990036279
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_csr_rw.1327634869
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_intr_test.3903956231
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_same_csr_outstanding.2423667576
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_tl_errors.3259818792
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_tl_intg_err.276950439
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.2971023491
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_csr_rw.3850051483
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_intr_test.2653531533
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_same_csr_outstanding.1373589965
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_tl_errors.663267083
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_tl_intg_err.3013271060
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.2389080415
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_csr_rw.4274473316
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_intr_test.334137517
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_same_csr_outstanding.2402790407
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_tl_errors.823039862
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_tl_intg_err.2264372386
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.968405911
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_csr_rw.2138456766
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_intr_test.3418351498
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_same_csr_outstanding.1180415168
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_tl_errors.1170921858
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_tl_intg_err.556223751
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.3410975784
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_csr_rw.2706028495
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_intr_test.1833883479
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_same_csr_outstanding.2455226578
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_tl_errors.4229956868
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_tl_intg_err.1255998630
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.3987079922
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_csr_rw.2189458225
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_intr_test.2050999625
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_same_csr_outstanding.1214368230
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_tl_errors.3771140033
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_tl_intg_err.2451905876
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_aliasing.3138028751
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_bit_bash.2374483775
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_hw_reset.3181108851
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.2346103313
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_rw.413375573
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_intr_test.1348806597
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_same_csr_outstanding.3530051716
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_tl_errors.3626029250
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_tl_intg_err.384684464
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/20.hmac_intr_test.2840072224
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/21.hmac_intr_test.285476140
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/22.hmac_intr_test.4233137271
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/23.hmac_intr_test.1771525274
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/24.hmac_intr_test.1152263864
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/25.hmac_intr_test.2806203308
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/26.hmac_intr_test.2305334591
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/27.hmac_intr_test.2497983364
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/28.hmac_intr_test.3703954297
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/29.hmac_intr_test.2052143352
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_aliasing.3184948800
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_bit_bash.2568006615
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_hw_reset.3520994664
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.626911508
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_rw.3818719312
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_intr_test.45672716
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_same_csr_outstanding.2769802020
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_tl_errors.1924628524
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/30.hmac_intr_test.3807369937
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/31.hmac_intr_test.438738316
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/32.hmac_intr_test.987890620
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/33.hmac_intr_test.3318872497
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/34.hmac_intr_test.3538399370
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/35.hmac_intr_test.3599624041
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/36.hmac_intr_test.2868388162
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/37.hmac_intr_test.382886818
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/38.hmac_intr_test.2535397815
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/39.hmac_intr_test.3223793780
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_aliasing.2200074246
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_bit_bash.3766517127
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_hw_reset.309058435
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.3827600645
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/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/4.hmac_test_sha256_vectors.643468840
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/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/44.hmac_back_pressure.3431751737
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/44.hmac_burst_wr.2428975233
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/44.hmac_datapath_stress.3013209768
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/44.hmac_error.921002447
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/44.hmac_long_msg.375804691
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/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/47.hmac_alert_test.1535574354
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/47.hmac_back_pressure.532499424
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/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/47.hmac_datapath_stress.2326272119
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/47.hmac_error.1410042612
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/47.hmac_long_msg.2714054224
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/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/48.hmac_alert_test.2572512573
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/48.hmac_back_pressure.504762359
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/48.hmac_burst_wr.80135640
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/48.hmac_datapath_stress.3650854779
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/48.hmac_error.3380739048
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/48.hmac_long_msg.634077872
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/48.hmac_smoke.3708418174
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/48.hmac_stress_all.2659451401
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/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/49.hmac_alert_test.1096917890
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/49.hmac_back_pressure.3302187006
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/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/49.hmac_error.3349072271
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/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/49.hmac_smoke.322169715
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/49.hmac_stress_all.2001641260
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/49.hmac_wipe_secret.3586322569
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/5.hmac_alert_test.4290174269
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/5.hmac_back_pressure.777552080
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/5.hmac_burst_wr.3673005379
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/5.hmac_datapath_stress.2390411849
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/5.hmac_error.1408878699
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/5.hmac_long_msg.196773349
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/5.hmac_stress_all.3295639339
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/5.hmac_stress_all_with_rand_reset.3555716525
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/5.hmac_wipe_secret.2349539235
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/6.hmac_alert_test.2457896635
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/6.hmac_back_pressure.16913914
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/6.hmac_burst_wr.331430258
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/6.hmac_datapath_stress.3507124775
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/6.hmac_error.3367690913
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/6.hmac_long_msg.3509974160
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/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/7.hmac_datapath_stress.3489328591
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/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/7.hmac_long_msg.2257419996
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/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/7.hmac_wipe_secret.1292429087
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/8.hmac_alert_test.603027198
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/8.hmac_burst_wr.3072387409
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/8.hmac_datapath_stress.2941948447
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/8.hmac_error.2763491169
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/8.hmac_long_msg.1596724400
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/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/8.hmac_wipe_secret.525371023
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/9.hmac_alert_test.2570087904
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/9.hmac_back_pressure.2867680842
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/9.hmac_burst_wr.1756503138
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/9.hmac_datapath_stress.4281718522
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/9.hmac_error.3056102947
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/9.hmac_long_msg.3363035807
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/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/9.hmac_stress_all.1550765393
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/9.hmac_stress_all_with_rand_reset.495748101
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/9.hmac_wipe_secret.1737899884




Total test records in report: 660
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html

TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/11.hmac_smoke.1274293769 Feb 09 07:41:50 AM UTC 25 Feb 09 07:41:53 AM UTC 25 885152268 ps
T2 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/0.hmac_alert_test.123151696 Feb 09 07:36:15 AM UTC 25 Feb 09 07:36:17 AM UTC 25 32266988 ps
T3 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/0.hmac_burst_wr.1968481927 Feb 09 07:36:15 AM UTC 25 Feb 09 07:36:18 AM UTC 25 82813801 ps
T18 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/0.hmac_sec_cm.1448394714 Feb 09 07:36:15 AM UTC 25 Feb 09 07:36:18 AM UTC 25 32604364 ps
T4 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/1.hmac_smoke.2281725199 Feb 09 07:36:15 AM UTC 25 Feb 09 07:36:24 AM UTC 25 1872900839 ps
T19 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/1.hmac_alert_test.1371857644 Feb 09 07:36:26 AM UTC 25 Feb 09 07:36:27 AM UTC 25 21160398 ps
T5 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/0.hmac_back_pressure.2991501338 Feb 09 07:36:15 AM UTC 25 Feb 09 07:36:28 AM UTC 25 228001184 ps
T20 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/1.hmac_sec_cm.3396265849 Feb 09 07:36:26 AM UTC 25 Feb 09 07:36:28 AM UTC 25 128145626 ps
T6 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/0.hmac_smoke.1792267734 Feb 09 07:36:15 AM UTC 25 Feb 09 07:36:31 AM UTC 25 2663060346 ps
T7 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/1.hmac_burst_wr.4174378842 Feb 09 07:36:19 AM UTC 25 Feb 09 07:36:36 AM UTC 25 6122727300 ps
T8 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/2.hmac_burst_wr.810389450 Feb 09 07:36:32 AM UTC 25 Feb 09 07:36:39 AM UTC 25 1179935020 ps
T9 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/2.hmac_smoke.2635673844 Feb 09 07:36:29 AM UTC 25 Feb 09 07:36:47 AM UTC 25 3803369189 ps
T11 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/2.hmac_back_pressure.2200034379 Feb 09 07:36:29 AM UTC 25 Feb 09 07:36:50 AM UTC 25 1460769712 ps
T21 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/0.hmac_error.1889339520 Feb 09 07:36:15 AM UTC 25 Feb 09 07:36:52 AM UTC 25 2975220530 ps
T22 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/1.hmac_wipe_secret.556952662 Feb 09 07:36:19 AM UTC 25 Feb 09 07:37:01 AM UTC 25 6427797230 ps
T76 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/2.hmac_sec_cm.3142272622 Feb 09 07:37:02 AM UTC 25 Feb 09 07:37:04 AM UTC 25 82772469 ps
T72 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/2.hmac_alert_test.2103678868 Feb 09 07:37:03 AM UTC 25 Feb 09 07:37:05 AM UTC 25 14392417 ps
T10 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/1.hmac_back_pressure.6323879 Feb 09 07:36:18 AM UTC 25 Feb 09 07:37:07 AM UTC 25 3430003410 ps
T157 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/3.hmac_smoke.1166007598 Feb 09 07:37:05 AM UTC 25 Feb 09 07:37:08 AM UTC 25 32827466 ps
T25 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/0.hmac_long_msg.977207258 Feb 09 07:36:15 AM UTC 25 Feb 09 07:37:11 AM UTC 25 10535291050 ps
T23 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/0.hmac_wipe_secret.3535608584 Feb 09 07:36:15 AM UTC 25 Feb 09 07:37:13 AM UTC 25 3621156473 ps
T26 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/1.hmac_long_msg.837389975 Feb 09 07:36:18 AM UTC 25 Feb 09 07:37:14 AM UTC 25 867914586 ps
T138 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/0.hmac_test_hmac384_vectors.2934390311 Feb 09 07:36:15 AM UTC 25 Feb 09 07:37:14 AM UTC 25 26760940354 ps
T27 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/2.hmac_wipe_secret.414264623 Feb 09 07:36:38 AM UTC 25 Feb 09 07:37:16 AM UTC 25 2095971908 ps
T28 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/3.hmac_burst_wr.648944141 Feb 09 07:37:13 AM UTC 25 Feb 09 07:37:22 AM UTC 25 196358431 ps
T67 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/2.hmac_error.4045288471 Feb 09 07:36:37 AM UTC 25 Feb 09 07:37:34 AM UTC 25 11783667450 ps
T139 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/1.hmac_test_hmac384_vectors.2629783082 Feb 09 07:36:21 AM UTC 25 Feb 09 07:37:35 AM UTC 25 8116087534 ps
T68 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/1.hmac_test_hmac256_vectors.29911676 Feb 09 07:36:19 AM UTC 25 Feb 09 07:37:36 AM UTC 25 10941462162 ps
T140 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/0.hmac_datapath_stress.1271953583 Feb 09 07:36:15 AM UTC 25 Feb 09 07:37:36 AM UTC 25 2227214173 ps
T77 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/3.hmac_sec_cm.3394861044 Feb 09 07:37:36 AM UTC 25 Feb 09 07:37:38 AM UTC 25 78465097 ps
T73 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/3.hmac_alert_test.2724525450 Feb 09 07:37:38 AM UTC 25 Feb 09 07:37:40 AM UTC 25 12966474 ps
T30 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/3.hmac_back_pressure.3194239792 Feb 09 07:37:08 AM UTC 25 Feb 09 07:37:44 AM UTC 25 465417929 ps
T71 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/0.hmac_test_hmac512_vectors.1699645871 Feb 09 07:36:15 AM UTC 25 Feb 09 07:37:46 AM UTC 25 7259181723 ps
T24 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/3.hmac_wipe_secret.306079615 Feb 09 07:37:15 AM UTC 25 Feb 09 07:37:52 AM UTC 25 1645867443 ps
T34 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/4.hmac_smoke.3652036992 Feb 09 07:37:38 AM UTC 25 Feb 09 07:37:55 AM UTC 25 972552525 ps
T174 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/0.hmac_test_hmac256_vectors.3915380277 Feb 09 07:36:15 AM UTC 25 Feb 09 07:38:01 AM UTC 25 7135273129 ps
T175 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/2.hmac_test_hmac384_vectors.1539401758 Feb 09 07:36:48 AM UTC 25 Feb 09 07:38:02 AM UTC 25 17947196481 ps
T176 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/2.hmac_test_hmac256_vectors.1185238003 Feb 09 07:36:48 AM UTC 25 Feb 09 07:38:02 AM UTC 25 1607641461 ps
T177 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/3.hmac_test_hmac256_vectors.1198449286 Feb 09 07:37:18 AM UTC 25 Feb 09 07:38:11 AM UTC 25 12260568666 ps
T78 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/4.hmac_sec_cm.3159521633 Feb 09 07:38:24 AM UTC 25 Feb 09 07:38:26 AM UTC 25 36659777 ps
T74 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/4.hmac_alert_test.2052877422 Feb 09 07:38:26 AM UTC 25 Feb 09 07:38:29 AM UTC 25 17141980 ps
T178 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/2.hmac_test_hmac512_vectors.1672222373 Feb 09 07:36:51 AM UTC 25 Feb 09 07:38:30 AM UTC 25 5027745492 ps
T173 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/3.hmac_test_hmac512_vectors.2444525542 Feb 09 07:37:23 AM UTC 25 Feb 09 07:38:32 AM UTC 25 2134010179 ps
T179 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/1.hmac_test_hmac512_vectors.4084525781 Feb 09 07:36:21 AM UTC 25 Feb 09 07:38:39 AM UTC 25 9832684097 ps
T29 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/4.hmac_burst_wr.3126430324 Feb 09 07:37:40 AM UTC 25 Feb 09 07:38:42 AM UTC 25 13661580060 ps
T61 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/4.hmac_back_pressure.209143385 Feb 09 07:37:39 AM UTC 25 Feb 09 07:38:42 AM UTC 25 4142130140 ps
T60 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/5.hmac_smoke.142900346 Feb 09 07:38:27 AM UTC 25 Feb 09 07:38:43 AM UTC 25 478793511 ps
T171 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/5.hmac_burst_wr.3673005379 Feb 09 07:38:41 AM UTC 25 Feb 09 07:38:46 AM UTC 25 482504219 ps
T75 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/5.hmac_error.1408878699 Feb 09 07:38:42 AM UTC 25 Feb 09 07:38:57 AM UTC 25 517443369 ps
T69 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/3.hmac_error.4288043407 Feb 09 07:37:13 AM UTC 25 Feb 09 07:38:59 AM UTC 25 33637887766 ps
T180 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/5.hmac_alert_test.4290174269 Feb 09 07:38:57 AM UTC 25 Feb 09 07:38:59 AM UTC 25 19552704 ps
T181 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/4.hmac_test_hmac256_vectors.472638403 Feb 09 07:38:04 AM UTC 25 Feb 09 07:39:03 AM UTC 25 51995495841 ps
T146 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/4.hmac_wipe_secret.2984002400 Feb 09 07:37:47 AM UTC 25 Feb 09 07:39:08 AM UTC 25 6999235857 ps
T62 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/5.hmac_back_pressure.777552080 Feb 09 07:38:32 AM UTC 25 Feb 09 07:39:09 AM UTC 25 915136969 ps
T147 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/2.hmac_long_msg.1020489591 Feb 09 07:36:29 AM UTC 25 Feb 09 07:39:13 AM UTC 25 2777358959 ps
T172 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/3.hmac_long_msg.3533778336 Feb 09 07:37:06 AM UTC 25 Feb 09 07:39:14 AM UTC 25 2432618165 ps
T158 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/6.hmac_smoke.2500857279 Feb 09 07:38:58 AM UTC 25 Feb 09 07:39:15 AM UTC 25 275577466 ps
T161 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/4.hmac_stress_all.2240386030 Feb 09 07:38:06 AM UTC 25 Feb 09 07:39:18 AM UTC 25 10256726001 ps
T182 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/6.hmac_alert_test.2457896635 Feb 09 07:39:16 AM UTC 25 Feb 09 07:39:18 AM UTC 25 42006519 ps
T70 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/4.hmac_error.4025099325 Feb 09 07:37:45 AM UTC 25 Feb 09 07:39:23 AM UTC 25 6442683906 ps
T183 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/7.hmac_long_msg.2257419996 Feb 09 07:39:18 AM UTC 25 Feb 09 07:39:27 AM UTC 25 1198586602 ps
T12 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/0.hmac_stress_all_with_rand_reset.981833871 Feb 09 07:36:15 AM UTC 25 Feb 09 07:39:28 AM UTC 25 12779557933 ps
T86 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/7.hmac_smoke.2914533194 Feb 09 07:39:16 AM UTC 25 Feb 09 07:39:29 AM UTC 25 830875044 ps
T87 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/3.hmac_test_hmac384_vectors.2685575041 Feb 09 07:37:18 AM UTC 25 Feb 09 07:39:33 AM UTC 25 13077014171 ps
T88 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/4.hmac_test_hmac384_vectors.1764718937 Feb 09 07:38:04 AM UTC 25 Feb 09 07:39:37 AM UTC 25 2298461656 ps
T89 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/7.hmac_burst_wr.611681893 Feb 09 07:39:25 AM UTC 25 Feb 09 07:39:41 AM UTC 25 1132690921 ps
T90 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/7.hmac_alert_test.3916768661 Feb 09 07:39:38 AM UTC 25 Feb 09 07:39:41 AM UTC 25 26651664 ps
T63 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/6.hmac_back_pressure.16913914 Feb 09 07:39:01 AM UTC 25 Feb 09 07:39:47 AM UTC 25 2210557996 ps
T91 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/8.hmac_smoke.1401203627 Feb 09 07:39:42 AM UTC 25 Feb 09 07:39:49 AM UTC 25 331936379 ps
T92 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/7.hmac_wipe_secret.1292429087 Feb 09 07:39:29 AM UTC 25 Feb 09 07:39:52 AM UTC 25 551338547 ps
T93 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/7.hmac_error.2637693218 Feb 09 07:39:28 AM UTC 25 Feb 09 07:39:57 AM UTC 25 25653806974 ps
T165 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/6.hmac_burst_wr.331430258 Feb 09 07:39:05 AM UTC 25 Feb 09 07:40:04 AM UTC 25 4520987874 ps
T184 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/4.hmac_test_hmac512_vectors.721015890 Feb 09 07:38:04 AM UTC 25 Feb 09 07:40:06 AM UTC 25 5707251345 ps
T185 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/1.hmac_error.1743993713 Feb 09 07:36:19 AM UTC 25 Feb 09 07:40:23 AM UTC 25 3728635036 ps
T164 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/4.hmac_long_msg.1502319744 Feb 09 07:37:38 AM UTC 25 Feb 09 07:40:24 AM UTC 25 40851153825 ps
T186 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/8.hmac_alert_test.603027198 Feb 09 07:40:26 AM UTC 25 Feb 09 07:40:28 AM UTC 25 13622183 ps
T162 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/7.hmac_back_pressure.1303278689 Feb 09 07:39:19 AM UTC 25 Feb 09 07:40:33 AM UTC 25 1333809487 ps
T187 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/9.hmac_smoke.2664606501 Feb 09 07:40:30 AM UTC 25 Feb 09 07:40:38 AM UTC 25 250654287 ps
T141 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/5.hmac_wipe_secret.2349539235 Feb 09 07:38:44 AM UTC 25 Feb 09 07:40:40 AM UTC 25 4800569610 ps
T39 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/8.hmac_burst_wr.3072387409 Feb 09 07:39:52 AM UTC 25 Feb 09 07:40:46 AM UTC 25 5732032294 ps
T163 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/8.hmac_back_pressure.763379555 Feb 09 07:39:48 AM UTC 25 Feb 09 07:40:53 AM UTC 25 18146395517 ps
T188 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/9.hmac_back_pressure.2867680842 Feb 09 07:40:39 AM UTC 25 Feb 09 07:40:56 AM UTC 25 809892915 ps
T40 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/9.hmac_burst_wr.1756503138 Feb 09 07:40:46 AM UTC 25 Feb 09 07:41:04 AM UTC 25 274265383 ps
T189 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/9.hmac_alert_test.2570087904 Feb 09 07:41:03 AM UTC 25 Feb 09 07:41:05 AM UTC 25 24414082 ps
T190 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/10.hmac_smoke.2971137725 Feb 09 07:41:05 AM UTC 25 Feb 09 07:41:10 AM UTC 25 174816195 ps
T191 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/9.hmac_wipe_secret.1737899884 Feb 09 07:40:57 AM UTC 25 Feb 09 07:41:17 AM UTC 25 1534705342 ps
T192 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/9.hmac_long_msg.3363035807 Feb 09 07:40:34 AM UTC 25 Feb 09 07:41:21 AM UTC 25 681115167 ps
T142 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/6.hmac_wipe_secret.1809229865 Feb 09 07:39:09 AM UTC 25 Feb 09 07:41:35 AM UTC 25 2179470378 ps
T193 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/10.hmac_long_msg.99174983 Feb 09 07:41:06 AM UTC 25 Feb 09 07:41:39 AM UTC 25 3653298273 ps
T194 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/5.hmac_long_msg.196773349 Feb 09 07:38:29 AM UTC 25 Feb 09 07:41:41 AM UTC 25 11231679348 ps
T13 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/1.hmac_stress_all_with_rand_reset.2400274992 Feb 09 07:36:23 AM UTC 25 Feb 09 07:41:47 AM UTC 25 47731738224 ps
T195 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/10.hmac_alert_test.1018980992 Feb 09 07:41:48 AM UTC 25 Feb 09 07:41:50 AM UTC 25 15378613 ps
T98 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/8.hmac_wipe_secret.525371023 Feb 09 07:40:05 AM UTC 25 Feb 09 07:41:54 AM UTC 25 27039188287 ps
T99 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/10.hmac_burst_wr.527923225 Feb 09 07:41:23 AM UTC 25 Feb 09 07:42:00 AM UTC 25 8769032978 ps
T100 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/11.hmac_back_pressure.58167579 Feb 09 07:41:54 AM UTC 25 Feb 09 07:42:15 AM UTC 25 477498813 ps
T101 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/10.hmac_back_pressure.907455872 Feb 09 07:41:10 AM UTC 25 Feb 09 07:42:15 AM UTC 25 4073634109 ps
T102 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/6.hmac_long_msg.3509974160 Feb 09 07:39:01 AM UTC 25 Feb 09 07:42:29 AM UTC 25 41401309475 ps
T31 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/11.hmac_burst_wr.2096737222 Feb 09 07:42:00 AM UTC 25 Feb 09 07:42:34 AM UTC 25 2386370806 ps
T103 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/11.hmac_alert_test.823051047 Feb 09 07:42:35 AM UTC 25 Feb 09 07:42:37 AM UTC 25 15444641 ps
T104 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/8.hmac_long_msg.1596724400 Feb 09 07:39:42 AM UTC 25 Feb 09 07:42:38 AM UTC 25 38959288455 ps
T105 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/8.hmac_error.2763491169 Feb 09 07:39:58 AM UTC 25 Feb 09 07:42:48 AM UTC 25 11379873840 ps
T106 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/12.hmac_smoke.2086070440 Feb 09 07:42:38 AM UTC 25 Feb 09 07:42:54 AM UTC 25 878152680 ps
T196 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/11.hmac_error.43120363 Feb 09 07:42:16 AM UTC 25 Feb 09 07:42:56 AM UTC 25 1055714249 ps
T197 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/9.hmac_error.3056102947 Feb 09 07:40:55 AM UTC 25 Feb 09 07:43:01 AM UTC 25 2268079570 ps
T166 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/12.hmac_burst_wr.1910731178 Feb 09 07:42:56 AM UTC 25 Feb 09 07:43:21 AM UTC 25 1923384509 ps
T198 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/12.hmac_error.2402473700 Feb 09 07:42:56 AM UTC 25 Feb 09 07:43:23 AM UTC 25 1411178688 ps
T199 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/12.hmac_alert_test.3083103552 Feb 09 07:43:22 AM UTC 25 Feb 09 07:43:24 AM UTC 25 12620414 ps
T159 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/2.hmac_datapath_stress.438804400 Feb 09 07:36:30 AM UTC 25 Feb 09 07:43:27 AM UTC 25 10414768433 ps
T200 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/12.hmac_back_pressure.3676502214 Feb 09 07:42:50 AM UTC 25 Feb 09 07:43:32 AM UTC 25 3171252473 ps
T201 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/13.hmac_smoke.4068885237 Feb 09 07:43:24 AM UTC 25 Feb 09 07:43:34 AM UTC 25 464614685 ps
T202 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/13.hmac_back_pressure.1269988183 Feb 09 07:43:29 AM UTC 25 Feb 09 07:43:38 AM UTC 25 98158702 ps
T203 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/10.hmac_datapath_stress.1258088547 Feb 09 07:41:18 AM UTC 25 Feb 09 07:43:47 AM UTC 25 678896448 ps
T204 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/6.hmac_error.3367690913 Feb 09 07:39:05 AM UTC 25 Feb 09 07:43:49 AM UTC 25 71665070932 ps
T205 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/13.hmac_alert_test.1336407152 Feb 09 07:43:50 AM UTC 25 Feb 09 07:43:53 AM UTC 25 14260148 ps
T206 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/13.hmac_error.4050080658 Feb 09 07:43:36 AM UTC 25 Feb 09 07:43:53 AM UTC 25 911492286 ps
T143 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/11.hmac_wipe_secret.1269189353 Feb 09 07:42:16 AM UTC 25 Feb 09 07:43:55 AM UTC 25 6611819015 ps
T207 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/14.hmac_smoke.4177108940 Feb 09 07:43:52 AM UTC 25 Feb 09 07:44:01 AM UTC 25 421050543 ps
T208 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/13.hmac_burst_wr.195665259 Feb 09 07:43:35 AM UTC 25 Feb 09 07:44:05 AM UTC 25 4059011948 ps
T107 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/13.hmac_wipe_secret.2451656505 Feb 09 07:43:39 AM UTC 25 Feb 09 07:44:13 AM UTC 25 22426460232 ps
T160 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/6.hmac_datapath_stress.3507124775 Feb 09 07:39:01 AM UTC 25 Feb 09 07:44:17 AM UTC 25 5229809427 ps
T209 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/13.hmac_long_msg.3495211896 Feb 09 07:43:25 AM UTC 25 Feb 09 07:44:20 AM UTC 25 6370476701 ps
T210 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/14.hmac_alert_test.570233812 Feb 09 07:44:21 AM UTC 25 Feb 09 07:44:23 AM UTC 25 38978029 ps
T82 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/8.hmac_stress_all.1097853708 Feb 09 07:40:08 AM UTC 25 Feb 09 07:44:26 AM UTC 25 18853553675 ps
T144 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/10.hmac_wipe_secret.2050157445 Feb 09 07:41:40 AM UTC 25 Feb 09 07:44:33 AM UTC 25 51183084316 ps
T211 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/10.hmac_error.1246295387 Feb 09 07:41:37 AM UTC 25 Feb 09 07:44:37 AM UTC 25 31055301598 ps
T32 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/14.hmac_back_pressure.1451543635 Feb 09 07:43:53 AM UTC 25 Feb 09 07:44:43 AM UTC 25 1262676242 ps
T212 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/15.hmac_error.1466226099 Feb 09 07:44:39 AM UTC 25 Feb 09 07:44:44 AM UTC 25 255853580 ps
T213 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/15.hmac_smoke.3479409699 Feb 09 07:44:24 AM UTC 25 Feb 09 07:44:44 AM UTC 25 4014496687 ps
T214 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/15.hmac_alert_test.1566724140 Feb 09 07:44:44 AM UTC 25 Feb 09 07:44:46 AM UTC 25 14893220 ps
T145 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/12.hmac_wipe_secret.3724267828 Feb 09 07:42:57 AM UTC 25 Feb 09 07:44:48 AM UTC 25 7468453311 ps
T215 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/22.hmac_smoke.3473155544 Feb 09 07:48:56 AM UTC 25 Feb 09 07:49:16 AM UTC 25 992361803 ps
T216 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/15.hmac_burst_wr.3868200735 Feb 09 07:44:39 AM UTC 25 Feb 09 07:44:49 AM UTC 25 1586133859 ps
T217 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/15.hmac_wipe_secret.2409577768 Feb 09 07:44:44 AM UTC 25 Feb 09 07:44:52 AM UTC 25 91185056 ps
T167 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/14.hmac_burst_wr.4079679340 Feb 09 07:44:02 AM UTC 25 Feb 09 07:44:53 AM UTC 25 1780959801 ps
T218 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/15.hmac_back_pressure.192682648 Feb 09 07:44:33 AM UTC 25 Feb 09 07:44:57 AM UTC 25 2542716434 ps
T219 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/16.hmac_back_pressure.1786016271 Feb 09 07:44:50 AM UTC 25 Feb 09 07:45:09 AM UTC 25 903495969 ps
T220 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/16.hmac_smoke.4231669463 Feb 09 07:44:47 AM UTC 25 Feb 09 07:45:12 AM UTC 25 2632644352 ps
T221 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/16.hmac_alert_test.4192843061 Feb 09 07:45:16 AM UTC 25 Feb 09 07:45:18 AM UTC 25 36148309 ps
T222 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/16.hmac_burst_wr.340948212 Feb 09 07:44:54 AM UTC 25 Feb 09 07:45:19 AM UTC 25 1196404118 ps
T223 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/12.hmac_long_msg.2820623894 Feb 09 07:42:40 AM UTC 25 Feb 09 07:45:23 AM UTC 25 2441783998 ps
T148 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/12.hmac_stress_all.1846015974 Feb 09 07:43:03 AM UTC 25 Feb 09 07:45:26 AM UTC 25 2571600565 ps
T224 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/17.hmac_smoke.1099339737 Feb 09 07:45:19 AM UTC 25 Feb 09 07:45:32 AM UTC 25 897455096 ps
T225 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/14.hmac_wipe_secret.771028521 Feb 09 07:44:14 AM UTC 25 Feb 09 07:45:33 AM UTC 25 4354273402 ps
T94 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/10.hmac_stress_all.3884945390 Feb 09 07:41:42 AM UTC 25 Feb 09 07:45:54 AM UTC 25 16480508317 ps
T226 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/14.hmac_error.215697809 Feb 09 07:44:06 AM UTC 25 Feb 09 07:46:06 AM UTC 25 26073792820 ps
T227 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/17.hmac_alert_test.1882462515 Feb 09 07:46:07 AM UTC 25 Feb 09 07:46:09 AM UTC 25 13011424 ps
T228 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/17.hmac_error.2760140634 Feb 09 07:45:33 AM UTC 25 Feb 09 07:46:10 AM UTC 25 4989158436 ps
T229 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/17.hmac_burst_wr.12469840 Feb 09 07:45:32 AM UTC 25 Feb 09 07:46:11 AM UTC 25 2299692304 ps
T230 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/9.hmac_datapath_stress.4281718522 Feb 09 07:40:41 AM UTC 25 Feb 09 07:46:15 AM UTC 25 3893307674 ps
T231 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/11.hmac_long_msg.2178691476 Feb 09 07:41:51 AM UTC 25 Feb 09 07:46:18 AM UTC 25 11352091474 ps
T232 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/18.hmac_smoke.345563143 Feb 09 07:46:10 AM UTC 25 Feb 09 07:46:19 AM UTC 25 355731232 ps
T233 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/15.hmac_long_msg.3474201521 Feb 09 07:44:28 AM UTC 25 Feb 09 07:46:24 AM UTC 25 6447276581 ps
T33 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/17.hmac_back_pressure.1061132849 Feb 09 07:45:25 AM UTC 25 Feb 09 07:46:40 AM UTC 25 1943878605 ps
T51 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/16.hmac_error.2150894779 Feb 09 07:44:58 AM UTC 25 Feb 09 07:46:48 AM UTC 25 14526129647 ps
T52 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/18.hmac_alert_test.252293061 Feb 09 07:46:50 AM UTC 25 Feb 09 07:46:52 AM UTC 25 132289771 ps
T53 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/16.hmac_wipe_secret.2864825477 Feb 09 07:45:11 AM UTC 25 Feb 09 07:46:53 AM UTC 25 3674608625 ps
T54 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/18.hmac_burst_wr.3814776202 Feb 09 07:46:20 AM UTC 25 Feb 09 07:46:57 AM UTC 25 979472275 ps
T55 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/17.hmac_wipe_secret.2196323226 Feb 09 07:45:35 AM UTC 25 Feb 09 07:46:59 AM UTC 25 5770131713 ps
T56 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/7.hmac_datapath_stress.3489328591 Feb 09 07:39:19 AM UTC 25 Feb 09 07:47:00 AM UTC 25 2977535261 ps
T57 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/18.hmac_long_msg.2395923211 Feb 09 07:46:10 AM UTC 25 Feb 09 07:47:01 AM UTC 25 3621847016 ps
T58 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/19.hmac_smoke.1103215650 Feb 09 07:46:53 AM UTC 25 Feb 09 07:47:09 AM UTC 25 2470799396 ps
T59 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/16.hmac_long_msg.2371805973 Feb 09 07:44:49 AM UTC 25 Feb 09 07:47:10 AM UTC 25 6072875764 ps
T234 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/14.hmac_long_msg.1684184349 Feb 09 07:43:53 AM UTC 25 Feb 09 07:47:15 AM UTC 25 6109056830 ps
T235 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/19.hmac_alert_test.3837822488 Feb 09 07:47:16 AM UTC 25 Feb 09 07:47:18 AM UTC 25 99534950 ps
T15 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/18.hmac_back_pressure.1587477292 Feb 09 07:46:13 AM UTC 25 Feb 09 07:47:27 AM UTC 25 7197314867 ps
T41 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/0.hmac_test_sha256_vectors.3268313852 Feb 09 07:36:15 AM UTC 25 Feb 09 07:47:29 AM UTC 25 48283984509 ps
T42 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/19.hmac_wipe_secret.1903032662 Feb 09 07:47:11 AM UTC 25 Feb 09 07:47:34 AM UTC 25 329490931 ps
T43 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/3.hmac_test_sha256_vectors.2731157119 Feb 09 07:37:15 AM UTC 25 Feb 09 07:47:41 AM UTC 25 41747650808 ps
T44 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/20.hmac_smoke.1445980298 Feb 09 07:47:19 AM UTC 25 Feb 09 07:47:41 AM UTC 25 3797070379 ps
T45 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/9.hmac_stress_all.1550765393 Feb 09 07:40:58 AM UTC 25 Feb 09 07:47:54 AM UTC 25 18897024665 ps
T46 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/17.hmac_long_msg.917914936 Feb 09 07:45:20 AM UTC 25 Feb 09 07:48:02 AM UTC 25 8042977391 ps
T47 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/19.hmac_burst_wr.1714365214 Feb 09 07:47:03 AM UTC 25 Feb 09 07:48:20 AM UTC 25 22726987794 ps
T48 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/20.hmac_burst_wr.3408922105 Feb 09 07:47:45 AM UTC 25 Feb 09 07:48:22 AM UTC 25 1924443992 ps
T49 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/20.hmac_alert_test.250503444 Feb 09 07:48:21 AM UTC 25 Feb 09 07:48:23 AM UTC 25 12567053 ps
T236 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/21.hmac_smoke.2035727076 Feb 09 07:48:22 AM UTC 25 Feb 09 07:48:25 AM UTC 25 18278675 ps
T237 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/18.hmac_error.2183565347 Feb 09 07:46:20 AM UTC 25 Feb 09 07:48:41 AM UTC 25 45323696230 ps
T64 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/20.hmac_back_pressure.3682201218 Feb 09 07:47:32 AM UTC 25 Feb 09 07:48:44 AM UTC 25 3826696819 ps
T238 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/20.hmac_wipe_secret.4236736692 Feb 09 07:47:56 AM UTC 25 Feb 09 07:48:46 AM UTC 25 2400337120 ps
T239 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/19.hmac_back_pressure.3525808904 Feb 09 07:46:58 AM UTC 25 Feb 09 07:48:47 AM UTC 25 4588211864 ps
T240 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/18.hmac_wipe_secret.2411069166 Feb 09 07:46:25 AM UTC 25 Feb 09 07:48:52 AM UTC 25 7400665203 ps
T241 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/3.hmac_datapath_stress.3042920301 Feb 09 07:37:09 AM UTC 25 Feb 09 07:48:53 AM UTC 25 68662887913 ps
T242 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/19.hmac_error.2768219424 Feb 09 07:47:03 AM UTC 25 Feb 09 07:48:54 AM UTC 25 5381213745 ps
T243 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/2.hmac_test_sha256_vectors.706286046 Feb 09 07:36:41 AM UTC 25 Feb 09 07:48:55 AM UTC 25 91518388880 ps
T244 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/1.hmac_test_sha256_vectors.3747336273 Feb 09 07:36:19 AM UTC 25 Feb 09 07:48:58 AM UTC 25 225758328944 ps
T245 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/21.hmac_alert_test.2641382305 Feb 09 07:48:56 AM UTC 25 Feb 09 07:48:59 AM UTC 25 17375654 ps
T246 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/20.hmac_error.3576705685 Feb 09 07:47:45 AM UTC 25 Feb 09 07:49:22 AM UTC 25 48646154032 ps
T65 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/21.hmac_burst_wr.358746863 Feb 09 07:48:45 AM UTC 25 Feb 09 07:49:32 AM UTC 25 860990196 ps
T247 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/21.hmac_wipe_secret.1479924409 Feb 09 07:48:48 AM UTC 25 Feb 09 07:49:34 AM UTC 25 9963662881 ps
T248 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/19.hmac_long_msg.3183168925 Feb 09 07:46:55 AM UTC 25 Feb 09 07:49:37 AM UTC 25 2704479345 ps
T249 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/22.hmac_alert_test.2765349197 Feb 09 07:49:39 AM UTC 25 Feb 09 07:49:41 AM UTC 25 11155214 ps
T66 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/5.hmac_stress_all.3295639339 Feb 09 07:38:44 AM UTC 25 Feb 09 07:49:46 AM UTC 25 17924969425 ps
T250 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/22.hmac_error.4116531119 Feb 09 07:49:23 AM UTC 25 Feb 09 07:49:46 AM UTC 25 6614147030 ps
T251 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/21.hmac_back_pressure.2614965694 Feb 09 07:48:26 AM UTC 25 Feb 09 07:49:53 AM UTC 25 1146792494 ps
T252 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/21.hmac_error.3251911606 Feb 09 07:48:48 AM UTC 25 Feb 09 07:49:55 AM UTC 25 8404755942 ps
T253 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/11.hmac_datapath_stress.3680684551 Feb 09 07:41:55 AM UTC 25 Feb 09 07:49:55 AM UTC 25 3312503620 ps
T254 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/21.hmac_long_msg.369123300 Feb 09 07:48:24 AM UTC 25 Feb 09 07:49:59 AM UTC 25 2823175427 ps
T255 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/23.hmac_smoke.2326502900 Feb 09 07:49:42 AM UTC 25 Feb 09 07:50:01 AM UTC 25 788886878 ps
T256 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/4.hmac_test_sha256_vectors.643468840 Feb 09 07:37:54 AM UTC 25 Feb 09 07:50:02 AM UTC 25 49584682529 ps
T257 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/23.hmac_alert_test.1969138586 Feb 09 07:50:05 AM UTC 25 Feb 09 07:50:07 AM UTC 25 22061783 ps
T258 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/22.hmac_back_pressure.1350359509 Feb 09 07:49:01 AM UTC 25 Feb 09 07:50:22 AM UTC 25 2701055361 ps
T259 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/24.hmac_smoke.1896555681 Feb 09 07:50:08 AM UTC 25 Feb 09 07:50:26 AM UTC 25 809818108 ps
T108 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/11.hmac_stress_all.3577210655 Feb 09 07:42:32 AM UTC 25 Feb 09 07:50:30 AM UTC 25 14759583250 ps
T260 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/22.hmac_burst_wr.1946210328 Feb 09 07:49:17 AM UTC 25 Feb 09 07:50:34 AM UTC 25 21484303919 ps
T261 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/23.hmac_back_pressure.3181922422 Feb 09 07:49:51 AM UTC 25 Feb 09 07:50:36 AM UTC 25 1566156329 ps
T262 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/12.hmac_datapath_stress.1373469711 Feb 09 07:42:50 AM UTC 25 Feb 09 07:50:37 AM UTC 25 2861931548 ps
T168 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/23.hmac_burst_wr.757706425 Feb 09 07:49:57 AM UTC 25 Feb 09 07:50:49 AM UTC 25 4325112583 ps
T263 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/21.hmac_datapath_stress.3009590687 Feb 09 07:48:42 AM UTC 25 Feb 09 07:50:58 AM UTC 25 1047667630 ps
T264 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/24.hmac_alert_test.838288172 Feb 09 07:51:00 AM UTC 25 Feb 09 07:51:02 AM UTC 25 70723329 ps
T265 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/22.hmac_wipe_secret.999264374 Feb 09 07:49:32 AM UTC 25 Feb 09 07:51:06 AM UTC 25 30592929647 ps
T266 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/20.hmac_long_msg.2875941706 Feb 09 07:47:28 AM UTC 25 Feb 09 07:51:13 AM UTC 25 27387638867 ps
T267 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/25.hmac_smoke.4095608731 Feb 09 07:51:03 AM UTC 25 Feb 09 07:51:22 AM UTC 25 295010744 ps
T268 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/22.hmac_long_msg.2471801594 Feb 09 07:49:00 AM UTC 25 Feb 09 07:51:26 AM UTC 25 19344854424 ps
T269 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/23.hmac_wipe_secret.999763484 Feb 09 07:50:01 AM UTC 25 Feb 09 07:51:41 AM UTC 25 9074157435 ps
T270 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/23.hmac_long_msg.717344087 Feb 09 07:49:51 AM UTC 25 Feb 09 07:51:55 AM UTC 25 7006935498 ps
T271 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/24.hmac_burst_wr.2478789146 Feb 09 07:50:35 AM UTC 25 Feb 09 07:52:03 AM UTC 25 5108101474 ps
T272 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/25.hmac_burst_wr.2408521126 Feb 09 07:51:28 AM UTC 25 Feb 09 07:52:11 AM UTC 25 10613642312 ps
T273 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/25.hmac_wipe_secret.910214023 Feb 09 07:51:56 AM UTC 25 Feb 09 07:52:12 AM UTC 25 654425698 ps
T274 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/25.hmac_alert_test.1611406533 Feb 09 07:52:12 AM UTC 25 Feb 09 07:52:14 AM UTC 25 16272395 ps
T275 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/24.hmac_back_pressure.2830494094 Feb 09 07:50:27 AM UTC 25 Feb 09 07:52:17 AM UTC 25 3086677406 ps
T276 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/26.hmac_smoke.142904692 Feb 09 07:52:14 AM UTC 25 Feb 09 07:52:20 AM UTC 25 1069325084 ps
T277 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/24.hmac_long_msg.3449043734 Feb 09 07:50:24 AM UTC 25 Feb 09 07:52:23 AM UTC 25 10228344998 ps
T95 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/6.hmac_stress_all.4236026914 Feb 09 07:39:11 AM UTC 25 Feb 09 07:52:45 AM UTC 25 217593120994 ps
T278 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/23.hmac_error.3744294493 Feb 09 07:49:57 AM UTC 25 Feb 09 07:52:45 AM UTC 25 11801044059 ps
T279 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/17.hmac_stress_all.2819320142 Feb 09 07:45:56 AM UTC 25 Feb 09 07:52:51 AM UTC 25 15417066469 ps
T280 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/26.hmac_error.2373822059 Feb 09 07:52:50 AM UTC 25 Feb 09 07:52:57 AM UTC 25 362555042 ps
T281 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/26.hmac_burst_wr.695629065 Feb 09 07:52:24 AM UTC 25 Feb 09 07:52:59 AM UTC 25 1902056623 ps
T282 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/26.hmac_alert_test.2410362558 Feb 09 07:52:58 AM UTC 25 Feb 09 07:53:00 AM UTC 25 39434387 ps
T283 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/24.hmac_wipe_secret.12196392 Feb 09 07:50:39 AM UTC 25 Feb 09 07:53:00 AM UTC 25 16886288000 ps
T284 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/26.hmac_back_pressure.897364911 Feb 09 07:52:19 AM UTC 25 Feb 09 07:53:09 AM UTC 25 810547120 ps
T285 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/27.hmac_smoke.2747026737 Feb 09 07:53:00 AM UTC 25 Feb 09 07:53:11 AM UTC 25 1644010243 ps
T286 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/27.hmac_long_msg.4146298706 Feb 09 07:53:02 AM UTC 25 Feb 09 07:53:16 AM UTC 25 213579719 ps
T14 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/4.hmac_stress_all_with_rand_reset.1401102185 Feb 09 07:38:12 AM UTC 25 Feb 09 07:53:18 AM UTC 25 112308548127 ps
T287 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/24.hmac_error.4278816447 Feb 09 07:50:37 AM UTC 25 Feb 09 07:53:25 AM UTC 25 20540580445 ps
T288 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/27.hmac_error.4076231197 Feb 09 07:53:17 AM UTC 25 Feb 09 07:53:26 AM UTC 25 96507841 ps
T289 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/27.hmac_alert_test.1046814164 Feb 09 07:53:27 AM UTC 25 Feb 09 07:53:29 AM UTC 25 11025478 ps
T290 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/25.hmac_back_pressure.2368365830 Feb 09 07:51:15 AM UTC 25 Feb 09 07:53:32 AM UTC 25 1564118523 ps
T291 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/28.hmac_smoke.762755013 Feb 09 07:53:30 AM UTC 25 Feb 09 07:53:35 AM UTC 25 245687626 ps
T292 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/23.hmac_datapath_stress.1314408720 Feb 09 07:49:54 AM UTC 25 Feb 09 07:53:40 AM UTC 25 1215483916 ps
T293 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/28.hmac_long_msg.344241269 Feb 09 07:53:34 AM UTC 25 Feb 09 07:53:45 AM UTC 25 452499608 ps
T294 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/25.hmac_long_msg.3643563050 Feb 09 07:51:08 AM UTC 25 Feb 09 07:53:52 AM UTC 25 29674925048 ps
T295 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/25.hmac_error.561091330 Feb 09 07:51:42 AM UTC 25 Feb 09 07:53:52 AM UTC 25 26032722389 ps
T296 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/27.hmac_back_pressure.3182359344 Feb 09 07:53:02 AM UTC 25 Feb 09 07:53:58 AM UTC 25 732059362 ps
T297 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/27.hmac_wipe_secret.487445647 Feb 09 07:53:21 AM UTC 25 Feb 09 07:53:58 AM UTC 25 4960690582 ps
T83 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/9.hmac_stress_all_with_rand_reset.495748101 Feb 09 07:41:01 AM UTC 25 Feb 09 07:54:02 AM UTC 25 137885445080 ps
T298 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/28.hmac_alert_test.596058773 Feb 09 07:54:00 AM UTC 25 Feb 09 07:54:02 AM UTC 25 87607516 ps
T299 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/28.hmac_wipe_secret.983064678 Feb 09 07:53:54 AM UTC 25 Feb 09 07:54:08 AM UTC 25 1823129033 ps
T300 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/27.hmac_burst_wr.1072771304 Feb 09 07:53:12 AM UTC 25 Feb 09 07:54:09 AM UTC 25 9870214071 ps
T301 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/18.hmac_datapath_stress.901391580 Feb 09 07:46:17 AM UTC 25 Feb 09 07:54:11 AM UTC 25 10155808201 ps
T302 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/28.hmac_burst_wr.549819426 Feb 09 07:53:46 AM UTC 25 Feb 09 07:54:19 AM UTC 25 3929781962 ps
T303 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/29.hmac_smoke.152958221 Feb 09 07:54:05 AM UTC 25 Feb 09 07:54:21 AM UTC 25 288808251 ps