Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::msg_len_cg

Group : hmac_env_pkg::hmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	32	0	32	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hmac_en	2	0	2	100.00	100	1	1	2
msg_len_lower_cp	15	0	15	100.00	100	1	1	0
msg_len_upper_cp	1	0	1	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
msg_len_lower_cross	30	0	30	100.00	100	1	1	0
msg_len_upper_cross	2	0	2	100.00	100	1	1	0

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

159474

1

T4

14

T5

2

T6

34

auto[1]

165572

1

T3

24

T4

20

T5

6

---

Summary for Variable msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len_lower_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_2050_plus	119727	1			T5	3		T7	100		T8	43
len_1026_2046	7141	1			T6	1		T7	2		T8	5
len_514_1022	4380	1			T4	1		T6	1		T7	1
len_2_510	5517	1			T4	1		T6	1		T8	1
len_2056	183	1			T6	4		T34	4		T60	1
len_2048	408	1			T4	2		T6	4		T9	1
len_2040	602	1			T4	7		T6	2		T9	3
len_1032	281	1			T6	2		T9	2		T157	1
len_1024	2204	1			T4	2		T6	1		T7	1
len_1016	231	1			T34	3		T60	6		T158	1
len_520	599	1			T9	2		T60	2		T158	3
len_512	399	1			T6	2		T9	4		T34	2
len_504	369	1			T6	2		T9	1		T34	8
len_8	1226	1			T26	2		T159	5		T160	5
len_0	19257	1			T3	12		T4	4		T5	1

---

Summary for Variable msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for msg_len_upper_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

len_upper

169

1

T60

2

T161

2

T12

1

---

Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for msg_len_lower_cross

Bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	len_2050_plus	60422	1			T5	1		T7	18		T8	9
auto[0]	len_1026_2046	3372	1			T6	1		T7	1		T8	3
auto[0]	len_514_1022	2841	1			T6	1		T8	2		T157	1
auto[0]	len_2_510	3836	1			T8	1		T9	1		T29	6
auto[0]	len_2056	102	1			T60	1		T158	3		T12	3
auto[0]	len_2048	228	1			T9	1		T158	2		T161	1
auto[0]	len_2040	248	1			T4	4		T6	1		T9	2
auto[0]	len_1032	171	1			T27	2		T158	1		T91	3
auto[0]	len_1024	386	1			T6	1		T7	1		T9	1
auto[0]	len_1016	122	1			T34	2		T60	1		T86	1
auto[0]	len_520	360	1			T60	2		T12	1		T106	3
auto[0]	len_512	223	1			T6	2		T9	1		T29	2
auto[0]	len_504	190	1			T6	1		T34	3		T60	2
auto[0]	len_8	40	1			T41	2		T43	2		T45	1
auto[0]	len_0	7197	1			T4	3		T6	10		T7	228
auto[1]	len_2050_plus	59305	1			T5	2		T7	82		T8	34
auto[1]	len_1026_2046	3769	1			T7	1		T8	2		T9	1
auto[1]	len_514_1022	1539	1			T4	1		T7	1		T9	2
auto[1]	len_2_510	1681	1			T4	1		T6	1		T9	2
auto[1]	len_2056	81	1			T6	4		T34	4		T12	1
auto[1]	len_2048	180	1			T4	2		T6	4		T25	1
auto[1]	len_2040	354	1			T4	3		T6	1		T9	1
auto[1]	len_1032	110	1			T6	2		T9	2		T157	1
auto[1]	len_1024	1818	1			T4	2		T9	2		T138	93
auto[1]	len_1016	109	1			T34	1		T60	5		T158	1
auto[1]	len_520	239	1			T9	2		T158	3		T86	1
auto[1]	len_512	176	1			T9	3		T34	2		T29	1
auto[1]	len_504	179	1			T6	1		T9	1		T34	5
auto[1]	len_8	1186	1			T26	2		T159	5		T160	5
auto[1]	len_0	12060	1			T3	12		T4	1		T5	1

---

Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	0	2	100.00

Automatically Generated Cross Bins for msg_len_upper_cross

Bins

hmac_en

msg_len_upper_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

len_upper

87

1

T12

1

T162

1

T163

2

auto[1]

len_upper

82

1

T60

2

T161

2

T164

2