Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::msg_len_cg

Group : hmac_env_pkg::hmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	32	0	32	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hmac_en	2	0	2	100.00	100	1	1	2
msg_len_lower_cp	15	0	15	100.00	100	1	1	0
msg_len_upper_cp	1	0	1	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
msg_len_lower_cross	30	0	30	100.00	100	1	1	0
msg_len_upper_cross	2	0	2	100.00	100	1	1	0

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

114508

1

T3

18

T4

42

T5

18

auto[1]

124686

1

T3

18

T4

26

T5

38

---

Summary for Variable msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len_lower_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_2050_plus	88719	1			T5	19		T7	6		T9	1
len_1026_2046	5564	1			T3	2		T4	2		T6	7
len_514_1022	3656	1			T4	2		T5	1		T6	4
len_2_510	3993	1			T3	3		T4	2		T6	3
len_2056	398	1			T3	2		T11	3		T19	2
len_2048	276	1			T4	4		T13	3		T11	2
len_2040	544	1			T3	3		T4	2		T13	4
len_1032	271	1			T49	125		T19	1		T126	2
len_1024	1733	1			T4	2		T6	1		T13	10
len_1016	195	1			T4	4		T147	1		T126	1
len_520	119	1			T3	3		T4	2		T11	4
len_512	496	1			T4	1		T13	2		T11	2
len_504	163	1			T3	3		T4	6		T13	2
len_8	1092	1			T148	4		T76	16		T149	1
len_0	12378	1			T3	2		T4	7		T5	8

---

Summary for Variable msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for msg_len_upper_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

len_upper

126

1

T18

2

T88

2

T91

2

---

Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for msg_len_lower_cross

Bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	len_2050_plus	44514	1			T5	9		T7	4		T6	189
auto[0]	len_1026_2046	2642	1			T3	1		T4	2		T6	3
auto[0]	len_514_1022	2029	1			T4	2		T6	3		T13	2
auto[0]	len_2_510	2222	1			T3	2		T4	1		T6	2
auto[0]	len_2056	105	1			T3	1		T11	3		T19	2
auto[0]	len_2048	151	1			T4	2		T13	2		T11	1
auto[0]	len_2040	379	1			T3	2		T4	2		T126	4
auto[0]	len_1032	77	1			T49	2		T19	1		T126	1
auto[0]	len_1024	205	1			T6	1		T13	4		T12	1
auto[0]	len_1016	76	1			T4	2		T147	1		T150	2
auto[0]	len_520	74	1			T3	2		T11	3		T19	1
auto[0]	len_512	342	1			T4	1		T13	1		T11	1
auto[0]	len_504	97	1			T4	3		T13	2		T126	3
auto[0]	len_8	31	1			T149	1		T151	1		T152	1
auto[0]	len_0	4310	1			T3	1		T4	6		T7	1
auto[1]	len_2050_plus	44205	1			T5	10		T7	2		T9	1
auto[1]	len_1026_2046	2922	1			T3	1		T6	4		T11	4
auto[1]	len_514_1022	1627	1			T5	1		T6	1		T13	3
auto[1]	len_2_510	1771	1			T3	1		T4	1		T6	1
auto[1]	len_2056	293	1			T3	1		T126	1		T150	1
auto[1]	len_2048	125	1			T4	2		T13	1		T11	1
auto[1]	len_2040	165	1			T3	1		T13	4		T11	2
auto[1]	len_1032	194	1			T49	123		T126	1		T153	4
auto[1]	len_1024	1528	1			T4	2		T13	6		T64	68
auto[1]	len_1016	119	1			T4	2		T126	1		T36	1
auto[1]	len_520	45	1			T3	1		T4	2		T11	1
auto[1]	len_512	154	1			T13	1		T11	1		T12	2
auto[1]	len_504	66	1			T3	3		T4	3		T126	3
auto[1]	len_8	1061	1			T148	4		T76	16		T65	3
auto[1]	len_0	8068	1			T3	1		T4	1		T5	8

---

Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	0	2	100.00

Automatically Generated Cross Bins for msg_len_upper_cross

Bins

hmac_en

msg_len_upper_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

len_upper

76

1

T88

2

T91

2

T154

2

auto[1]

len_upper

50

1

T18

2

T70

2

T25

1