Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	192	0	192	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
key_swap	2	0	2	100.00	100	1	1	2
sta_fifo_depth	8	0	8	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	32	0	32	100.00	100	1	1	0
fifo_full_cross	32	0	32	100.00	100	1	1	0
fifo_depth_cross	128	0	128	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4468179

1

T3

141

T4

589

T7

7

auto[1]

2592975

1

T3

308

T4

360

T5

1107

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2700712

1

T3

236

T4

450

T5

648

auto[1]

4360442

1

T3

213

T4

499

T5

459

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3211866

1

T3

185

T4

435

T5

578

auto[1]

3849288

1

T3

264

T4

514

T5

529

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4384729

1

T3

304

T4

504

T5

459

auto[1]

2676425

1

T3

145

T4

445

T5

648

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	6365627	1			T3	409		T4	930		T5	82
fifo_depth[1]	114886	1			T3	1		T4	11		T5	21
fifo_depth[2]	88612	1			T3	8		T4	5		T5	6
fifo_depth[3]	70676	1			T3	5		T4	2		T5	21
fifo_depth[4]	65182	1			T3	8		T4	1		T5	36
fifo_depth[5]	51436	1			T3	4		T5	33		T7	1
fifo_depth[6]	41833	1			T3	6		T5	40		T6	16
fifo_depth[7]	27322	1			T3	3		T5	31		T6	20

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

695527

1

T3

40

T4

19

T5

1025

auto[1]

6365627

1

T3

409

T4

930

T5

82

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7050548

1

T3

449

T4

949

T5

1103

auto[1]

10606

1

T5

4

T6

10

T12

1664

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

26423

1

T3

5

T16

22

T13

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

25623

1

T7

1

T6

401

T11

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

27287

1

T3

5

T6

1022

T13

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

32439

1

T3

12

T5

572

T10

11

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

163844

1

T16

14

T29

10

T18

195

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

31241

1

T4

1

T16

18

T10

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

30531

1

T7

1

T13

2

T29

29

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

29024

1

T4

3

T11

1

T12

877

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

29890

1

T3

9

T4

2

T7

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

45901

1

T13

2

T11

3

T17

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

37235

1

T4

1

T13

4

T11

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

37037

1

T3

6

T16

1

T10

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

56610

1

T4

7

T10

23

T13

7

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

44070

1

T4

3

T6

28

T11

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

40520

1

T3

3

T4

2

T5

453

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

37852

1

T14

18

T17

1

T18

15

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

150246

1

T3

32

T4

72

T7

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

163986

1

T4

43

T6

9

T13

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

162305

1

T3

34

T4

54

T6

192

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

156668

1

T3

34

T5

6

T7

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1712670

1

T4

53

T9

1

T6

94

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

178405

1

T3

1

T4

67

T16

288

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

153342

1

T3

62

T4

49

T13

81

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

167832

1

T4

93

T6

181

T16

22

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

445570

1

T3

52

T4

40

T7

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

478878

1

T4

130

T7

1

T6

150

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

438897

1

T4

25

T16

735

T13

40

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

442327

1

T3

47

T4

83

T5

70

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

520296

1

T3

42

T4

151

T10

662

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

394526

1

T4

20

T7

2

T6

57

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

389063

1

T3

60

T4

48

T5

6

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

410616

1

T3

45

T4

2

T7

1

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

175906

1

T3

37

T4

72

T7

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

188527

1

T4

43

T7

1

T6

408

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

189232

1

T3

39

T4

54

T6

1206

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

188544

1

T3

46

T5

575

T7

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1876117

1

T4

53

T9

1

T6

94

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

208716

1

T3

1

T4

68

T16

306

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

182450

1

T3

62

T4

49

T7

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

195908

1

T4

96

T6

181

T16

22

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

475047

1

T3

61

T4

42

T7

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

524365

1

T4

130

T7

1

T6

150

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

475638

1

T4

26

T16

735

T13

44

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

478868

1

T3

53

T4

83

T5

70

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

576321

1

T3

42

T4

158

T10

685

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

437930

1

T4

23

T7

2

T6

85

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

429008

1

T3

63

T4

50

T5

458

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

447971

1

T3

45

T4

2

T7

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

763

1

T12

96

T18

7

T46

104

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

1082

1

T6

2

T12

5

T18

7

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

360

1

T6

8

T18

20

T157

6

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

563

1

T5

3

T12

1

T49

56

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

397

1

T157

1

T158

8

T159

7

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

930

1

T18

42

T160

7

T161

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1423

1

T12

1201

T18

8

T46

11

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

948

1

T12

1

T18

7

T88

55

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

413

1

T18

6

T49

158

T158

28

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

414

1

T18

4

T88

2

T162

4

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

494

1

T12

324

T65

25

T160

90

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

496

1

T157

167

T159

141

T163

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

585

1

T18

3

T49

2

T46

9

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

666

1

T18

27

T21

3

T162

3

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

575

1

T5

1

T12

36

T18

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

497

1

T163

362

T34

129

T164

6

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fifo_depth[0]

auto[0]

auto[0]

auto[0]

auto[0]

150246

1

T3

32

T4

72

T7

1

fifo_depth[0]

auto[0]

auto[0]

auto[0]

auto[1]

163986

1

T4

43

T6

9

T13

1

fifo_depth[0]

auto[0]

auto[0]

auto[1]

auto[0]

162305

1

T3

34

T4

54

T6

192

fifo_depth[0]

auto[0]

auto[0]

auto[1]

auto[1]

156668

1

T3

34

T5

6

T7

1

fifo_depth[0]

auto[0]

auto[1]

auto[0]

auto[0]

1712670

1

T4

53

T9

1

T6

94

fifo_depth[0]

auto[0]

auto[1]

auto[0]

auto[1]

178405

1

T3

1

T4

67

T16

288

fifo_depth[0]

auto[0]

auto[1]

auto[1]

auto[0]

153342

1

T3

62

T4

49

T13

81

fifo_depth[0]

auto[0]

auto[1]

auto[1]

auto[1]

167832

1

T4

93

T6

181

T16

22

fifo_depth[0]

auto[1]

auto[0]

auto[0]

auto[0]

445570

1

T3

52

T4

40

T7

1

fifo_depth[0]

auto[1]

auto[0]

auto[0]

auto[1]

478878

1

T4

130

T7

1

T6

150

fifo_depth[0]

auto[1]

auto[0]

auto[1]

auto[0]

438897

1

T4

25

T16

735

T13

40

fifo_depth[0]

auto[1]

auto[0]

auto[1]

auto[1]

442327

1

T3

47

T4

83

T5

70

fifo_depth[0]

auto[1]

auto[1]

auto[0]

auto[0]

520296

1

T3

42

T4

151

T10

662

fifo_depth[0]

auto[1]

auto[1]

auto[0]

auto[1]

394526

1

T4

20

T7

2

T6

57

fifo_depth[0]

auto[1]

auto[1]

auto[1]

auto[0]

389063

1

T3

60

T4

48

T5

6

fifo_depth[0]

auto[1]

auto[1]

auto[1]

auto[1]

410616

1

T3

45

T4

2

T7

1

fifo_depth[1]

auto[0]

auto[0]

auto[0]

auto[0]

2703

1

T16

9

T11

4

T45

4

fifo_depth[1]

auto[0]

auto[0]

auto[0]

auto[1]

2897

1

T11

1

T12

42

T45

11

fifo_depth[1]

auto[0]

auto[0]

auto[1]

auto[0]

3154

1

T3

1

T13

1

T8

10

fifo_depth[1]

auto[0]

auto[0]

auto[1]

auto[1]

3358

1

T5

20

T10

7

T13

1

fifo_depth[1]

auto[0]

auto[1]

auto[0]

auto[0]

43913

1

T16

9

T29

5

T18

4

fifo_depth[1]

auto[0]

auto[1]

auto[0]

auto[1]

3679

1

T4

1

T16

15

T10

1

fifo_depth[1]

auto[0]

auto[1]

auto[1]

auto[0]

2925

1

T13

2

T29

17

T30

8

fifo_depth[1]

auto[0]

auto[1]

auto[1]

auto[1]

3329

1

T4

2

T11

1

T17

1

fifo_depth[1]

auto[1]

auto[0]

auto[0]

auto[0]

4528

1

T4

1

T13

1

T165

11

fifo_depth[1]

auto[1]

auto[0]

auto[0]

auto[1]

6497

1

T13

1

T51

10

T18

4

fifo_depth[1]

auto[1]

auto[0]

auto[1]

auto[0]

5718

1

T13

3

T12

9

T17

1

fifo_depth[1]

auto[1]

auto[0]

auto[1]

auto[1]

5500

1

T16

1

T10

2

T166

27

fifo_depth[1]

auto[1]

auto[1]

auto[0]

auto[0]

8688

1

T4

3

T10

16

T13

3

fifo_depth[1]

auto[1]

auto[1]

auto[0]

auto[1]

6086

1

T4

3

T11

2

T12

12

fifo_depth[1]

auto[1]

auto[1]

auto[1]

auto[0]

5216

1

T4

1

T5

1

T11

4

fifo_depth[1]

auto[1]

auto[1]

auto[1]

auto[1]

6695

1

T14

11

T18

5

T166

25

fifo_depth[2]

auto[0]

auto[0]

auto[0]

auto[0]

1867

1

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41

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22

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1

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43

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5

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1

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12

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34

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16

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65

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13

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4

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1

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76

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1

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1

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58

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2

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22

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164

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12

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42

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5

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3

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41

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1

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39

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12

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fifo_depth[5]

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17

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41

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22

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21

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129

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172

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22

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28

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7

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1

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29

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1

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6

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11

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1

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35

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11

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89

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49

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15

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13

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18

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22

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6

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43

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17

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5

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12

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1

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93

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10

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6

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58

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3

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14

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6

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1

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1

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59

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65

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155

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14

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21

fifo_depth[6]

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5

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3

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1

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14

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2

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26

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1

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1

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6

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4

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8

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4

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11

fifo_depth[7]

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1

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1

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10

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5

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17

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9

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29

fifo_depth[7]

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1

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2

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26

T92

1

fifo_depth[7]

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1

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4

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11

T133

1

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1

T88

3

T46

16

T74

6

fifo_depth[7]

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1

T12

74

T45

1

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1

fifo_depth[7]

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1

T18

15

T89

4

T70

1

fifo_depth[7]

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1

T18

95

T166

9

T88

6

fifo_depth[7]

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1

T12

18

T18

2

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1

fifo_depth[7]

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1705

1

T3

1

T166

11

T53

2

fifo_depth[7]

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1

T54

23

T55

31

T167

128

fifo_depth[7]

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1

T6

2

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9

T17

1

fifo_depth[7]

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1

T5

14

T18

2

T49

40

fifo_depth[7]

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2190

1

T166

17

T74

4

T150

1