Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	192	0	192	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
key_swap	2	0	2	100.00	100	1	1	2
sta_fifo_depth	8	0	8	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	32	0	32	100.00	100	1	1	0
fifo_full_cross	32	0	32	100.00	100	1	1	0
fifo_depth_cross	128	0	128	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5195254

1

T3

43

T4

186

T5

2

auto[1]

3559113

1

T1

45

T4

217

T5

6

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3515708

1

T1

45

T4

260

T5

4

auto[1]

5238659

1

T3

43

T4

143

T5

4

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3692149

1

T1

45

T4

115

T5

3

auto[1]

5062218

1

T3

43

T4

288

T5

5

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5205388

1

T3

43

T4

171

T5

4

auto[1]

3548979

1

T1

45

T4

232

T5

4

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	7905854	1			T1	44		T3	43		T4	388
fifo_depth[1]	139261	1			T1	1		T4	7		T6	10
fifo_depth[2]	108607	1			T4	6		T6	5		T7	18
fifo_depth[3]	86299	1			T4	1		T5	1		T6	1
fifo_depth[4]	78371	1			T4	1		T6	3		T7	7
fifo_depth[5]	61529	1			T8	2		T22	1		T157	2
fifo_depth[6]	50257	1			T7	3		T8	1		T10	1
fifo_depth[7]	33445	1			T25	26		T23	39		T26	12

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

848513

1

T1

1

T4

15

T5

1

auto[1]

7905854

1

T1

44

T3

43

T4

388

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8737473

1

T1

45

T3

43

T4

403

auto[1]

16894

1

T28

86

T39

191

T40

64

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

33382

1

T22

15

T10

1

T30

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

41987

1

T8

5

T30

1

T24

10

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

39957

1

T10

1

T23

82

T26

48

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

41755

1

T1

1

T11

1

T23

176

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

165990

1

T6

3

T8

1

T9

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

39698

1

T11

1

T10

1

T157

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

36689

1

T6

1

T21

1

T10

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

43130

1

T4

1

T6

1

T9

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

46820

1

T6

3

T9

1

T10

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

54578

1

T4

1

T9

4

T22

23

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

48933

1

T4

5

T157

7

T60

19

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

48884

1

T6

3

T8

10

T9

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

58556

1

T4

2

T5

1

T10

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

49694

1

T6

6

T9

2

T10

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

50757

1

T4

5

T6

2

T7

29

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

47703

1

T4

1

T9

2

T22

9

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

214744

1

T4

12

T9

20

T22

154

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

222376

1

T4

1

T8

38

T9

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

202254

1

T4

13

T5

1

T6

49

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

211642

1

T1

44

T4

43

T6

7

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1747318

1

T4

1

T6

98

T7

879

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

219939

1

T5

1

T6

27

T9

40

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

216796

1

T6

82

T7

17

T9

114

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

214492

1

T4

44

T5

1

T6

144

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

558615

1

T6

58

T9

62

T11

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

546529

1

T4

130

T6

36

T9

34

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

579715

1

T4

55

T5

1

T9

44

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

623537

1

T5

2

T6

70

T7

99

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

631680

1

T3

43

T4

39

T6

47

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

563348

1

T6

68

T9

25

T10

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

573182

1

T4

39

T5

1

T6

52

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

579687

1

T4

11

T6

18

T8

56

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

247332

1

T4

12

T9

20

T22

169

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

262947

1

T4

1

T8

43

T9

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

241751

1

T4

13

T5

1

T6

49

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

251479

1

T1

45

T4

43

T6

7

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1912148

1

T4

1

T6

101

T7

879

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

258928

1

T5

1

T6

27

T9

40

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

252812

1

T6

83

T7

17

T9

114

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

256546

1

T4

45

T5

1

T6

145

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

604213

1

T6

61

T9

63

T11

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

600256

1

T4

131

T6

36

T9

38

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

628420

1

T4

60

T5

1

T9

44

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

671556

1

T5

2

T6

73

T7

99

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

687932

1

T3

43

T4

41

T5

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

612221

1

T6

74

T9

27

T10

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

622852

1

T4

44

T5

1

T6

54

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

626080

1

T4

12

T6

18

T8

56

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

794

1

T40

1

T148

450

T66

48

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

1416

1

T39

1

T167

9

T148

98

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

460

1

T28

10

T40

24

T167

4

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

1918

1

T39

1

T167

5

T65

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1160

1

T40

33

T148

45

T66

4

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

709

1

T39

93

T31

263

T167

24

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

673

1

T39

4

T40

4

T31

76

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

1076

1

T31

1

T167

4

T65

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1222

1

T167

1

T65

10

T168

5

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

851

1

T167

5

T148

19

T66

8

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

228

1

T39

1

T148

3

T65

7

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

865

1

T28

76

T54

6

T66

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

2304

1

T39

1

T65

89

T169

32

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

821

1

T148

12

T66

8

T170

55

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1087

1

T39

90

T40

2

T167

40

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

1310

1

T31

540

T148

78

T54

6

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fifo_depth[0]

auto[0]

auto[0]

auto[0]

auto[0]

214744

1

T4

12

T9

20

T22

154

fifo_depth[0]

auto[0]

auto[0]

auto[0]

auto[1]

222376

1

T4

1

T8

38

T9

1

fifo_depth[0]

auto[0]

auto[0]

auto[1]

auto[0]

202254

1

T4

13

T5

1

T6

49

fifo_depth[0]

auto[0]

auto[0]

auto[1]

auto[1]

211642

1

T1

44

T4

43

T6

7

fifo_depth[0]

auto[0]

auto[1]

auto[0]

auto[0]

1747318

1

T4

1

T6

98

T7

879

fifo_depth[0]

auto[0]

auto[1]

auto[0]

auto[1]

219939

1

T5

1

T6

27

T9

40

fifo_depth[0]

auto[0]

auto[1]

auto[1]

auto[0]

216796

1

T6

82

T7

17

T9

114

fifo_depth[0]

auto[0]

auto[1]

auto[1]

auto[1]

214492

1

T4

44

T5

1

T6

144

fifo_depth[0]

auto[1]

auto[0]

auto[0]

auto[0]

558615

1

T6

58

T9

62

T11

1

fifo_depth[0]

auto[1]

auto[0]

auto[0]

auto[1]

546529

1

T4

130

T6

36

T9

34

fifo_depth[0]

auto[1]

auto[0]

auto[1]

auto[0]

579715

1

T4

55

T5

1

T9

44

fifo_depth[0]

auto[1]

auto[0]

auto[1]

auto[1]

623537

1

T5

2

T6

70

T7

99

fifo_depth[0]

auto[1]

auto[1]

auto[0]

auto[0]

631680

1

T3

43

T4

39

T6

47

fifo_depth[0]

auto[1]

auto[1]

auto[0]

auto[1]

563348

1

T6

68

T9

25

T10

2

fifo_depth[0]

auto[1]

auto[1]

auto[1]

auto[0]

573182

1

T4

39

T5

1

T6

52

fifo_depth[0]

auto[1]

auto[1]

auto[1]

auto[1]

579687

1

T4

11

T6

18

T8

56

fifo_depth[1]

auto[0]

auto[0]

auto[0]

auto[0]

4853

1

T22

9

T29

11

T146

6

fifo_depth[1]

auto[0]

auto[0]

auto[0]

auto[1]

4502

1

T8

2

T24

4

T29

8

fifo_depth[1]

auto[0]

auto[0]

auto[1]

auto[0]

4338

1

T23

17

T26

5

T147

1

fifo_depth[1]

auto[0]

auto[0]

auto[1]

auto[1]

4172

1

T1

1

T23

33

T29

1

fifo_depth[1]

auto[0]

auto[1]

auto[0]

auto[0]

44287

1

T6

2

T9

2

T24

12

fifo_depth[1]

auto[0]

auto[1]

auto[0]

auto[1]

4435

1

T10

1

T27

1

T69

2

fifo_depth[1]

auto[0]

auto[1]

auto[1]

auto[0]

5034

1

T6

1

T21

1

T67

6

fifo_depth[1]

auto[0]

auto[1]

auto[1]

auto[1]

4780

1

T4

1

T9

1

T22

13

fifo_depth[1]

auto[1]

auto[0]

auto[0]

auto[0]

8074

1

T6

1

T9

1

T26

19

fifo_depth[1]

auto[1]

auto[0]

auto[0]

auto[1]

7351

1

T9

2

T22

12

T23

17

fifo_depth[1]

auto[1]

auto[0]

auto[1]

auto[0]

7890

1

T4

4

T157

1

T60

5

fifo_depth[1]

auto[1]

auto[0]

auto[1]

auto[1]

7591

1

T6

1

T8

2

T9

2

fifo_depth[1]

auto[1]

auto[1]

auto[0]

auto[0]

9792

1

T4

1

T138

124

T67

6

fifo_depth[1]

auto[1]

auto[1]

auto[0]

auto[1]

7297

1

T6

3

T9

2

T10

1

fifo_depth[1]

auto[1]

auto[1]

auto[1]

auto[0]

7322

1

T4

1

T6

2

T9

3

fifo_depth[1]

auto[1]

auto[1]

auto[1]

auto[1]

7543

1

T9

2

T22

7

T26

8

fifo_depth[2]

auto[0]

auto[0]

auto[0]

auto[0]

3762

1

T22

5

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99

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174

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22

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1

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62

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117

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16

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11

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14

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12

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86

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1

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1

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33

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1

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4

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36

fifo_depth[4]

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10

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4

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3

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1

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9

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15

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1

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2

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2

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1

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29

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14

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13

fifo_depth[4]

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1

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1

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7

fifo_depth[4]

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19

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1

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1

fifo_depth[4]

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1

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3

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27

T172

11

fifo_depth[4]

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1

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1

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17

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1

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1

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21

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28

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24

fifo_depth[4]

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1

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2

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95

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18

fifo_depth[4]

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1

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7

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8

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2

fifo_depth[4]

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1

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1

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8

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65

fifo_depth[5]

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1

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38

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1

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3

fifo_depth[5]

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1

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3

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17

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42

fifo_depth[5]

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1

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13

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6

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1

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1

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34

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1

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6

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1

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1

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2

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11

fifo_depth[5]

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1

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13

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12

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4

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19

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1

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11

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16

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12

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26

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1

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1

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17

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76

fifo_depth[5]

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1

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1

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19

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8

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2

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18

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1

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1

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4

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5

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60

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13

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11

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1

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19

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3

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11

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85

T60

1

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1

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22

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3

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1

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1

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1

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1

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8

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1

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7

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5

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4

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1

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18

T171

5

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54

fifo_depth[6]

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1

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2

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12

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21

fifo_depth[6]

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1

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7

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6

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14

fifo_depth[6]

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1

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1

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1

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1

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1

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12

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6

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12

fifo_depth[6]

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1

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10

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16

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16

fifo_depth[6]

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1

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8

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42

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17

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1

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13

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4

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1

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14

T28

2

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1

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1

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1

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1

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46

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12

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7

fifo_depth[6]

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1

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3

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8

T29

1

fifo_depth[6]

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3319

1

T26

8

T140

54

T60

1

fifo_depth[7]

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1

T147

15

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2

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2

fifo_depth[7]

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1

T147

7

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12

T161

7

fifo_depth[7]

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1

T23

8

T26

4

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28

fifo_depth[7]

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1

T23

5

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6

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26

fifo_depth[7]

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1

T60

1

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7

T172

14

fifo_depth[7]

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1

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1

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8

T172

4

fifo_depth[7]

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1167

1

T147

1

T92

1

T39

15

fifo_depth[7]

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1203

1

T23

10

T172

3

T70

7

fifo_depth[7]

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auto[0]

2395

1

T26

4

T147

10

T172

9

fifo_depth[7]

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2347

1

T23

16

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18

T172

8

fifo_depth[7]

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auto[0]

2488

1

T60

3

T147

11

T172

3

fifo_depth[7]

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auto[1]

2423

1

T25

15

T147

6

T172

23

fifo_depth[7]

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auto[0]

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2528

1

T138

1

T173

158

T147

13

fifo_depth[7]

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auto[0]

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2563

1

T147

29

T172

6

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7

fifo_depth[7]

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auto[1]

auto[0]

2577

1

T25

11

T60

2

T161

1

fifo_depth[7]

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auto[1]

auto[1]

2134

1

T26

4

T140

44

T29

1