Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	96	0	96	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
sta_fifo_depth	8	0	8	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	16	0	16	100.00	100	1	1	0
fifo_full_cross	16	0	16	100.00	100	1	1	0
fifo_depth_cross	64	0	64	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3408540

1

T1

31

T3

12665

T4

6470

auto[1]

1104995

1

T3

19247

T4

9737

T5

64

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1069672

1

T3

15892

T4

9280

T5

54

auto[1]

3443863

1

T1

31

T3

16020

T4

6927

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2795493

1

T5

54

T6

37528

T7

24

auto[1]

1718042

1

T1

31

T3

31912

T4

16207

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	3750437	1			T1	30		T3	25773		T4	14100
fifo_depth[1]	139435	1			T1	1		T3	641		T4	220
fifo_depth[2]	109877	1			T3	666		T4	210		T5	1
fifo_depth[3]	86727	1			T3	683		T4	205		T6	2107
fifo_depth[4]	69995	1			T3	662		T4	214		T6	1753
fifo_depth[5]	60396	1			T3	624		T4	229		T6	1521
fifo_depth[6]	56961	1			T3	648		T4	212		T6	1265
fifo_depth[7]	45917	1			T3	596		T4	208		T6	859

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

763098

1

T1

1

T3

6139

T4

2107

auto[1]

3750437

1

T1

30

T3

25773

T4

14100

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4510424

1

T1

31

T3

31912

T4

16207

auto[1]

3111

1

T7

1

T21

573

T22

2

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

26520

1

T7

2

T14

102

T15

15

auto[0]

auto[0]

auto[0]

auto[1]

22274

1

T7

8

T14

68

T15

23

auto[0]

auto[0]

auto[1]

auto[0]

430696

1

T6

13591

T9

1708

T29

2172

auto[0]

auto[0]

auto[1]

auto[1]

29007

1

T7

4

T14

16

T15

42

auto[0]

auto[1]

auto[0]

auto[0]

69912

1

T4

1246

T5

1

T7

3

auto[0]

auto[1]

auto[0]

auto[1]

49086

1

T3

1821

T4

782

T5

3

auto[0]

auto[1]

auto[1]

auto[0]

57434

1

T1

1

T3

1914

T5

2

auto[0]

auto[1]

auto[1]

auto[1]

78169

1

T3

2404

T4

79

T7

4

auto[1]

auto[0]

auto[0]

auto[0]

92751

1

T5

5

T7

4

T14

1855

auto[1]

auto[0]

auto[0]

auto[1]

84923

1

T5

16

T7

2

T14

1525

auto[1]

auto[0]

auto[1]

auto[0]

2034467

1

T5

9

T6

23937

T7

3

auto[1]

auto[0]

auto[1]

auto[1]

74855

1

T5

24

T7

1

T14

693

auto[1]

auto[1]

auto[0]

auto[0]

342645

1

T3

5076

T4

2354

T5

8

auto[1]

auto[1]

auto[0]

auto[1]

381561

1

T3

8995

T4

4898

T5

21

auto[1]

auto[1]

auto[1]

auto[0]

354115

1

T1

30

T3

5675

T4

2870

auto[1]

auto[1]

auto[1]

auto[1]

385120

1

T3

6027

T4

3978

T7

4

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

118406

1

T5

5

T7

6

T14

1957

auto[0]

auto[0]

auto[0]

auto[1]

106963

1

T5

16

T7

10

T14

1593

auto[0]

auto[0]

auto[1]

auto[0]

2464038

1

T5

9

T6

37528

T7

3

auto[0]

auto[0]

auto[1]

auto[1]

103578

1

T5

24

T7

5

T14

709

auto[0]

auto[1]

auto[0]

auto[0]

412455

1

T3

5076

T4

3600

T5

9

auto[0]

auto[1]

auto[0]

auto[1]

430547

1

T3

10816

T4

5680

T5

24

auto[0]

auto[1]

auto[1]

auto[0]

411454

1

T1

31

T3

7589

T4

2870

auto[0]

auto[1]

auto[1]

auto[1]

462983

1

T3

8431

T4

4057

T7

8

auto[1]

auto[0]

auto[0]

auto[0]

865

1

T21

418

T46

1

T138

1

auto[1]

auto[0]

auto[0]

auto[1]

234

1

T21

5

T33

6

T36

1

auto[1]

auto[0]

auto[1]

auto[0]

1125

1

T21

82

T34

10

T139

1

auto[1]

auto[0]

auto[1]

auto[1]

284

1

T21

54

T45

1

T140

1

auto[1]

auto[1]

auto[0]

auto[0]

102

1

T21

11

T22

1

T140

1

auto[1]

auto[1]

auto[0]

auto[1]

100

1

T7

1

T46

1

T47

2

auto[1]

auto[1]

auto[1]

auto[0]

95

1

T21

3

T141

17

T142

2

auto[1]

auto[1]

auto[1]

auto[1]

306

1

T22

1

T123

1

T143

1

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth	hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	auto[0]	auto[0]	auto[0]	92751	1			T5	5		T7	4		T14	1855
fifo_depth[0]	auto[0]	auto[0]	auto[1]	84923	1			T5	16		T7	2		T14	1525
fifo_depth[0]	auto[0]	auto[1]	auto[0]	2034467	1			T5	9		T6	23937		T7	3
fifo_depth[0]	auto[0]	auto[1]	auto[1]	74855	1			T5	24		T7	1		T14	693
fifo_depth[0]	auto[1]	auto[0]	auto[0]	342645	1			T3	5076		T4	2354		T5	8
fifo_depth[0]	auto[1]	auto[0]	auto[1]	381561	1			T3	8995		T4	4898		T5	21
fifo_depth[0]	auto[1]	auto[1]	auto[0]	354115	1			T1	30		T3	5675		T4	2870
fifo_depth[0]	auto[1]	auto[1]	auto[1]	385120	1			T3	6027		T4	3978		T7	4
fifo_depth[1]	auto[0]	auto[0]	auto[0]	2021	1			T14	54		T15	3		T108	137
fifo_depth[1]	auto[0]	auto[0]	auto[1]	1702	1			T14	31		T15	2		T108	5
fifo_depth[1]	auto[0]	auto[1]	auto[0]	108965	1			T6	2389		T9	1133		T29	1422
fifo_depth[1]	auto[0]	auto[1]	auto[1]	1930	1			T14	10		T15	1		T28	38
fifo_depth[1]	auto[1]	auto[0]	auto[0]	6577	1			T4	134		T5	1		T144	1
fifo_depth[1]	auto[1]	auto[0]	auto[1]	5147	1			T3	179		T4	77		T5	3
fifo_depth[1]	auto[1]	auto[1]	auto[0]	5654	1			T1	1		T3	218		T5	1
fifo_depth[1]	auto[1]	auto[1]	auto[1]	7439	1			T3	244		T4	9		T8	36
fifo_depth[2]	auto[0]	auto[0]	auto[0]	1896	1			T14	27		T15	2		T108	151
fifo_depth[2]	auto[0]	auto[0]	auto[1]	1453	1			T14	20		T15	7		T108	8
fifo_depth[2]	auto[0]	auto[1]	auto[0]	79854	1			T6	2513		T9	357		T29	505
fifo_depth[2]	auto[0]	auto[1]	auto[1]	1804	1			T14	4		T15	18		T28	10
fifo_depth[2]	auto[1]	auto[0]	auto[0]	6701	1			T4	122		T28	1		T109	167
fifo_depth[2]	auto[1]	auto[0]	auto[1]	5187	1			T3	205		T4	82		T8	84
fifo_depth[2]	auto[1]	auto[1]	auto[0]	5610	1			T3	207		T5	1		T8	76
fifo_depth[2]	auto[1]	auto[1]	auto[1]	7372	1			T3	254		T4	6		T8	30
fifo_depth[3]	auto[0]	auto[0]	auto[0]	1350	1			T14	15		T15	2		T108	164
fifo_depth[3]	auto[0]	auto[0]	auto[1]	1070	1			T14	15		T15	3		T108	5
fifo_depth[3]	auto[0]	auto[1]	auto[0]	59080	1			T6	2107		T9	138		T29	182
fifo_depth[3]	auto[0]	auto[1]	auto[1]	1398	1			T14	2		T15	1		T28	11
fifo_depth[3]	auto[1]	auto[0]	auto[0]	6419	1			T4	123		T28	1		T109	183
fifo_depth[3]	auto[1]	auto[0]	auto[1]	4914	1			T3	193		T4	72		T8	76
fifo_depth[3]	auto[1]	auto[1]	auto[0]	5409	1			T3	225		T8	79		T14	5
fifo_depth[3]	auto[1]	auto[1]	auto[1]	7087	1			T3	265		T4	10		T8	38
fifo_depth[4]	auto[0]	auto[0]	auto[0]	1428	1			T14	5		T15	2		T108	151
fifo_depth[4]	auto[0]	auto[0]	auto[1]	1115	1			T14	2		T15	1		T108	4
fifo_depth[4]	auto[0]	auto[1]	auto[0]	41863	1			T6	1753		T9	59		T29	48
fifo_depth[4]	auto[0]	auto[1]	auto[1]	1593	1			T15	9		T28	3		T21	22
fifo_depth[4]	auto[1]	auto[0]	auto[0]	6634	1			T4	133		T109	160		T21	1
fifo_depth[4]	auto[1]	auto[0]	auto[1]	4863	1			T3	197		T4	74		T8	85
fifo_depth[4]	auto[1]	auto[1]	auto[0]	5367	1			T3	208		T8	77		T14	3
fifo_depth[4]	auto[1]	auto[1]	auto[1]	7132	1			T3	257		T4	7		T8	36
fifo_depth[5]	auto[0]	auto[0]	auto[0]	1188	1			T14	1		T15	3		T108	163
fifo_depth[5]	auto[0]	auto[0]	auto[1]	915	1			T15	5		T108	5		T21	1
fifo_depth[5]	auto[0]	auto[1]	auto[0]	33875	1			T6	1521		T9	14		T29	11
fifo_depth[5]	auto[0]	auto[1]	auto[1]	1214	1			T28	1		T21	1		T145	17
fifo_depth[5]	auto[1]	auto[0]	auto[0]	6335	1			T4	138		T109	175		T43	2
fifo_depth[5]	auto[1]	auto[0]	auto[1]	4735	1			T3	179		T4	83		T8	83
fifo_depth[5]	auto[1]	auto[1]	auto[0]	5217	1			T3	194		T8	72		T15	1
fifo_depth[5]	auto[1]	auto[1]	auto[1]	6917	1			T3	251		T4	8		T8	35
fifo_depth[6]	auto[0]	auto[0]	auto[0]	1504	1			T15	1		T108	132		T21	31
fifo_depth[6]	auto[0]	auto[0]	auto[1]	1575	1			T15	3		T108	4		T21	9
fifo_depth[6]	auto[0]	auto[1]	auto[0]	28980	1			T6	1265		T9	4		T29	2
fifo_depth[6]	auto[0]	auto[1]	auto[1]	1537	1			T15	12		T21	112		T145	19
fifo_depth[6]	auto[1]	auto[0]	auto[0]	6481	1			T4	130		T109	149		T43	2
fifo_depth[6]	auto[1]	auto[0]	auto[1]	4702	1			T3	206		T4	76		T8	87
fifo_depth[6]	auto[1]	auto[1]	auto[0]	5279	1			T3	204		T8	71		T15	3
fifo_depth[6]	auto[1]	auto[1]	auto[1]	6903	1			T3	238		T4	6		T8	39
fifo_depth[7]	auto[0]	auto[0]	auto[0]	1036	1			T108	149		T21	36		T145	45
fifo_depth[7]	auto[0]	auto[0]	auto[1]	869	1			T108	9		T21	10		T110	31
fifo_depth[7]	auto[0]	auto[1]	auto[0]	21739	1			T6	859		T9	3		T29	1
fifo_depth[7]	auto[0]	auto[1]	auto[1]	1095	1			T15	1		T21	5		T145	8
fifo_depth[7]	auto[1]	auto[0]	auto[0]	5852	1			T4	120		T109	154		T43	1
fifo_depth[7]	auto[1]	auto[0]	auto[1]	4208	1			T3	180		T4	84		T8	81
fifo_depth[7]	auto[1]	auto[1]	auto[0]	4754	1			T3	185		T8	81		T17	2
fifo_depth[7]	auto[1]	auto[1]	auto[1]	6364	1			T3	231		T4	4		T8	29