Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	16956249	1			T3	1044		T4	1937		T5	137
all_pins[1]	16956249	1			T3	1044		T4	1937		T5	137
all_pins[2]	16956249	1			T3	1044		T4	1937		T5	137

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	43500253	1			T3	2694		T4	5031		T5	357
values[0x1]	7368494	1			T3	438		T4	780		T5	54
transitions[0x0=>0x1]	7368348	1			T3	438		T4	780		T5	54
transitions[0x1=>0x0]	7368361	1			T3	438		T4	780		T5	54

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	16936787	1			T3	1031		T4	1907		T5	135
all_pins[0]	values[0x1]	19462	1			T3	13		T4	30		T5	2
all_pins[0]	transitions[0x0=>0x1]	19394	1			T3	13		T4	30		T5	2
all_pins[0]	transitions[0x1=>0x0]	7348704	1			T3	425		T4	750		T5	52
all_pins[1]	values[0x0]	16955976	1			T3	1044		T4	1937		T5	137
all_pins[1]	values[0x1]	273	1			T6	2		T18	1		T49	3
all_pins[1]	transitions[0x0=>0x1]	238	1			T6	2		T18	1		T49	3
all_pins[1]	transitions[0x1=>0x0]	19427	1			T3	13		T4	30		T5	2
all_pins[2]	values[0x0]	9607490	1			T3	619		T4	1187		T5	85
all_pins[2]	values[0x1]	7348759	1			T3	425		T4	750		T5	52
all_pins[2]	transitions[0x0=>0x1]	7348716	1			T3	425		T4	750		T5	52
all_pins[2]	transitions[0x1=>0x0]	230	1			T6	2		T18	1		T49	3