Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	20637835	1			T1	90		T3	27		T4	895
all_pins[1]	20637835	1			T1	90		T3	27		T4	895
all_pins[2]	20637835	1			T1	90		T3	27		T4	895

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	52833602	1			T1	270		T3	57		T4	2416
values[0x1]	9079903	1			T3	24		T4	269		T5	1372
transitions[0x0=>0x1]	9079672	1			T3	24		T4	269		T5	1372
transitions[0x1=>0x0]	9079683	1			T3	24		T4	269		T5	1372

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	20614526	1			T1	90		T3	27		T4	882
all_pins[0]	values[0x1]	23309	1			T4	13		T5	2		T6	23
all_pins[0]	transitions[0x0=>0x1]	23210	1			T4	13		T5	2		T6	23
all_pins[0]	transitions[0x1=>0x0]	9056047	1			T3	24		T4	256		T5	1370
all_pins[1]	values[0x0]	20637376	1			T1	90		T3	27		T4	895
all_pins[1]	values[0x1]	459	1			T12	2		T39	2		T40	1
all_pins[1]	transitions[0x0=>0x1]	392	1			T12	2		T39	2		T40	1
all_pins[1]	transitions[0x1=>0x0]	23242	1			T4	13		T5	2		T6	23
all_pins[2]	values[0x0]	11581700	1			T1	90		T3	3		T4	639
all_pins[2]	values[0x1]	9056135	1			T3	24		T4	256		T5	1370
all_pins[2]	transitions[0x0=>0x1]	9056070	1			T3	24		T4	256		T5	1370
all_pins[2]	transitions[0x1=>0x0]	394	1			T39	2		T40	1		T13	3