Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	6843273	1			T1	36		T3	32342		T4	16432
all_pins[1]	6843273	1			T1	36		T3	32342		T4	16432
all_pins[2]	6843273	1			T1	36		T3	32342		T4	16432

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	18704543	1			T1	104		T3	82658		T4	38937
values[0x1]	1825276	1			T1	4		T3	14368		T4	10359
transitions[0x0=>0x1]	1825189	1			T1	4		T3	14368		T4	10359
transitions[0x1=>0x0]	1825201	1			T1	4		T3	14368		T4	10359

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	6825756	1			T1	32		T3	32318		T4	16416
all_pins[0]	values[0x1]	17517	1			T1	4		T3	24		T4	16
all_pins[0]	transitions[0x0=>0x1]	17478	1			T1	4		T3	24		T4	16
all_pins[0]	transitions[0x1=>0x0]	1807590	1			T3	14344		T4	10343		T5	17
all_pins[1]	values[0x0]	6843131	1			T1	36		T3	32342		T4	16432
all_pins[1]	values[0x1]	142	1			T21	1		T33	2		T123	1
all_pins[1]	transitions[0x0=>0x1]	122	1			T21	1		T33	2		T123	1
all_pins[1]	transitions[0x1=>0x0]	17497	1			T1	4		T3	24		T4	16
all_pins[2]	values[0x0]	5035656	1			T1	36		T3	17998		T4	6089
all_pins[2]	values[0x1]	1807617	1			T3	14344		T4	10343		T5	17
all_pins[2]	transitions[0x0=>0x1]	1807589	1			T3	14344		T4	10343		T5	17
all_pins[2]	transitions[0x1=>0x0]	114	1			T21	1		T33	2		T123	1