Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 791 1 T20 21 T31 14 T65 10
all_values[1] 791 1 T20 21 T31 14 T65 10
all_values[2] 791 1 T20 21 T31 14 T65 10


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1246 1 T20 22 T31 17 T65 14
auto[1] 1127 1 T20 41 T31 25 T65 16


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 865 1 T20 33 T31 15 T65 6
auto[1] 1508 1 T20 30 T31 27 T65 24


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1369 1 T20 42 T31 24 T65 14
auto[1] 1004 1 T20 21 T31 18 T65 16


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 146 1 T31 1 T25 1 T21 10
all_values[0] auto[0] auto[0] auto[1] 70 1 T20 1 T21 2 T131 1
all_values[0] auto[0] auto[1] auto[0] 126 1 T20 6 T31 4 T21 5
all_values[0] auto[0] auto[1] auto[1] 94 1 T20 3 T31 3 T65 2
all_values[0] auto[1] auto[0] auto[1] 177 1 T20 5 T31 2 T65 5
all_values[0] auto[1] auto[1] auto[1] 178 1 T20 6 T31 4 T65 3
all_values[1] auto[0] auto[0] auto[0] 149 1 T20 5 T31 1 T21 6
all_values[1] auto[0] auto[0] auto[1] 106 1 T20 2 T31 1 T65 2
all_values[1] auto[0] auto[1] auto[0] 134 1 T20 7 T31 3 T65 2
all_values[1] auto[0] auto[1] auto[1] 81 1 T20 2 T31 2 T65 1
all_values[1] auto[1] auto[0] auto[1] 185 1 T20 3 T31 4 T65 3
all_values[1] auto[1] auto[1] auto[1] 136 1 T20 2 T31 3 T65 2
all_values[2] auto[0] auto[0] auto[0] 169 1 T20 5 T31 3 T65 1
all_values[2] auto[0] auto[0] auto[1] 67 1 T31 1 T65 1 T21 2
all_values[2] auto[0] auto[1] auto[0] 141 1 T20 10 T31 3 T65 3
all_values[2] auto[0] auto[1] auto[1] 86 1 T20 1 T31 2 T65 2
all_values[2] auto[1] auto[0] auto[1] 177 1 T20 1 T31 4 T65 2
all_values[2] auto[1] auto[1] auto[1] 151 1 T20 4 T31 1 T65 1


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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