Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 1182 1 T12 7 T13 23 T82 30
all_values[1] 1182 1 T12 7 T13 23 T82 30
all_values[2] 1182 1 T12 7 T13 23 T82 30


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1716 1 T12 6 T13 34 T82 48
auto[1] 1830 1 T12 15 T13 35 T82 42


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1248 1 T12 4 T13 32 T82 26
auto[1] 2298 1 T12 17 T13 37 T82 64


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2042 1 T12 12 T13 45 T82 50
auto[1] 1504 1 T12 9 T13 24 T82 40


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 218 1 T12 1 T13 5 T82 9
all_values[0] auto[0] auto[0] auto[1] 108 1 T13 4 T148 5 T95 1
all_values[0] auto[0] auto[1] auto[0] 230 1 T12 1 T13 3 T82 5
all_values[0] auto[0] auto[1] auto[1] 145 1 T12 3 T82 6 T148 3
all_values[0] auto[1] auto[0] auto[1] 234 1 T12 1 T13 6 T82 5
all_values[0] auto[1] auto[1] auto[1] 247 1 T12 1 T13 5 T82 5
all_values[1] auto[0] auto[0] auto[0] 190 1 T13 3 T82 6 T148 4
all_values[1] auto[0] auto[0] auto[1] 150 1 T12 1 T13 4 T82 7
all_values[1] auto[0] auto[1] auto[0] 183 1 T12 2 T13 8 T82 2
all_values[1] auto[0] auto[1] auto[1] 151 1 T12 1 T13 1 T82 3
all_values[1] auto[1] auto[0] auto[1] 244 1 T12 1 T13 4 T82 10
all_values[1] auto[1] auto[1] auto[1] 264 1 T12 2 T13 3 T82 2
all_values[2] auto[0] auto[0] auto[0] 207 1 T13 4 T82 2 T148 3
all_values[2] auto[0] auto[0] auto[1] 121 1 T12 1 T13 3 T82 2
all_values[2] auto[0] auto[1] auto[0] 220 1 T13 9 T82 2 T148 6
all_values[2] auto[0] auto[1] auto[1] 119 1 T12 2 T13 1 T82 6
all_values[2] auto[1] auto[0] auto[1] 244 1 T12 1 T13 1 T82 7
all_values[2] auto[1] auto[1] auto[1] 271 1 T12 3 T13 5 T82 11


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%