Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 491 1 T10 4 T53 7 T11 24
all_values[1] 491 1 T10 4 T53 7 T11 24
all_values[2] 491 1 T10 4 T53 7 T11 24


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 802 1 T10 8 T53 11 T11 30
auto[1] 671 1 T10 4 T53 10 T11 42


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 511 1 T10 3 T53 7 T11 17
auto[1] 962 1 T10 9 T53 14 T11 55


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 854 1 T10 7 T53 10 T11 38
auto[1] 619 1 T10 5 T53 11 T11 34


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 94 1 T53 2 T11 4 T67 3
all_values[0] auto[0] auto[0] auto[1] 53 1 T10 1 T53 2 T11 2
all_values[0] auto[0] auto[1] auto[0] 86 1 T11 4 T67 1 T125 6
all_values[0] auto[0] auto[1] auto[1] 57 1 T10 1 T11 5 T67 1
all_values[0] auto[1] auto[0] auto[1] 115 1 T10 2 T11 5 T67 4
all_values[0] auto[1] auto[1] auto[1] 86 1 T53 3 T11 4 T125 5
all_values[1] auto[0] auto[0] auto[0] 82 1 T10 2 T53 2 T11 1
all_values[1] auto[0] auto[0] auto[1] 62 1 T10 1 T11 6 T67 2
all_values[1] auto[0] auto[1] auto[0] 63 1 T53 1 T11 3 T67 2
all_values[1] auto[0] auto[1] auto[1] 69 1 T53 1 T11 2 T126 2
all_values[1] auto[1] auto[0] auto[1] 124 1 T10 1 T53 2 T11 5
all_values[1] auto[1] auto[1] auto[1] 91 1 T53 1 T11 7 T126 1
all_values[2] auto[0] auto[0] auto[0] 109 1 T53 1 T11 2 T67 1
all_values[2] auto[0] auto[0] auto[1] 49 1 T67 1 T126 1 T125 2
all_values[2] auto[0] auto[1] auto[0] 77 1 T10 1 T53 1 T11 3
all_values[2] auto[0] auto[1] auto[1] 53 1 T10 1 T11 6 T67 2
all_values[2] auto[1] auto[0] auto[1] 114 1 T10 1 T53 2 T11 5
all_values[2] auto[1] auto[1] auto[1] 89 1 T10 1 T53 3 T11 8


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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