Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	90	0	90	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	0	5	100.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	0	7	100.00	100	1	1	0
key_swap	2	0	2	100.00	100	1	1	2
sha_en	2	0	2	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	16	0	16	100.00	100	1	1	0
hmac_dis_x_sha_en	4	0	4	100.00	100	1	1	0
key_x_digest_mismatch	35	0	35	100.00	100	1	1	0
key_length_x_digest_size	35	0	35	100.00	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for digest_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_invalid	3815	1			T3	3		T4	8		T7	2
sha2_none	3791	1			T3	1		T4	8		T5	2
sha2_512	7076	1			T3	6		T4	11		T5	2
sha2_384	7048	1			T3	4		T4	13		T7	4
sha2_256	5829	1			T3	5		T4	8		T7	3

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17741

1

T3

5

T4

27

T7

7

auto[1]

10176

1

T3

14

T4

21

T5

4

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10174

1

T3

9

T4

23

T5

2

auto[1]

17743

1

T3

10

T4

25

T5

2

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

14224

1

T3

11

T4

24

T5

2

disabled

13693

1

T3

8

T4

24

T5

2

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for key_length

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	4082	1			T3	3		T4	12		T7	2
key_none	7433	1			T3	6		T4	7		T7	1
key_1024	4107	1			T3	1		T4	7		T5	2
key_512	3503	1			T3	3		T4	6		T7	3
key_384	3140	1			T3	2		T4	6		T5	1
key_256	2855	1			T3	3		T4	6		T5	1
key_128	2731	1			T3	1		T4	4		T6	2

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17683

1

T3

12

T4

27

T5

2

auto[1]

10234

1

T3

7

T4

21

T5

2

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

27755

1

T3

19

T4

48

T5

4

disabled

162

1

T30

2

T51

3

T52

1

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

auto[0]

auto[0]

auto[0]

1390

1

T3

2

T4

2

T7

2

enabled

auto[0]

auto[0]

auto[1]

1487

1

T4

3

T7

1

T6

1

enabled

auto[0]

auto[1]

auto[0]

1468

1

T4

2

T6

1

T16

2

enabled

auto[0]

auto[1]

auto[1]

1433

1

T3

2

T4

3

T5

1

enabled

auto[1]

auto[0]

auto[0]

4129

1

T3

1

T4

5

T10

2

enabled

auto[1]

auto[0]

auto[1]

1458

1

T4

4

T7

2

T6

2

enabled

auto[1]

auto[1]

auto[0]

1465

1

T3

4

T4

3

T5

1

enabled

auto[1]

auto[1]

auto[1]

1394

1

T3

2

T4

2

T7

1

disabled

auto[0]

auto[0]

auto[0]

1065

1

T3

1

T4

4

T7

1

disabled

auto[0]

auto[0]

auto[1]

1148

1

T4

5

T7

1

T6

1

disabled

auto[0]

auto[1]

auto[0]

1102

1

T3

2

T4

4

T6

5

disabled

auto[0]

auto[1]

auto[1]

1081

1

T3

2

T5

1

T7

1

disabled

auto[1]

auto[0]

auto[0]

5947

1

T4

2

T9

1

T6

1

disabled

auto[1]

auto[0]

auto[1]

1117

1

T3

1

T4

2

T16

1

disabled

auto[1]

auto[1]

auto[0]

1117

1

T3

2

T4

5

T5

1

disabled

auto[1]

auto[1]

auto[1]

1116

1

T4

2

T6

2

T16

1

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

14157

1

T3

11

T4

24

T5

2

enabled

disabled

67

1

T30

1

T51

2

T52

1

disabled

disabled

95

1

T30

1

T51

1

T146

1

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

13598

1

T3

8

T4

24

T5

2

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	0	35	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1001	1			T29	1		T11	2		T30	1
key_invalid	sha2_none	767	1			T4	2		T6	1		T13	1
key_invalid	sha2_512	689	1			T3	2		T4	3		T6	1
key_invalid	sha2_384	765	1			T3	1		T4	4		T7	1
key_invalid	sha2_256	776	1			T4	3		T7	1		T10	1
key_none	sha2_invalid	428	1			T3	2		T4	1		T16	2
key_none	sha2_none	479	1			T13	1		T29	1		T17	1
key_none	sha2_512	2490	1			T3	2		T4	3		T29	1
key_none	sha2_384	2496	1			T4	2		T13	2		T147	1
key_none	sha2_256	1486	1			T3	2		T4	1		T7	1
key_1024	sha2_invalid	482	1			T4	3		T7	1		T6	2
key_1024	sha2_none	504	1			T4	1		T5	1		T13	1
key_1024	sha2_512	1686	1			T5	1		T13	1		T8	1
key_1024	sha2_384	854	1			T4	2		T7	1		T10	1
key_512	sha2_invalid	451	1			T4	1		T7	1		T6	1
key_512	sha2_none	505	1			T4	3		T7	1		T13	1
key_512	sha2_512	538	1			T3	1		T4	2		T16	1
key_512	sha2_384	1192	1			T3	1		T7	1		T9	1
key_512	sha2_256	779	1			T3	1		T16	1		T10	1
key_384	sha2_invalid	481	1			T4	2		T6	1		T16	1
key_384	sha2_none	484	1			T3	1		T5	1		T16	1
key_384	sha2_512	553	1			T4	1		T10	1		T12	1
key_384	sha2_384	592	1			T4	2		T9	1		T16	2
key_384	sha2_256	988	1			T3	1		T4	1		T13	2
key_256	sha2_invalid	470	1			T3	1		T10	1		T13	2
key_256	sha2_none	506	1			T4	2		T6	1		T16	1
key_256	sha2_512	558	1			T3	1		T4	1		T5	1
key_256	sha2_384	580	1			T3	1		T4	2		T7	1
key_256	sha2_256	690	1			T4	1		T6	1		T29	1
key_128	sha2_invalid	486	1			T4	1		T13	1		T29	1
key_128	sha2_none	537	1			T6	1		T13	2		T15	1
key_128	sha2_512	548	1			T4	1		T10	1		T13	2
key_128	sha2_384	557	1			T3	1		T4	1		T16	1
key_128	sha2_256	563	1			T4	1		T6	1		T16	1

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

535

1

T3

1

T4

1

T7

1

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	0	35	100.00

Automatically Generated Cross Bins for key_length_x_digest_size

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1001	1			T29	1		T11	2		T30	1
key_invalid	sha2_none	767	1			T4	2		T6	1		T13	1
key_invalid	sha2_512	689	1			T3	2		T4	3		T6	1
key_invalid	sha2_384	765	1			T3	1		T4	4		T7	1
key_invalid	sha2_256	776	1			T4	3		T7	1		T10	1
key_none	sha2_invalid	428	1			T3	2		T4	1		T16	2
key_none	sha2_none	479	1			T13	1		T29	1		T17	1
key_none	sha2_512	2490	1			T3	2		T4	3		T29	1
key_none	sha2_384	2496	1			T4	2		T13	2		T147	1
key_none	sha2_256	1486	1			T3	2		T4	1		T7	1
key_1024	sha2_invalid	482	1			T4	3		T7	1		T6	2
key_1024	sha2_none	504	1			T4	1		T5	1		T13	1
key_1024	sha2_512	1686	1			T5	1		T13	1		T8	1
key_1024	sha2_384	854	1			T4	2		T7	1		T10	1
key_1024	sha2_256	535	1			T3	1		T4	1		T7	1
key_512	sha2_invalid	451	1			T4	1		T7	1		T6	1
key_512	sha2_none	505	1			T4	3		T7	1		T13	1
key_512	sha2_512	538	1			T3	1		T4	2		T16	1
key_512	sha2_384	1192	1			T3	1		T7	1		T9	1
key_512	sha2_256	779	1			T3	1		T16	1		T10	1
key_384	sha2_invalid	481	1			T4	2		T6	1		T16	1
key_384	sha2_none	484	1			T3	1		T5	1		T16	1
key_384	sha2_512	553	1			T4	1		T10	1		T12	1
key_384	sha2_384	592	1			T4	2		T9	1		T16	2
key_384	sha2_256	988	1			T3	1		T4	1		T13	2
key_256	sha2_invalid	470	1			T3	1		T10	1		T13	2
key_256	sha2_none	506	1			T4	2		T6	1		T16	1
key_256	sha2_512	558	1			T3	1		T4	1		T5	1
key_256	sha2_384	580	1			T3	1		T4	2		T7	1
key_256	sha2_256	690	1			T4	1		T6	1		T29	1
key_128	sha2_invalid	486	1			T4	1		T13	1		T29	1
key_128	sha2_none	537	1			T6	1		T13	2		T15	1
key_128	sha2_512	548	1			T4	1		T10	1		T13	2
key_128	sha2_384	557	1			T3	1		T4	1		T16	1
key_128	sha2_256	563	1			T4	1		T6	1		T16	1