Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	90	0	90	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	0	5	100.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	0	7	100.00	100	1	1	0
key_swap	2	0	2	100.00	100	1	1	2
sha_en	2	0	2	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	16	0	16	100.00	100	1	1	0
hmac_dis_x_sha_en	4	0	4	100.00	100	1	1	0
key_x_digest_mismatch	35	0	35	100.00	100	1	1	0
key_length_x_digest_size	35	0	35	100.00	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for digest_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_invalid	5010	1			T3	1		T4	4		T5	3
sha2_none	5092	1			T3	1		T4	2		T5	3
sha2_512	8413	1			T1	1		T4	4		T6	9
sha2_384	8410	1			T4	4		T5	2		T6	9
sha2_256	7251	1			T4	5		T6	8		T7	2

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21005

1

T3

2

T4

9

T5

2

auto[1]

13676

1

T1

1

T4

10

T5

6

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

13457

1

T1

1

T3

1

T4

11

auto[1]

21224

1

T3

1

T4

8

T5

4

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

18266

1

T3

1

T4

12

T5

5

disabled

16415

1

T1

1

T3

1

T4

7

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for key_length

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	5464	1			T4	2		T5	2		T6	7
key_none	8500	1			T4	1		T5	1		T6	5
key_1024	5092	1			T4	3		T6	5		T9	3
key_512	4328	1			T4	2		T5	2		T6	5
key_384	3982	1			T4	5		T5	1		T6	2
key_256	3621	1			T1	1		T3	1		T4	1
key_128	3584	1			T3	1		T4	5		T5	1

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21068

1

T3

2

T4

10

T5

4

auto[1]

13613

1

T1

1

T4

9

T5

4

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

34504

1

T1

1

T3

2

T4

19

disabled

177

1

T21

1

T67

1

T69

4

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

auto[0]

auto[0]

auto[0]

1943

1

T6

2

T9

2

T11

1

enabled

auto[0]

auto[0]

auto[1]

1921

1

T4

4

T6

3

T9

2

enabled

auto[0]

auto[1]

auto[0]

1885

1

T4

2

T5

1

T9

7

enabled

auto[0]

auto[1]

auto[1]

1969

1

T5

2

T6

4

T7

3

enabled

auto[1]

auto[0]

auto[0]

4595

1

T3

1

T4

1

T5

1

enabled

auto[1]

auto[0]

auto[1]

1917

1

T6

3

T9

3

T10

4

enabled

auto[1]

auto[1]

auto[0]

2081

1

T4

3

T5

1

T6

2

enabled

auto[1]

auto[1]

auto[1]

1955

1

T4

2

T6

2

T8

1

disabled

auto[0]

auto[0]

auto[0]

1423

1

T3

1

T4

2

T9

1

disabled

auto[0]

auto[0]

auto[1]

1476

1

T4

1

T8

1

T9

1

disabled

auto[0]

auto[1]

auto[0]

1422

1

T4

1

T5

1

T6

1

disabled

auto[0]

auto[1]

auto[1]

1418

1

T1

1

T4

1

T6

3

disabled

auto[1]

auto[0]

auto[0]

6247

1

T4

1

T6

5

T7

1

disabled

auto[1]

auto[0]

auto[1]

1483

1

T5

1

T6

5

T9

2

disabled

auto[1]

auto[1]

auto[0]

1472

1

T6

4

T7

1

T9

4

disabled

auto[1]

auto[1]

auto[1]

1474

1

T4

1

T5

1

T6

5

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

18193

1

T3

1

T4

12

T5

5

enabled

disabled

73

1

T67

1

T69

1

T70

1

disabled

disabled

104

1

T21

1

T69

3

T70

1

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

16311

1

T1

1

T3

1

T4

7

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	0	35	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1274	1			T5	1		T6	3		T9	1
key_invalid	sha2_none	1014	1			T5	1		T11	2		T25	1
key_invalid	sha2_512	994	1			T4	1		T6	2		T9	2
key_invalid	sha2_384	1059	1			T4	1		T6	2		T7	1
key_invalid	sha2_256	1000	1			T7	1		T8	1		T22	1
key_none	sha2_invalid	676	1			T5	1		T6	1		T9	1
key_none	sha2_none	669	1			T6	1		T11	2		T10	1
key_none	sha2_512	2630	1			T6	1		T21	1		T10	1
key_none	sha2_384	2717	1			T4	1		T6	1		T9	2
key_none	sha2_256	1735	1			T6	1		T9	3		T21	1
key_1024	sha2_invalid	598	1			T9	1		T22	1		T23	1
key_1024	sha2_none	715	1			T4	1		T6	1		T11	1
key_1024	sha2_512	1862	1			T6	1		T9	1		T22	1
key_1024	sha2_384	1063	1			T4	1		T10	1		T23	1
key_512	sha2_invalid	603	1			T5	1		T9	1		T11	2
key_512	sha2_none	689	1			T6	1		T9	2		T10	1
key_512	sha2_512	680	1			T4	1		T6	1		T10	2
key_512	sha2_384	1327	1			T5	1		T6	1		T138	120
key_512	sha2_256	957	1			T4	1		T6	2		T7	1
key_384	sha2_invalid	620	1			T4	2		T6	1		T9	2
key_384	sha2_none	654	1			T4	1		T7	2		T8	1
key_384	sha2_512	739	1			T4	1		T9	5		T22	1
key_384	sha2_384	743	1			T5	1		T6	1		T9	1
key_384	sha2_256	1167	1			T4	1		T9	2		T21	3
key_256	sha2_invalid	603	1			T6	4		T7	1		T9	1
key_256	sha2_none	651	1			T3	1		T6	2		T26	1
key_256	sha2_512	707	1			T1	1		T6	2		T8	1
key_256	sha2_384	735	1			T6	3		T10	1		T157	1
key_256	sha2_256	872	1			T4	1		T6	1		T9	1
key_128	sha2_invalid	613	1			T3	1		T4	2		T9	1
key_128	sha2_none	681	1			T5	1		T6	1		T7	1
key_128	sha2_512	783	1			T4	1		T6	1		T7	1
key_128	sha2_384	740	1			T4	1		T6	1		T9	3
key_128	sha2_256	710	1			T4	1		T6	1		T10	1

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

788

1

T4

1

T6

3

T9

1

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	0	35	100.00

Automatically Generated Cross Bins for key_length_x_digest_size

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1274	1			T5	1		T6	3		T9	1
key_invalid	sha2_none	1014	1			T5	1		T11	2		T25	1
key_invalid	sha2_512	994	1			T4	1		T6	2		T9	2
key_invalid	sha2_384	1059	1			T4	1		T6	2		T7	1
key_invalid	sha2_256	1000	1			T7	1		T8	1		T22	1
key_none	sha2_invalid	676	1			T5	1		T6	1		T9	1
key_none	sha2_none	669	1			T6	1		T11	2		T10	1
key_none	sha2_512	2630	1			T6	1		T21	1		T10	1
key_none	sha2_384	2717	1			T4	1		T6	1		T9	2
key_none	sha2_256	1735	1			T6	1		T9	3		T21	1
key_1024	sha2_invalid	598	1			T9	1		T22	1		T23	1
key_1024	sha2_none	715	1			T4	1		T6	1		T11	1
key_1024	sha2_512	1862	1			T6	1		T9	1		T22	1
key_1024	sha2_384	1063	1			T4	1		T10	1		T23	1
key_1024	sha2_256	788	1			T4	1		T6	3		T9	1
key_512	sha2_invalid	603	1			T5	1		T9	1		T11	2
key_512	sha2_none	689	1			T6	1		T9	2		T10	1
key_512	sha2_512	680	1			T4	1		T6	1		T10	2
key_512	sha2_384	1327	1			T5	1		T6	1		T138	120
key_512	sha2_256	957	1			T4	1		T6	2		T7	1
key_384	sha2_invalid	620	1			T4	2		T6	1		T9	2
key_384	sha2_none	654	1			T4	1		T7	2		T8	1
key_384	sha2_512	739	1			T4	1		T9	5		T22	1
key_384	sha2_384	743	1			T5	1		T6	1		T9	1
key_384	sha2_256	1167	1			T4	1		T9	2		T21	3
key_256	sha2_invalid	603	1			T6	4		T7	1		T9	1
key_256	sha2_none	651	1			T3	1		T6	2		T26	1
key_256	sha2_512	707	1			T1	1		T6	2		T8	1
key_256	sha2_384	735	1			T6	3		T10	1		T157	1
key_256	sha2_256	872	1			T4	1		T6	1		T9	1
key_128	sha2_invalid	613	1			T3	1		T4	2		T9	1
key_128	sha2_none	681	1			T5	1		T6	1		T7	1
key_128	sha2_512	783	1			T4	1		T6	1		T7	1
key_128	sha2_384	740	1			T4	1		T6	1		T9	3
key_128	sha2_256	710	1			T4	1		T6	1		T10	1