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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.03 95.40 97.17 100.00 97.06 98.27 98.48 99.85


Total test records in report: 660
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html
T534 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.26408637 Feb 09 08:14:29 AM UTC 25 Feb 09 08:14:33 AM UTC 25 309350378 ps
T132 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_same_csr_outstanding.1702366893 Feb 09 08:14:29 AM UTC 25 Feb 09 08:14:33 AM UTC 25 110843699 ps
T535 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_tl_errors.4148276546 Feb 09 08:14:29 AM UTC 25 Feb 09 08:14:34 AM UTC 25 49820990 ps
T114 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_aliasing.784490676 Feb 09 08:14:29 AM UTC 25 Feb 09 08:14:43 AM UTC 25 470060924 ps
T536 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_bit_bash.2567897376 Feb 09 08:14:25 AM UTC 25 Feb 09 08:14:50 AM UTC 25 2203142230 ps
T537 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_intr_test.1234282180 Feb 09 08:14:51 AM UTC 25 Feb 09 08:14:53 AM UTC 25 39206338 ps
T538 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_hw_reset.2577792571 Feb 09 08:14:51 AM UTC 25 Feb 09 08:14:53 AM UTC 25 62304759 ps
T133 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_rw.1456730248 Feb 09 08:14:51 AM UTC 25 Feb 09 08:14:53 AM UTC 25 19569578 ps
T134 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_same_csr_outstanding.2885144719 Feb 09 08:14:51 AM UTC 25 Feb 09 08:14:55 AM UTC 25 207464613 ps
T539 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2557741876 Feb 09 08:14:51 AM UTC 25 Feb 09 08:14:55 AM UTC 25 100186399 ps
T80 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_tl_intg_err.999798325 Feb 09 08:14:51 AM UTC 25 Feb 09 08:14:55 AM UTC 25 1287707214 ps
T540 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_intr_test.1348806597 Feb 09 08:14:54 AM UTC 25 Feb 09 08:14:56 AM UTC 25 10951979 ps
T541 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_tl_errors.3626029250 Feb 09 08:14:53 AM UTC 25 Feb 09 08:14:57 AM UTC 25 49429378 ps
T81 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_tl_intg_err.384684464 Feb 09 08:14:54 AM UTC 25 Feb 09 08:14:58 AM UTC 25 55162004 ps
T115 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_rw.413375573 Feb 09 08:14:56 AM UTC 25 Feb 09 08:14:58 AM UTC 25 31142909 ps
T116 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_hw_reset.3181108851 Feb 09 08:14:56 AM UTC 25 Feb 09 08:14:59 AM UTC 25 332939177 ps
T117 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_aliasing.2374928608 Feb 09 08:14:51 AM UTC 25 Feb 09 08:15:01 AM UTC 25 1245243752 ps
T135 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_same_csr_outstanding.3530051716 Feb 09 08:14:58 AM UTC 25 Feb 09 08:15:02 AM UTC 25 93087235 ps
T118 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_bit_bash.4141689266 Feb 09 08:14:51 AM UTC 25 Feb 09 08:15:02 AM UTC 25 907533383 ps
T542 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_tl_errors.1924628524 Feb 09 08:14:59 AM UTC 25 Feb 09 08:15:02 AM UTC 25 203704372 ps
T543 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.2346103313 Feb 09 08:14:58 AM UTC 25 Feb 09 08:15:03 AM UTC 25 65702042 ps
T544 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_intr_test.45672716 Feb 09 08:15:01 AM UTC 25 Feb 09 08:15:03 AM UTC 25 24598124 ps
T119 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_hw_reset.3520994664 Feb 09 08:15:03 AM UTC 25 Feb 09 08:15:05 AM UTC 25 37901751 ps
T149 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_tl_intg_err.879073526 Feb 09 08:14:59 AM UTC 25 Feb 09 08:15:06 AM UTC 25 463710067 ps
T123 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_bit_bash.2374483775 Feb 09 08:14:56 AM UTC 25 Feb 09 08:15:07 AM UTC 25 2311934361 ps
T120 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_aliasing.3138028751 Feb 09 08:14:57 AM UTC 25 Feb 09 08:15:07 AM UTC 25 1201501107 ps
T121 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_rw.3818719312 Feb 09 08:15:06 AM UTC 25 Feb 09 08:15:08 AM UTC 25 16521848 ps
T545 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_intr_test.270100642 Feb 09 08:15:08 AM UTC 25 Feb 09 08:15:10 AM UTC 25 29756908 ps
T122 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_hw_reset.309058435 Feb 09 08:15:08 AM UTC 25 Feb 09 08:15:10 AM UTC 25 42063525 ps
T546 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_tl_intg_err.1626043437 Feb 09 08:15:08 AM UTC 25 Feb 09 08:15:11 AM UTC 25 53436662 ps
T547 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.626911508 Feb 09 08:15:07 AM UTC 25 Feb 09 08:15:11 AM UTC 25 71367138 ps
T136 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_same_csr_outstanding.2769802020 Feb 09 08:15:07 AM UTC 25 Feb 09 08:15:11 AM UTC 25 313911550 ps
T548 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_rw.3639906798 Feb 09 08:15:10 AM UTC 25 Feb 09 08:15:12 AM UTC 25 19908281 ps
T549 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_tl_errors.3747026479 Feb 09 08:15:08 AM UTC 25 Feb 09 08:15:12 AM UTC 25 186804055 ps
T137 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_same_csr_outstanding.1820486264 Feb 09 08:15:12 AM UTC 25 Feb 09 08:15:16 AM UTC 25 487007242 ps
T550 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_intr_test.3852758281 Feb 09 08:15:14 AM UTC 25 Feb 09 08:15:16 AM UTC 25 26273311 ps
T551 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.3827600645 Feb 09 08:15:12 AM UTC 25 Feb 09 08:15:17 AM UTC 25 120448970 ps
T124 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_aliasing.3184948800 Feb 09 08:15:06 AM UTC 25 Feb 09 08:15:17 AM UTC 25 450509239 ps
T552 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_tl_errors.2261954464 Feb 09 08:15:12 AM UTC 25 Feb 09 08:15:18 AM UTC 25 181897015 ps
T125 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_csr_rw.1496503531 Feb 09 08:15:16 AM UTC 25 Feb 09 08:15:19 AM UTC 25 33873327 ps
T154 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_tl_intg_err.4009741983 Feb 09 08:15:14 AM UTC 25 Feb 09 08:15:21 AM UTC 25 231380742 ps
T553 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_aliasing.2200074246 Feb 09 08:15:12 AM UTC 25 Feb 09 08:15:25 AM UTC 25 451884054 ps
T554 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_bit_bash.2568006615 Feb 09 08:15:06 AM UTC 25 Feb 09 08:15:27 AM UTC 25 1071890055 ps
T555 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_intr_test.3020885170 Feb 09 08:15:27 AM UTC 25 Feb 09 08:15:29 AM UTC 25 92667441 ps
T556 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.412098715 Feb 09 08:15:27 AM UTC 25 Feb 09 08:15:30 AM UTC 25 39494350 ps
T557 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_same_csr_outstanding.3680841613 Feb 09 08:15:27 AM UTC 25 Feb 09 08:15:31 AM UTC 25 185983540 ps
T558 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_tl_errors.2509555515 Feb 09 08:15:27 AM UTC 25 Feb 09 08:15:31 AM UTC 25 74155271 ps
T559 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_csr_rw.2129457506 Feb 09 08:15:29 AM UTC 25 Feb 09 08:15:32 AM UTC 25 28842976 ps
T150 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_tl_intg_err.3440295291 Feb 09 08:15:27 AM UTC 25 Feb 09 08:15:32 AM UTC 25 1270432624 ps
T560 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_bit_bash.3766517127 Feb 09 08:15:12 AM UTC 25 Feb 09 08:15:33 AM UTC 25 4390215876 ps
T561 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_same_csr_outstanding.1933203749 Feb 09 08:15:30 AM UTC 25 Feb 09 08:15:33 AM UTC 25 21682384 ps
T562 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3454691266 Feb 09 08:15:30 AM UTC 25 Feb 09 08:15:33 AM UTC 25 68013414 ps
T126 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_csr_rw.857417007 Feb 09 08:15:33 AM UTC 25 Feb 09 08:15:35 AM UTC 25 20974135 ps
T563 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_intr_test.91680934 Feb 09 08:15:33 AM UTC 25 Feb 09 08:15:35 AM UTC 25 23561173 ps
T564 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_intr_test.2178007862 Feb 09 08:15:33 AM UTC 25 Feb 09 08:15:35 AM UTC 25 18140847 ps
T565 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_tl_errors.525856299 Feb 09 08:15:30 AM UTC 25 Feb 09 08:15:36 AM UTC 25 126415499 ps
T566 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3560929956 Feb 09 08:15:33 AM UTC 25 Feb 09 08:15:36 AM UTC 25 100874746 ps
T151 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_tl_intg_err.2527529123 Feb 09 08:15:30 AM UTC 25 Feb 09 08:15:37 AM UTC 25 883202025 ps
T567 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_csr_rw.3864034005 Feb 09 08:15:35 AM UTC 25 Feb 09 08:15:38 AM UTC 25 81721701 ps
T568 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.2467361903 Feb 09 08:15:35 AM UTC 25 Feb 09 08:15:38 AM UTC 25 70966859 ps
T569 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_intr_test.4258325555 Feb 09 08:15:36 AM UTC 25 Feb 09 08:15:38 AM UTC 25 29032816 ps
T570 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_same_csr_outstanding.1601151727 Feb 09 08:15:35 AM UTC 25 Feb 09 08:15:38 AM UTC 25 123575447 ps
T571 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_tl_errors.4052154414 Feb 09 08:15:33 AM UTC 25 Feb 09 08:15:38 AM UTC 25 211718238 ps
T127 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_csr_rw.1638167855 Feb 09 08:15:36 AM UTC 25 Feb 09 08:15:39 AM UTC 25 21541224 ps
T572 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.2527640139 Feb 09 08:15:33 AM UTC 25 Feb 09 08:15:39 AM UTC 25 98592675 ps
T153 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_tl_intg_err.624294547 Feb 09 08:15:33 AM UTC 25 Feb 09 08:15:39 AM UTC 25 165927009 ps
T573 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_intr_test.114469407 Feb 09 08:15:43 AM UTC 25 Feb 09 08:15:45 AM UTC 25 11793013 ps
T574 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_tl_intg_err.1049314166 Feb 09 08:15:36 AM UTC 25 Feb 09 08:15:40 AM UTC 25 102358946 ps
T575 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.1762167898 Feb 09 08:15:37 AM UTC 25 Feb 09 08:15:41 AM UTC 25 480322154 ps
T576 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_tl_errors.3924727952 Feb 09 08:15:36 AM UTC 25 Feb 09 08:15:41 AM UTC 25 181425325 ps
T577 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_intr_test.245511589 Feb 09 08:15:38 AM UTC 25 Feb 09 08:15:41 AM UTC 25 17562850 ps
T578 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_same_csr_outstanding.1100443529 Feb 09 08:15:37 AM UTC 25 Feb 09 08:15:42 AM UTC 25 138793371 ps
T128 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_csr_rw.1976133345 Feb 09 08:15:40 AM UTC 25 Feb 09 08:15:42 AM UTC 25 32909262 ps
T579 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_intr_test.1074903466 Feb 09 08:15:40 AM UTC 25 Feb 09 08:15:42 AM UTC 25 47427273 ps
T155 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_tl_intg_err.917418564 Feb 09 08:15:40 AM UTC 25 Feb 09 08:15:43 AM UTC 25 120068358 ps
T580 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_csr_rw.30971634 Feb 09 08:15:41 AM UTC 25 Feb 09 08:15:43 AM UTC 25 21306335 ps
T581 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_tl_errors.1136331309 Feb 09 08:15:37 AM UTC 25 Feb 09 08:15:43 AM UTC 25 604906775 ps
T582 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_same_csr_outstanding.1263406200 Feb 09 08:15:40 AM UTC 25 Feb 09 08:15:43 AM UTC 25 428080769 ps
T152 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_tl_intg_err.1454733855 Feb 09 08:15:38 AM UTC 25 Feb 09 08:15:43 AM UTC 25 322526319 ps
T583 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_same_csr_outstanding.4003154626 Feb 09 08:15:42 AM UTC 25 Feb 09 08:15:45 AM UTC 25 216491738 ps
T584 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.1138886863 Feb 09 08:15:42 AM UTC 25 Feb 09 08:15:45 AM UTC 25 183344781 ps
T585 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.2158649939 Feb 09 08:15:40 AM UTC 25 Feb 09 08:15:45 AM UTC 25 180444923 ps
T129 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_csr_rw.3648048777 Feb 09 08:15:43 AM UTC 25 Feb 09 08:15:46 AM UTC 25 132179603 ps
T586 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_intr_test.1230163676 Feb 09 08:15:44 AM UTC 25 Feb 09 08:15:46 AM UTC 25 69625339 ps
T587 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_tl_errors.2448386412 Feb 09 08:15:42 AM UTC 25 Feb 09 08:15:46 AM UTC 25 298133268 ps
T588 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_tl_errors.205464800 Feb 09 08:15:40 AM UTC 25 Feb 09 08:15:47 AM UTC 25 161955618 ps
T589 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_csr_rw.1186856201 Feb 09 08:15:45 AM UTC 25 Feb 09 08:15:48 AM UTC 25 82514056 ps
T590 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_tl_errors.3018832712 Feb 09 08:15:44 AM UTC 25 Feb 09 08:15:48 AM UTC 25 86358493 ps
T591 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_same_csr_outstanding.270034348 Feb 09 08:15:44 AM UTC 25 Feb 09 08:15:48 AM UTC 25 531124712 ps
T592 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_same_csr_outstanding.381435623 Feb 09 08:15:45 AM UTC 25 Feb 09 08:15:49 AM UTC 25 111320321 ps
T593 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_intr_test.3903956231 Feb 09 08:15:48 AM UTC 25 Feb 09 08:15:50 AM UTC 25 24822813 ps
T156 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_tl_intg_err.2794014547 Feb 09 08:15:43 AM UTC 25 Feb 09 08:15:50 AM UTC 25 3189594634 ps
T594 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.476668119 Feb 09 08:15:46 AM UTC 25 Feb 09 08:15:50 AM UTC 25 196346130 ps
T130 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_csr_rw.1327634869 Feb 09 08:15:48 AM UTC 25 Feb 09 08:15:50 AM UTC 25 68140344 ps
T595 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_tl_intg_err.276950439 Feb 09 08:15:47 AM UTC 25 Feb 09 08:15:50 AM UTC 25 368790544 ps
T596 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_tl_intg_err.3740020761 Feb 09 08:15:44 AM UTC 25 Feb 09 08:15:50 AM UTC 25 220327862 ps
T597 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.1990036279 Feb 09 08:15:49 AM UTC 25 Feb 09 08:15:52 AM UTC 25 87614985 ps
T598 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_intr_test.2653531533 Feb 09 08:15:50 AM UTC 25 Feb 09 08:15:52 AM UTC 25 11556310 ps
T599 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_same_csr_outstanding.2423667576 Feb 09 08:15:48 AM UTC 25 Feb 09 08:15:52 AM UTC 25 148981909 ps
T600 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_csr_rw.3850051483 Feb 09 08:15:50 AM UTC 25 Feb 09 08:15:52 AM UTC 25 89990426 ps
T601 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_tl_errors.3259818792 Feb 09 08:15:47 AM UTC 25 Feb 09 08:15:53 AM UTC 25 269310438 ps
T602 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_intr_test.334137517 Feb 09 08:15:51 AM UTC 25 Feb 09 08:15:53 AM UTC 25 18691386 ps
T603 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.2971023491 Feb 09 08:15:51 AM UTC 25 Feb 09 08:15:54 AM UTC 25 72706101 ps
T604 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_same_csr_outstanding.1373589965 Feb 09 08:15:51 AM UTC 25 Feb 09 08:15:54 AM UTC 25 57888863 ps
T605 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_tl_errors.663267083 Feb 09 08:15:49 AM UTC 25 Feb 09 08:15:54 AM UTC 25 245128507 ps
T606 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_csr_rw.4274473316 Feb 09 08:15:52 AM UTC 25 Feb 09 08:15:54 AM UTC 25 13630134 ps
T607 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_tl_intg_err.3013271060 Feb 09 08:15:49 AM UTC 25 Feb 09 08:15:56 AM UTC 25 270671356 ps
T608 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_intr_test.3418351498 Feb 09 08:15:55 AM UTC 25 Feb 09 08:15:57 AM UTC 25 38122559 ps
T609 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_csr_rw.2138456766 Feb 09 08:15:55 AM UTC 25 Feb 09 08:15:57 AM UTC 25 59458632 ps
T610 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.2389080415 Feb 09 08:15:53 AM UTC 25 Feb 09 08:15:57 AM UTC 25 523439605 ps
T611 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_tl_errors.823039862 Feb 09 08:15:51 AM UTC 25 Feb 09 08:15:57 AM UTC 25 128996436 ps
T612 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_tl_errors.1170921858 Feb 09 08:15:53 AM UTC 25 Feb 09 08:15:58 AM UTC 25 182571852 ps
T613 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_same_csr_outstanding.2402790407 Feb 09 08:15:53 AM UTC 25 Feb 09 08:15:58 AM UTC 25 83564200 ps
T614 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_same_csr_outstanding.1180415168 Feb 09 08:15:55 AM UTC 25 Feb 09 08:15:59 AM UTC 25 38268055 ps
T615 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_tl_intg_err.2264372386 Feb 09 08:15:51 AM UTC 25 Feb 09 08:15:59 AM UTC 25 920817446 ps
T616 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_intr_test.1833883479 Feb 09 08:15:57 AM UTC 25 Feb 09 08:15:59 AM UTC 25 125504762 ps
T617 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_tl_errors.4229956868 Feb 09 08:15:56 AM UTC 25 Feb 09 08:15:59 AM UTC 25 262630095 ps
T618 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.968405911 Feb 09 08:15:55 AM UTC 25 Feb 09 08:16:00 AM UTC 25 95793010 ps
T619 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_tl_intg_err.556223751 Feb 09 08:15:55 AM UTC 25 Feb 09 08:16:00 AM UTC 25 178232197 ps
T620 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_csr_rw.2706028495 Feb 09 08:15:58 AM UTC 25 Feb 09 08:16:00 AM UTC 25 52195558 ps
T621 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_intr_test.2050999625 Feb 09 08:15:59 AM UTC 25 Feb 09 08:16:01 AM UTC 25 17524234 ps
T622 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_same_csr_outstanding.2455226578 Feb 09 08:15:58 AM UTC 25 Feb 09 08:16:02 AM UTC 25 387702374 ps
T623 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_tl_intg_err.2451905876 Feb 09 08:15:58 AM UTC 25 Feb 09 08:16:02 AM UTC 25 392823737 ps
T624 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_csr_rw.2189458225 Feb 09 08:16:00 AM UTC 25 Feb 09 08:16:02 AM UTC 25 13319697 ps
T625 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/20.hmac_intr_test.2840072224 Feb 09 08:16:01 AM UTC 25 Feb 09 08:16:03 AM UTC 25 11865845 ps
T626 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/21.hmac_intr_test.285476140 Feb 09 08:16:01 AM UTC 25 Feb 09 08:16:03 AM UTC 25 13037608 ps
T627 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/22.hmac_intr_test.4233137271 Feb 09 08:16:01 AM UTC 25 Feb 09 08:16:04 AM UTC 25 54053042 ps
T628 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.3987079922 Feb 09 08:16:00 AM UTC 25 Feb 09 08:16:04 AM UTC 25 74328630 ps
T629 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_same_csr_outstanding.1214368230 Feb 09 08:16:00 AM UTC 25 Feb 09 08:16:04 AM UTC 25 50884215 ps
T630 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_tl_intg_err.1255998630 Feb 09 08:15:57 AM UTC 25 Feb 09 08:16:04 AM UTC 25 1243674683 ps
T631 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_tl_errors.3771140033 Feb 09 08:15:58 AM UTC 25 Feb 09 08:16:04 AM UTC 25 127298216 ps
T632 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/24.hmac_intr_test.1152263864 Feb 09 08:16:04 AM UTC 25 Feb 09 08:16:05 AM UTC 25 28473773 ps
T633 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/25.hmac_intr_test.2806203308 Feb 09 08:16:04 AM UTC 25 Feb 09 08:16:06 AM UTC 25 12950870 ps
T634 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/23.hmac_intr_test.1771525274 Feb 09 08:16:03 AM UTC 25 Feb 09 08:16:06 AM UTC 25 38897454 ps
T635 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/27.hmac_intr_test.2497983364 Feb 09 08:16:04 AM UTC 25 Feb 09 08:16:06 AM UTC 25 15836733 ps
T636 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/26.hmac_intr_test.2305334591 Feb 09 08:16:04 AM UTC 25 Feb 09 08:16:06 AM UTC 25 17859922 ps
T637 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/29.hmac_intr_test.2052143352 Feb 09 08:16:05 AM UTC 25 Feb 09 08:16:07 AM UTC 25 22918890 ps
T638 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/28.hmac_intr_test.3703954297 Feb 09 08:16:05 AM UTC 25 Feb 09 08:16:07 AM UTC 25 56610295 ps
T639 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/31.hmac_intr_test.438738316 Feb 09 08:16:05 AM UTC 25 Feb 09 08:16:07 AM UTC 25 13563735 ps
T640 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/32.hmac_intr_test.987890620 Feb 09 08:16:05 AM UTC 25 Feb 09 08:16:07 AM UTC 25 14523007 ps
T641 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/30.hmac_intr_test.3807369937 Feb 09 08:16:05 AM UTC 25 Feb 09 08:16:07 AM UTC 25 60303795 ps
T642 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/34.hmac_intr_test.3538399370 Feb 09 08:16:05 AM UTC 25 Feb 09 08:16:07 AM UTC 25 24218672 ps
T643 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/33.hmac_intr_test.3318872497 Feb 09 08:16:05 AM UTC 25 Feb 09 08:16:07 AM UTC 25 14007296 ps
T644 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/35.hmac_intr_test.3599624041 Feb 09 08:16:06 AM UTC 25 Feb 09 08:16:08 AM UTC 25 17250500 ps
T645 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/36.hmac_intr_test.2868388162 Feb 09 08:16:06 AM UTC 25 Feb 09 08:16:08 AM UTC 25 68294702 ps
T646 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/38.hmac_intr_test.2535397815 Feb 09 08:16:06 AM UTC 25 Feb 09 08:16:08 AM UTC 25 37822290 ps
T647 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/37.hmac_intr_test.382886818 Feb 09 08:16:06 AM UTC 25 Feb 09 08:16:08 AM UTC 25 22590520 ps
T648 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/39.hmac_intr_test.3223793780 Feb 09 08:16:06 AM UTC 25 Feb 09 08:16:08 AM UTC 25 36993892 ps
T649 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/42.hmac_intr_test.946164318 Feb 09 08:16:07 AM UTC 25 Feb 09 08:16:09 AM UTC 25 47280731 ps
T650 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/41.hmac_intr_test.1126169850 Feb 09 08:16:07 AM UTC 25 Feb 09 08:16:09 AM UTC 25 16671079 ps
T651 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/40.hmac_intr_test.295534196 Feb 09 08:16:07 AM UTC 25 Feb 09 08:16:09 AM UTC 25 14641534 ps
T652 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/43.hmac_intr_test.553332912 Feb 09 08:16:07 AM UTC 25 Feb 09 08:16:09 AM UTC 25 57124773 ps
T653 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/44.hmac_intr_test.381947402 Feb 09 08:16:07 AM UTC 25 Feb 09 08:16:10 AM UTC 25 31768225 ps
T654 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/47.hmac_intr_test.1481878385 Feb 09 08:16:09 AM UTC 25 Feb 09 08:16:11 AM UTC 25 31950263 ps
T655 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/45.hmac_intr_test.3822623888 Feb 09 08:16:09 AM UTC 25 Feb 09 08:16:11 AM UTC 25 76438670 ps
T656 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/46.hmac_intr_test.2156475430 Feb 09 08:16:09 AM UTC 25 Feb 09 08:16:11 AM UTC 25 63025301 ps
T657 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/48.hmac_intr_test.3105838415 Feb 09 08:16:09 AM UTC 25 Feb 09 08:16:11 AM UTC 25 20799064 ps
T658 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/49.hmac_intr_test.3749447032 Feb 09 08:16:09 AM UTC 25 Feb 09 08:16:11 AM UTC 25 15360800 ps
T659 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.3650022882 Feb 09 08:15:44 AM UTC 25 Feb 09 08:20:25 AM UTC 25 77362391195 ps
T660 /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.3410975784 Feb 09 08:15:58 AM UTC 25 Feb 09 08:25:40 AM UTC 25 101731939014 ps

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/0.hmac_smoke.1792267734
Short name T6
Test name
Test status
Simulation time 2663060346 ps
CPU time 14.81 seconds
Started Feb 09 07:36:15 AM UTC 25
Finished Feb 09 07:36:31 AM UTC 25
Peak memory 207408 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1792267734 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.hmac_smoke.1792267734
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/0.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/0.hmac_stress_all_with_rand_reset.981833871
Short name T12
Test name
Test status
Simulation time 12779557933 ps
CPU time 189.13 seconds
Started Feb 09 07:36:15 AM UTC 25
Finished Feb 09 07:39:28 AM UTC 25
Peak memory 215808 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=981833871 -assert nopostproc +
UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all_with_rand_reset.981833871
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/0.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/2.hmac_long_msg.1020489591
Short name T147
Test name
Test status
Simulation time 2777358959 ps
CPU time 161.2 seconds
Started Feb 09 07:36:29 AM UTC 25
Finished Feb 09 07:39:13 AM UTC 25
Peak memory 215628 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020489591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 2.hmac_long_msg.1020489591
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/2.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/0.hmac_wipe_secret.3535608584
Short name T23
Test name
Test status
Simulation time 3621156473 ps
CPU time 55.44 seconds
Started Feb 09 07:36:15 AM UTC 25
Finished Feb 09 07:37:13 AM UTC 25
Peak memory 207216 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3535608584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_sec
ret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.hmac_wipe_secret.3535608584
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/0.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/8.hmac_stress_all_with_rand_reset.813962682
Short name T35
Test name
Test status
Simulation time 116098340440 ps
CPU time 1588.43 seconds
Started Feb 09 07:40:26 AM UTC 25
Finished Feb 09 08:07:13 AM UTC 25
Peak memory 743976 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=813962682 -assert nopostproc +
UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all_with_rand_reset.813962682
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/8.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_tl_intg_err.3275366556
Short name T79
Test name
Test status
Simulation time 1310157004 ps
CPU time 6.13 seconds
Started Feb 09 08:14:21 AM UTC 25
Finished Feb 09 08:14:29 AM UTC 25
Peak memory 209108 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3275366556 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.3275366556
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/0.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/12.hmac_stress_all.1846015974
Short name T148
Test name
Test status
Simulation time 2571600565 ps
CPU time 140.69 seconds
Started Feb 09 07:43:03 AM UTC 25
Finished Feb 09 07:45:26 AM UTC 25
Peak memory 215700 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1846015974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 12.hmac_stress_all.1846015974
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/12.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/2.hmac_error.4045288471
Short name T67
Test name
Test status
Simulation time 11783667450 ps
CPU time 55.71 seconds
Started Feb 09 07:36:37 AM UTC 25
Finished Feb 09 07:37:34 AM UTC 25
Peak memory 207208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045288471 -assert nopostproc +UVM_TESTNAME=hmac_base_tes
t +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.4045288471
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/2.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/3.hmac_sec_cm.3394861044
Short name T77
Test name
Test status
Simulation time 78465097 ps
CPU time 1.41 seconds
Started Feb 09 07:37:36 AM UTC 25
Finished Feb 09 07:37:38 AM UTC 25
Peak memory 235712 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394861044 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.3394861044
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/3.hmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/5.hmac_smoke.142900346
Short name T60
Test name
Test status
Simulation time 478793511 ps
CPU time 14.41 seconds
Started Feb 09 07:38:27 AM UTC 25
Finished Feb 09 07:38:43 AM UTC 25
Peak memory 207148 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=142900346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 5.hmac_smoke.142900346
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/5.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/18.hmac_back_pressure.1587477292
Short name T15
Test name
Test status
Simulation time 7197314867 ps
CPU time 72.27 seconds
Started Feb 09 07:46:13 AM UTC 25
Finished Feb 09 07:47:27 AM UTC 25
Peak memory 207212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1587477292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SE
Q=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.1587477292
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/18.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_aliasing.2374928608
Short name T117
Test name
Test status
Simulation time 1245243752 ps
CPU time 8.68 seconds
Started Feb 09 08:14:51 AM UTC 25
Finished Feb 09 08:15:01 AM UTC 25
Peak memory 209372 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2374928608 -assert nopostproc +UVM_TESTNAME=hmac_base_te
st +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.2374928608
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/1.hmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/21.hmac_burst_wr.358746863
Short name T65
Test name
Test status
Simulation time 860990196 ps
CPU time 45.38 seconds
Started Feb 09 07:48:45 AM UTC 25
Finished Feb 09 07:49:32 AM UTC 25
Peak memory 207260 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=358746863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 21.hmac_burst_wr.358746863
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/21.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/0.hmac_test_hmac512_vectors.1699645871
Short name T71
Test name
Test status
Simulation time 7259181723 ps
CPU time 88.5 seconds
Started Feb 09 07:36:15 AM UTC 25
Finished Feb 09 07:37:46 AM UTC 25
Peak memory 207272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1699645871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TE
ST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac512_vectors.1699645871
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/0.hmac_test_hmac512_vectors/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/0.hmac_error.1889339520
Short name T21
Test name
Test status
Simulation time 2975220530 ps
CPU time 35.05 seconds
Started Feb 09 07:36:15 AM UTC 25
Finished Feb 09 07:36:52 AM UTC 25
Peak memory 207284 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1889339520 -assert nopostproc +UVM_TESTNAME=hmac_base_tes
t +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.1889339520
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/0.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/8.hmac_back_pressure.763379555
Short name T163
Test name
Test status
Simulation time 18146395517 ps
CPU time 63.56 seconds
Started Feb 09 07:39:48 AM UTC 25
Finished Feb 09 07:40:53 AM UTC 25
Peak memory 207208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763379555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ
=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.763379555
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/8.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_tl_intg_err.2794014547
Short name T156
Test name
Test status
Simulation time 3189594634 ps
CPU time 5.76 seconds
Started Feb 09 08:15:43 AM UTC 25
Finished Feb 09 08:15:50 AM UTC 25
Peak memory 209116 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794014547 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.2794014547
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/12.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/11.hmac_stress_all.3577210655
Short name T108
Test name
Test status
Simulation time 14759583250 ps
CPU time 472.44 seconds
Started Feb 09 07:42:32 AM UTC 25
Finished Feb 09 07:50:30 AM UTC 25
Peak memory 207268 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3577210655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 11.hmac_stress_all.3577210655
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/11.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/2.hmac_alert_test.2103678868
Short name T72
Test name
Test status
Simulation time 14392417 ps
CPU time 0.91 seconds
Started Feb 09 07:37:03 AM UTC 25
Finished Feb 09 07:37:05 AM UTC 25
Peak memory 203992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2103678868 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.2103678868
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/2.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/1.hmac_long_msg.837389975
Short name T26
Test name
Test status
Simulation time 867914586 ps
CPU time 53.42 seconds
Started Feb 09 07:36:18 AM UTC 25
Finished Feb 09 07:37:14 AM UTC 25
Peak memory 207140 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837389975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 1.hmac_long_msg.837389975
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/1.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/2.hmac_wipe_secret.414264623
Short name T27
Test name
Test status
Simulation time 2095971908 ps
CPU time 36.51 seconds
Started Feb 09 07:36:38 AM UTC 25
Finished Feb 09 07:37:16 AM UTC 25
Peak memory 207244 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414264623 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secr
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 2.hmac_wipe_secret.414264623
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/2.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_rw.1209751565
Short name T131
Test name
Test status
Simulation time 84731836 ps
CPU time 1.1 seconds
Started Feb 09 08:14:25 AM UTC 25
Finished Feb 09 08:14:28 AM UTC 25
Peak memory 207972 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1209751565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UV
M_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.1209751565
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/0.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_tl_intg_err.879073526
Short name T149
Test name
Test status
Simulation time 463710067 ps
CPU time 5.55 seconds
Started Feb 09 08:14:59 AM UTC 25
Finished Feb 09 08:15:06 AM UTC 25
Peak memory 209252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879073526 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.879073526
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/3.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/11.hmac_burst_wr.2096737222
Short name T31
Test name
Test status
Simulation time 2386370806 ps
CPU time 31.93 seconds
Started Feb 09 07:42:00 AM UTC 25
Finished Feb 09 07:42:34 AM UTC 25
Peak memory 207472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2096737222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 11.hmac_burst_wr.2096737222
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/11.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/0.hmac_alert_test.123151696
Short name T2
Test name
Test status
Simulation time 32266988 ps
CPU time 0.58 seconds
Started Feb 09 07:36:15 AM UTC 25
Finished Feb 09 07:36:17 AM UTC 25
Peak memory 204644 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123151696 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.123151696
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/0.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_aliasing.784490676
Short name T114
Test name
Test status
Simulation time 470060924 ps
CPU time 12.8 seconds
Started Feb 09 08:14:29 AM UTC 25
Finished Feb 09 08:14:43 AM UTC 25
Peak memory 209348 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=784490676 -assert nopostproc +UVM_TESTNAME=hmac_base_tes
t +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.784490676
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/0.hmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_bit_bash.2567897376
Short name T536
Test name
Test status
Simulation time 2203142230 ps
CPU time 22.91 seconds
Started Feb 09 08:14:25 AM UTC 25
Finished Feb 09 08:14:50 AM UTC 25
Peak memory 209092 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2567897376 -assert nopostproc +UVM_TESTNAME=hmac_base_te
st +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.2567897376
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/0.hmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_hw_reset.2844291648
Short name T113
Test name
Test status
Simulation time 31513980 ps
CPU time 1.28 seconds
Started Feb 09 08:14:23 AM UTC 25
Finished Feb 09 08:14:26 AM UTC 25
Peak memory 207976 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2844291648 -assert nopostproc +UVM_TESTNAME=hmac_base_te
st +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.2844291648
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/0.hmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.26408637
Short name T534
Test name
Test status
Simulation time 309350378 ps
CPU time 2.8 seconds
Started Feb 09 08:14:29 AM UTC 25
Finished Feb 09 08:14:33 AM UTC 25
Peak memory 209552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26408637
-assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.26408637
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_intr_test.849151325
Short name T533
Test name
Test status
Simulation time 54245537 ps
CPU time 0.87 seconds
Started Feb 09 08:14:21 AM UTC 25
Finished Feb 09 08:14:23 AM UTC 25
Peak memory 206180 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=849151325 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TE
ST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.849151325
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/0.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_same_csr_outstanding.1702366893
Short name T132
Test name
Test status
Simulation time 110843699 ps
CPU time 3.07 seconds
Started Feb 09 08:14:29 AM UTC 25
Finished Feb 09 08:14:33 AM UTC 25
Peak memory 209416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702366893 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr_outstanding.1702366893
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/0.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_tl_errors.3287741721
Short name T532
Test name
Test status
Simulation time 1929421151 ps
CPU time 3.81 seconds
Started Feb 09 08:14:15 AM UTC 25
Finished Feb 09 08:14:21 AM UTC 25
Peak memory 209604 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3287741721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_T
EST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.3287741721
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/0.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_bit_bash.4141689266
Short name T118
Test name
Test status
Simulation time 907533383 ps
CPU time 10.37 seconds
Started Feb 09 08:14:51 AM UTC 25
Finished Feb 09 08:15:02 AM UTC 25
Peak memory 209032 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141689266 -assert nopostproc +UVM_TESTNAME=hmac_base_te
st +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.4141689266
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/1.hmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_hw_reset.2577792571
Short name T538
Test name
Test status
Simulation time 62304759 ps
CPU time 1.07 seconds
Started Feb 09 08:14:51 AM UTC 25
Finished Feb 09 08:14:53 AM UTC 25
Peak memory 207976 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2577792571 -assert nopostproc +UVM_TESTNAME=hmac_base_te
st +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.2577792571
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/1.hmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2557741876
Short name T539
Test name
Test status
Simulation time 100186399 ps
CPU time 3.38 seconds
Started Feb 09 08:14:51 AM UTC 25
Finished Feb 09 08:14:55 AM UTC 25
Peak memory 219440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=255774187
6 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.2557741876
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_rw.1456730248
Short name T133
Test name
Test status
Simulation time 19569578 ps
CPU time 1.11 seconds
Started Feb 09 08:14:51 AM UTC 25
Finished Feb 09 08:14:53 AM UTC 25
Peak memory 207972 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1456730248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UV
M_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.1456730248
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/1.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_intr_test.1234282180
Short name T537
Test name
Test status
Simulation time 39206338 ps
CPU time 0.83 seconds
Started Feb 09 08:14:51 AM UTC 25
Finished Feb 09 08:14:53 AM UTC 25
Peak memory 206076 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1234282180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_T
EST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.1234282180
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/1.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_same_csr_outstanding.2885144719
Short name T134
Test name
Test status
Simulation time 207464613 ps
CPU time 3.12 seconds
Started Feb 09 08:14:51 AM UTC 25
Finished Feb 09 08:14:55 AM UTC 25
Peak memory 209416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2885144719 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr_outstanding.2885144719
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/1.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_tl_errors.4148276546
Short name T535
Test name
Test status
Simulation time 49820990 ps
CPU time 3.57 seconds
Started Feb 09 08:14:29 AM UTC 25
Finished Feb 09 08:14:34 AM UTC 25
Peak memory 209540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4148276546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_T
EST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.4148276546
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/1.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_tl_intg_err.999798325
Short name T80
Test name
Test status
Simulation time 1287707214 ps
CPU time 3.67 seconds
Started Feb 09 08:14:51 AM UTC 25
Finished Feb 09 08:14:55 AM UTC 25
Peak memory 208900 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999798325 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.999798325
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/1.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.2158649939
Short name T585
Test name
Test status
Simulation time 180444923 ps
CPU time 4.33 seconds
Started Feb 09 08:15:40 AM UTC 25
Finished Feb 09 08:15:45 AM UTC 25
Peak memory 219520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=215864993
9 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.2158649939
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_csr_rw.1976133345
Short name T128
Test name
Test status
Simulation time 32909262 ps
CPU time 1.02 seconds
Started Feb 09 08:15:40 AM UTC 25
Finished Feb 09 08:15:42 AM UTC 25
Peak memory 207908 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1976133345 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UV
M_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.1976133345
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/10.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_intr_test.245511589
Short name T577
Test name
Test status
Simulation time 17562850 ps
CPU time 0.83 seconds
Started Feb 09 08:15:38 AM UTC 25
Finished Feb 09 08:15:41 AM UTC 25
Peak memory 206176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=245511589 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TE
ST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.245511589
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/10.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_same_csr_outstanding.1263406200
Short name T582
Test name
Test status
Simulation time 428080769 ps
CPU time 2.55 seconds
Started Feb 09 08:15:40 AM UTC 25
Finished Feb 09 08:15:43 AM UTC 25
Peak memory 208928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1263406200 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_csr_outstanding.1263406200
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/10.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_tl_errors.1136331309
Short name T581
Test name
Test status
Simulation time 604906775 ps
CPU time 4.58 seconds
Started Feb 09 08:15:37 AM UTC 25
Finished Feb 09 08:15:43 AM UTC 25
Peak memory 209328 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1136331309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_T
EST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.1136331309
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/10.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_tl_intg_err.1454733855
Short name T152
Test name
Test status
Simulation time 322526319 ps
CPU time 3.71 seconds
Started Feb 09 08:15:38 AM UTC 25
Finished Feb 09 08:15:43 AM UTC 25
Peak memory 209408 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1454733855 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.1454733855
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/10.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.1138886863
Short name T584
Test name
Test status
Simulation time 183344781 ps
CPU time 1.71 seconds
Started Feb 09 08:15:42 AM UTC 25
Finished Feb 09 08:15:45 AM UTC 25
Peak memory 207968 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=113888686
3 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.1138886863
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_csr_rw.30971634
Short name T580
Test name
Test status
Simulation time 21306335 ps
CPU time 1.02 seconds
Started Feb 09 08:15:41 AM UTC 25
Finished Feb 09 08:15:43 AM UTC 25
Peak memory 207972 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30971634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_
TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.30971634
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/11.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_intr_test.1074903466
Short name T579
Test name
Test status
Simulation time 47427273 ps
CPU time 0.91 seconds
Started Feb 09 08:15:40 AM UTC 25
Finished Feb 09 08:15:42 AM UTC 25
Peak memory 206176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1074903466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_T
EST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.1074903466
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/11.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_same_csr_outstanding.4003154626
Short name T583
Test name
Test status
Simulation time 216491738 ps
CPU time 1.67 seconds
Started Feb 09 08:15:42 AM UTC 25
Finished Feb 09 08:15:45 AM UTC 25
Peak memory 208012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4003154626 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_csr_outstanding.4003154626
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/11.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_tl_errors.205464800
Short name T588
Test name
Test status
Simulation time 161955618 ps
CPU time 5.74 seconds
Started Feb 09 08:15:40 AM UTC 25
Finished Feb 09 08:15:47 AM UTC 25
Peak memory 209368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205464800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TE
ST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.205464800
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/11.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_tl_intg_err.917418564
Short name T155
Test name
Test status
Simulation time 120068358 ps
CPU time 1.8 seconds
Started Feb 09 08:15:40 AM UTC 25
Finished Feb 09 08:15:43 AM UTC 25
Peak memory 207976 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=917418564 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.917418564
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/11.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.3650022882
Short name T659
Test name
Test status
Simulation time 77362391195 ps
CPU time 276.47 seconds
Started Feb 09 08:15:44 AM UTC 25
Finished Feb 09 08:20:25 AM UTC 25
Peak memory 219524 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=365002288
2 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.3650022882
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_csr_rw.3648048777
Short name T129
Test name
Test status
Simulation time 132179603 ps
CPU time 1.34 seconds
Started Feb 09 08:15:43 AM UTC 25
Finished Feb 09 08:15:46 AM UTC 25
Peak memory 208032 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3648048777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UV
M_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.3648048777
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/12.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_intr_test.114469407
Short name T573
Test name
Test status
Simulation time 11793013 ps
CPU time 0.87 seconds
Started Feb 09 08:15:43 AM UTC 25
Finished Feb 09 08:15:45 AM UTC 25
Peak memory 206032 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=114469407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TE
ST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.114469407
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/12.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_same_csr_outstanding.270034348
Short name T591
Test name
Test status
Simulation time 531124712 ps
CPU time 2.75 seconds
Started Feb 09 08:15:44 AM UTC 25
Finished Feb 09 08:15:48 AM UTC 25
Peak memory 209476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270034348 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_csr_outstanding.270034348
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/12.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_tl_errors.2448386412
Short name T587
Test name
Test status
Simulation time 298133268 ps
CPU time 3.16 seconds
Started Feb 09 08:15:42 AM UTC 25
Finished Feb 09 08:15:46 AM UTC 25
Peak memory 209276 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448386412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_T
EST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.2448386412
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/12.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.476668119
Short name T594
Test name
Test status
Simulation time 196346130 ps
CPU time 3.41 seconds
Started Feb 09 08:15:46 AM UTC 25
Finished Feb 09 08:15:50 AM UTC 25
Peak memory 209496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=476668119
-assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.476668119
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_csr_rw.1186856201
Short name T589
Test name
Test status
Simulation time 82514056 ps
CPU time 1.2 seconds
Started Feb 09 08:15:45 AM UTC 25
Finished Feb 09 08:15:48 AM UTC 25
Peak memory 207520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1186856201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UV
M_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.1186856201
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/13.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_intr_test.1230163676
Short name T586
Test name
Test status
Simulation time 69625339 ps
CPU time 0.8 seconds
Started Feb 09 08:15:44 AM UTC 25
Finished Feb 09 08:15:46 AM UTC 25
Peak memory 206176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1230163676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_T
EST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.1230163676
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/13.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_same_csr_outstanding.381435623
Short name T592
Test name
Test status
Simulation time 111320321 ps
CPU time 2.57 seconds
Started Feb 09 08:15:45 AM UTC 25
Finished Feb 09 08:15:49 AM UTC 25
Peak memory 209320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=381435623 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_csr_outstanding.381435623
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/13.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_tl_errors.3018832712
Short name T590
Test name
Test status
Simulation time 86358493 ps
CPU time 2.68 seconds
Started Feb 09 08:15:44 AM UTC 25
Finished Feb 09 08:15:48 AM UTC 25
Peak memory 209556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3018832712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_T
EST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.3018832712
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/13.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_tl_intg_err.3740020761
Short name T596
Test name
Test status
Simulation time 220327862 ps
CPU time 4.9 seconds
Started Feb 09 08:15:44 AM UTC 25
Finished Feb 09 08:15:50 AM UTC 25
Peak memory 209408 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3740020761 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.3740020761
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/13.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.1990036279
Short name T597
Test name
Test status
Simulation time 87614985 ps
CPU time 2.03 seconds
Started Feb 09 08:15:49 AM UTC 25
Finished Feb 09 08:15:52 AM UTC 25
Peak memory 209364 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199003627
9 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.1990036279
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_csr_rw.1327634869
Short name T130
Test name
Test status
Simulation time 68140344 ps
CPU time 1.23 seconds
Started Feb 09 08:15:48 AM UTC 25
Finished Feb 09 08:15:50 AM UTC 25
Peak memory 208032 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1327634869 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UV
M_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.1327634869
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/14.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_intr_test.3903956231
Short name T593
Test name
Test status
Simulation time 24822813 ps
CPU time 0.84 seconds
Started Feb 09 08:15:48 AM UTC 25
Finished Feb 09 08:15:50 AM UTC 25
Peak memory 206176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3903956231 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_T
EST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.3903956231
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/14.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_same_csr_outstanding.2423667576
Short name T599
Test name
Test status
Simulation time 148981909 ps
CPU time 3.57 seconds
Started Feb 09 08:15:48 AM UTC 25
Finished Feb 09 08:15:52 AM UTC 25
Peak memory 209104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2423667576 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_csr_outstanding.2423667576
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/14.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_tl_errors.3259818792
Short name T601
Test name
Test status
Simulation time 269310438 ps
CPU time 5.43 seconds
Started Feb 09 08:15:47 AM UTC 25
Finished Feb 09 08:15:53 AM UTC 25
Peak memory 209256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3259818792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_T
EST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.3259818792
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/14.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_tl_intg_err.276950439
Short name T595
Test name
Test status
Simulation time 368790544 ps
CPU time 2.6 seconds
Started Feb 09 08:15:47 AM UTC 25
Finished Feb 09 08:15:50 AM UTC 25
Peak memory 209100 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276950439 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.276950439
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/14.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.2971023491
Short name T603
Test name
Test status
Simulation time 72706101 ps
CPU time 1.46 seconds
Started Feb 09 08:15:51 AM UTC 25
Finished Feb 09 08:15:54 AM UTC 25
Peak memory 207980 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297102349
1 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.2971023491
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_csr_rw.3850051483
Short name T600
Test name
Test status
Simulation time 89990426 ps
CPU time 1.18 seconds
Started Feb 09 08:15:50 AM UTC 25
Finished Feb 09 08:15:52 AM UTC 25
Peak memory 208032 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3850051483 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UV
M_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.3850051483
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/15.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_intr_test.2653531533
Short name T598
Test name
Test status
Simulation time 11556310 ps
CPU time 0.85 seconds
Started Feb 09 08:15:50 AM UTC 25
Finished Feb 09 08:15:52 AM UTC 25
Peak memory 206176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2653531533 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_T
EST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.2653531533
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/15.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_same_csr_outstanding.1373589965
Short name T604
Test name
Test status
Simulation time 57888863 ps
CPU time 1.65 seconds
Started Feb 09 08:15:51 AM UTC 25
Finished Feb 09 08:15:54 AM UTC 25
Peak memory 208032 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1373589965 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_csr_outstanding.1373589965
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/15.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_tl_errors.663267083
Short name T605
Test name
Test status
Simulation time 245128507 ps
CPU time 4.25 seconds
Started Feb 09 08:15:49 AM UTC 25
Finished Feb 09 08:15:54 AM UTC 25
Peak memory 209348 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=663267083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TE
ST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.663267083
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/15.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_tl_intg_err.3013271060
Short name T607
Test name
Test status
Simulation time 270671356 ps
CPU time 5.75 seconds
Started Feb 09 08:15:49 AM UTC 25
Finished Feb 09 08:15:56 AM UTC 25
Peak memory 209080 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3013271060 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.3013271060
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/15.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.2389080415
Short name T610
Test name
Test status
Simulation time 523439605 ps
CPU time 2.66 seconds
Started Feb 09 08:15:53 AM UTC 25
Finished Feb 09 08:15:57 AM UTC 25
Peak memory 219444 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=238908041
5 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.2389080415
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_csr_rw.4274473316
Short name T606
Test name
Test status
Simulation time 13630134 ps
CPU time 0.96 seconds
Started Feb 09 08:15:52 AM UTC 25
Finished Feb 09 08:15:54 AM UTC 25
Peak memory 208032 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4274473316 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UV
M_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.4274473316
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/16.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_intr_test.334137517
Short name T602
Test name
Test status
Simulation time 18691386 ps
CPU time 0.85 seconds
Started Feb 09 08:15:51 AM UTC 25
Finished Feb 09 08:15:53 AM UTC 25
Peak memory 206176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=334137517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TE
ST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.334137517
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/16.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_same_csr_outstanding.2402790407
Short name T613
Test name
Test status
Simulation time 83564200 ps
CPU time 3 seconds
Started Feb 09 08:15:53 AM UTC 25
Finished Feb 09 08:15:58 AM UTC 25
Peak memory 209468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2402790407 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_csr_outstanding.2402790407
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/16.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_tl_errors.823039862
Short name T611
Test name
Test status
Simulation time 128996436 ps
CPU time 4.68 seconds
Started Feb 09 08:15:51 AM UTC 25
Finished Feb 09 08:15:57 AM UTC 25
Peak memory 209288 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=823039862 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TE
ST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.823039862
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/16.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_tl_intg_err.2264372386
Short name T615
Test name
Test status
Simulation time 920817446 ps
CPU time 6.35 seconds
Started Feb 09 08:15:51 AM UTC 25
Finished Feb 09 08:15:59 AM UTC 25
Peak memory 209100 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2264372386 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.2264372386
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/16.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.968405911
Short name T618
Test name
Test status
Simulation time 95793010 ps
CPU time 4.37 seconds
Started Feb 09 08:15:55 AM UTC 25
Finished Feb 09 08:16:00 AM UTC 25
Peak memory 209244 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=968405911
-assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.968405911
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_csr_rw.2138456766
Short name T609
Test name
Test status
Simulation time 59458632 ps
CPU time 1.26 seconds
Started Feb 09 08:15:55 AM UTC 25
Finished Feb 09 08:15:57 AM UTC 25
Peak memory 208032 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2138456766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UV
M_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.2138456766
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/17.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_intr_test.3418351498
Short name T608
Test name
Test status
Simulation time 38122559 ps
CPU time 0.77 seconds
Started Feb 09 08:15:55 AM UTC 25
Finished Feb 09 08:15:57 AM UTC 25
Peak memory 206112 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418351498 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_T
EST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.3418351498
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/17.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_same_csr_outstanding.1180415168
Short name T614
Test name
Test status
Simulation time 38268055 ps
CPU time 2.72 seconds
Started Feb 09 08:15:55 AM UTC 25
Finished Feb 09 08:15:59 AM UTC 25
Peak memory 209180 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1180415168 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_csr_outstanding.1180415168
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/17.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_tl_errors.1170921858
Short name T612
Test name
Test status
Simulation time 182571852 ps
CPU time 2.92 seconds
Started Feb 09 08:15:53 AM UTC 25
Finished Feb 09 08:15:58 AM UTC 25
Peak memory 209556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1170921858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_T
EST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.1170921858
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/17.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_tl_intg_err.556223751
Short name T619
Test name
Test status
Simulation time 178232197 ps
CPU time 4.59 seconds
Started Feb 09 08:15:55 AM UTC 25
Finished Feb 09 08:16:00 AM UTC 25
Peak memory 209156 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=556223751 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.556223751
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/17.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.3410975784
Short name T660
Test name
Test status
Simulation time 101731939014 ps
CPU time 574.95 seconds
Started Feb 09 08:15:58 AM UTC 25
Finished Feb 09 08:25:40 AM UTC 25
Peak memory 225820 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341097578
4 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.3410975784
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_csr_rw.2706028495
Short name T620
Test name
Test status
Simulation time 52195558 ps
CPU time 1.29 seconds
Started Feb 09 08:15:58 AM UTC 25
Finished Feb 09 08:16:00 AM UTC 25
Peak memory 208032 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2706028495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UV
M_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.2706028495
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/18.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_intr_test.1833883479
Short name T616
Test name
Test status
Simulation time 125504762 ps
CPU time 0.91 seconds
Started Feb 09 08:15:57 AM UTC 25
Finished Feb 09 08:15:59 AM UTC 25
Peak memory 206176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833883479 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_T
EST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.1833883479
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/18.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_same_csr_outstanding.2455226578
Short name T622
Test name
Test status
Simulation time 387702374 ps
CPU time 2.76 seconds
Started Feb 09 08:15:58 AM UTC 25
Finished Feb 09 08:16:02 AM UTC 25
Peak memory 209332 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2455226578 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_csr_outstanding.2455226578
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/18.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_tl_errors.4229956868
Short name T617
Test name
Test status
Simulation time 262630095 ps
CPU time 2.05 seconds
Started Feb 09 08:15:56 AM UTC 25
Finished Feb 09 08:15:59 AM UTC 25
Peak memory 209344 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4229956868 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_T
EST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.4229956868
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/18.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_tl_intg_err.1255998630
Short name T630
Test name
Test status
Simulation time 1243674683 ps
CPU time 6.11 seconds
Started Feb 09 08:15:57 AM UTC 25
Finished Feb 09 08:16:04 AM UTC 25
Peak memory 209220 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255998630 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.1255998630
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/18.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.3987079922
Short name T628
Test name
Test status
Simulation time 74328630 ps
CPU time 2.11 seconds
Started Feb 09 08:16:00 AM UTC 25
Finished Feb 09 08:16:04 AM UTC 25
Peak memory 225912 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398707992
2 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.3987079922
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_csr_rw.2189458225
Short name T624
Test name
Test status
Simulation time 13319697 ps
CPU time 0.98 seconds
Started Feb 09 08:16:00 AM UTC 25
Finished Feb 09 08:16:02 AM UTC 25
Peak memory 207712 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2189458225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UV
M_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.2189458225
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/19.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_intr_test.2050999625
Short name T621
Test name
Test status
Simulation time 17524234 ps
CPU time 0.88 seconds
Started Feb 09 08:15:59 AM UTC 25
Finished Feb 09 08:16:01 AM UTC 25
Peak memory 206112 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2050999625 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_T
EST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.2050999625
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/19.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_same_csr_outstanding.1214368230
Short name T629
Test name
Test status
Simulation time 50884215 ps
CPU time 2.5 seconds
Started Feb 09 08:16:00 AM UTC 25
Finished Feb 09 08:16:04 AM UTC 25
Peak memory 208860 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1214368230 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_csr_outstanding.1214368230
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/19.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_tl_errors.3771140033
Short name T631
Test name
Test status
Simulation time 127298216 ps
CPU time 4.93 seconds
Started Feb 09 08:15:58 AM UTC 25
Finished Feb 09 08:16:04 AM UTC 25
Peak memory 209460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3771140033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_T
EST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.3771140033
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/19.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_tl_intg_err.2451905876
Short name T623
Test name
Test status
Simulation time 392823737 ps
CPU time 2.72 seconds
Started Feb 09 08:15:58 AM UTC 25
Finished Feb 09 08:16:02 AM UTC 25
Peak memory 209100 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2451905876 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.2451905876
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/19.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_aliasing.3138028751
Short name T120
Test name
Test status
Simulation time 1201501107 ps
CPU time 8.28 seconds
Started Feb 09 08:14:57 AM UTC 25
Finished Feb 09 08:15:07 AM UTC 25
Peak memory 209028 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3138028751 -assert nopostproc +UVM_TESTNAME=hmac_base_te
st +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.3138028751
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/2.hmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_bit_bash.2374483775
Short name T123
Test name
Test status
Simulation time 2311934361 ps
CPU time 9.25 seconds
Started Feb 09 08:14:56 AM UTC 25
Finished Feb 09 08:15:07 AM UTC 25
Peak memory 209092 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2374483775 -assert nopostproc +UVM_TESTNAME=hmac_base_te
st +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.2374483775
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/2.hmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_hw_reset.3181108851
Short name T116
Test name
Test status
Simulation time 332939177 ps
CPU time 1.44 seconds
Started Feb 09 08:14:56 AM UTC 25
Finished Feb 09 08:14:59 AM UTC 25
Peak memory 207976 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181108851 -assert nopostproc +UVM_TESTNAME=hmac_base_te
st +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.3181108851
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/2.hmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.2346103313
Short name T543
Test name
Test status
Simulation time 65702042 ps
CPU time 3.21 seconds
Started Feb 09 08:14:58 AM UTC 25
Finished Feb 09 08:15:03 AM UTC 25
Peak memory 219520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234610331
3 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.2346103313
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_rw.413375573
Short name T115
Test name
Test status
Simulation time 31142909 ps
CPU time 1.09 seconds
Started Feb 09 08:14:56 AM UTC 25
Finished Feb 09 08:14:58 AM UTC 25
Peak memory 207976 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413375573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM
_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.413375573
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/2.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_intr_test.1348806597
Short name T540
Test name
Test status
Simulation time 10951979 ps
CPU time 0.83 seconds
Started Feb 09 08:14:54 AM UTC 25
Finished Feb 09 08:14:56 AM UTC 25
Peak memory 206236 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348806597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_T
EST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.1348806597
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/2.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_same_csr_outstanding.3530051716
Short name T135
Test name
Test status
Simulation time 93087235 ps
CPU time 2.37 seconds
Started Feb 09 08:14:58 AM UTC 25
Finished Feb 09 08:15:02 AM UTC 25
Peak memory 209152 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3530051716 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr_outstanding.3530051716
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/2.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_tl_errors.3626029250
Short name T541
Test name
Test status
Simulation time 49429378 ps
CPU time 3.26 seconds
Started Feb 09 08:14:53 AM UTC 25
Finished Feb 09 08:14:57 AM UTC 25
Peak memory 209344 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3626029250 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_T
EST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.3626029250
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/2.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_tl_intg_err.384684464
Short name T81
Test name
Test status
Simulation time 55162004 ps
CPU time 2.57 seconds
Started Feb 09 08:14:54 AM UTC 25
Finished Feb 09 08:14:58 AM UTC 25
Peak memory 209112 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=384684464 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.384684464
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/2.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/20.hmac_intr_test.2840072224
Short name T625
Test name
Test status
Simulation time 11865845 ps
CPU time 0.82 seconds
Started Feb 09 08:16:01 AM UTC 25
Finished Feb 09 08:16:03 AM UTC 25
Peak memory 206176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840072224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_T
EST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.2840072224
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/20.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/21.hmac_intr_test.285476140
Short name T626
Test name
Test status
Simulation time 13037608 ps
CPU time 0.85 seconds
Started Feb 09 08:16:01 AM UTC 25
Finished Feb 09 08:16:03 AM UTC 25
Peak memory 206176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=285476140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TE
ST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.285476140
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/21.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/22.hmac_intr_test.4233137271
Short name T627
Test name
Test status
Simulation time 54053042 ps
CPU time 0.86 seconds
Started Feb 09 08:16:01 AM UTC 25
Finished Feb 09 08:16:04 AM UTC 25
Peak memory 206176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4233137271 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_T
EST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.4233137271
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/22.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/23.hmac_intr_test.1771525274
Short name T634
Test name
Test status
Simulation time 38897454 ps
CPU time 0.87 seconds
Started Feb 09 08:16:03 AM UTC 25
Finished Feb 09 08:16:06 AM UTC 25
Peak memory 205984 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1771525274 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_T
EST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.1771525274
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/23.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/24.hmac_intr_test.1152263864
Short name T632
Test name
Test status
Simulation time 28473773 ps
CPU time 0.83 seconds
Started Feb 09 08:16:04 AM UTC 25
Finished Feb 09 08:16:05 AM UTC 25
Peak memory 206176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1152263864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_T
EST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.1152263864
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/24.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/25.hmac_intr_test.2806203308
Short name T633
Test name
Test status
Simulation time 12950870 ps
CPU time 0.84 seconds
Started Feb 09 08:16:04 AM UTC 25
Finished Feb 09 08:16:06 AM UTC 25
Peak memory 206176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2806203308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_T
EST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.2806203308
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/25.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/26.hmac_intr_test.2305334591
Short name T636
Test name
Test status
Simulation time 17859922 ps
CPU time 0.82 seconds
Started Feb 09 08:16:04 AM UTC 25
Finished Feb 09 08:16:06 AM UTC 25
Peak memory 206176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2305334591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_T
EST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.2305334591
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/26.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/27.hmac_intr_test.2497983364
Short name T635
Test name
Test status
Simulation time 15836733 ps
CPU time 0.8 seconds
Started Feb 09 08:16:04 AM UTC 25
Finished Feb 09 08:16:06 AM UTC 25
Peak memory 206112 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2497983364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_T
EST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.2497983364
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/27.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/28.hmac_intr_test.3703954297
Short name T638
Test name
Test status
Simulation time 56610295 ps
CPU time 0.9 seconds
Started Feb 09 08:16:05 AM UTC 25
Finished Feb 09 08:16:07 AM UTC 25
Peak memory 206176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3703954297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_T
EST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.3703954297
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/28.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/29.hmac_intr_test.2052143352
Short name T637
Test name
Test status
Simulation time 22918890 ps
CPU time 0.95 seconds
Started Feb 09 08:16:05 AM UTC 25
Finished Feb 09 08:16:07 AM UTC 25
Peak memory 206176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2052143352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_T
EST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.2052143352
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/29.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_aliasing.3184948800
Short name T124
Test name
Test status
Simulation time 450509239 ps
CPU time 10.19 seconds
Started Feb 09 08:15:06 AM UTC 25
Finished Feb 09 08:15:17 AM UTC 25
Peak memory 209088 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184948800 -assert nopostproc +UVM_TESTNAME=hmac_base_te
st +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.3184948800
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/3.hmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_bit_bash.2568006615
Short name T554
Test name
Test status
Simulation time 1071890055 ps
CPU time 19.76 seconds
Started Feb 09 08:15:06 AM UTC 25
Finished Feb 09 08:15:27 AM UTC 25
Peak memory 209028 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2568006615 -assert nopostproc +UVM_TESTNAME=hmac_base_te
st +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.2568006615
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/3.hmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_hw_reset.3520994664
Short name T119
Test name
Test status
Simulation time 37901751 ps
CPU time 1.03 seconds
Started Feb 09 08:15:03 AM UTC 25
Finished Feb 09 08:15:05 AM UTC 25
Peak memory 207976 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520994664 -assert nopostproc +UVM_TESTNAME=hmac_base_te
st +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.3520994664
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/3.hmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.626911508
Short name T547
Test name
Test status
Simulation time 71367138 ps
CPU time 2.48 seconds
Started Feb 09 08:15:07 AM UTC 25
Finished Feb 09 08:15:11 AM UTC 25
Peak memory 209288 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=626911508
-assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.626911508
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_rw.3818719312
Short name T121
Test name
Test status
Simulation time 16521848 ps
CPU time 1.11 seconds
Started Feb 09 08:15:06 AM UTC 25
Finished Feb 09 08:15:08 AM UTC 25
Peak memory 207972 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3818719312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UV
M_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.3818719312
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/3.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_intr_test.45672716
Short name T544
Test name
Test status
Simulation time 24598124 ps
CPU time 0.78 seconds
Started Feb 09 08:15:01 AM UTC 25
Finished Feb 09 08:15:03 AM UTC 25
Peak memory 206180 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=45672716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TES
T_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.45672716
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/3.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_same_csr_outstanding.2769802020
Short name T136
Test name
Test status
Simulation time 313911550 ps
CPU time 2.55 seconds
Started Feb 09 08:15:07 AM UTC 25
Finished Feb 09 08:15:11 AM UTC 25
Peak memory 209400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769802020 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr_outstanding.2769802020
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/3.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_tl_errors.1924628524
Short name T542
Test name
Test status
Simulation time 203704372 ps
CPU time 1.93 seconds
Started Feb 09 08:14:59 AM UTC 25
Finished Feb 09 08:15:02 AM UTC 25
Peak memory 208108 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1924628524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_T
EST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.1924628524
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/3.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/30.hmac_intr_test.3807369937
Short name T641
Test name
Test status
Simulation time 60303795 ps
CPU time 0.96 seconds
Started Feb 09 08:16:05 AM UTC 25
Finished Feb 09 08:16:07 AM UTC 25
Peak memory 206176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3807369937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_T
EST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.3807369937
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/30.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/31.hmac_intr_test.438738316
Short name T639
Test name
Test status
Simulation time 13563735 ps
CPU time 0.85 seconds
Started Feb 09 08:16:05 AM UTC 25
Finished Feb 09 08:16:07 AM UTC 25
Peak memory 206176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=438738316 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TE
ST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.438738316
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/31.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/32.hmac_intr_test.987890620
Short name T640
Test name
Test status
Simulation time 14523007 ps
CPU time 0.77 seconds
Started Feb 09 08:16:05 AM UTC 25
Finished Feb 09 08:16:07 AM UTC 25
Peak memory 206112 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987890620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TE
ST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.987890620
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/32.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/33.hmac_intr_test.3318872497
Short name T643
Test name
Test status
Simulation time 14007296 ps
CPU time 0.91 seconds
Started Feb 09 08:16:05 AM UTC 25
Finished Feb 09 08:16:07 AM UTC 25
Peak memory 206176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3318872497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_T
EST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.3318872497
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/33.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/34.hmac_intr_test.3538399370
Short name T642
Test name
Test status
Simulation time 24218672 ps
CPU time 0.88 seconds
Started Feb 09 08:16:05 AM UTC 25
Finished Feb 09 08:16:07 AM UTC 25
Peak memory 206176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3538399370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_T
EST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.3538399370
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/34.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/35.hmac_intr_test.3599624041
Short name T644
Test name
Test status
Simulation time 17250500 ps
CPU time 0.79 seconds
Started Feb 09 08:16:06 AM UTC 25
Finished Feb 09 08:16:08 AM UTC 25
Peak memory 206112 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3599624041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_T
EST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.3599624041
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/35.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/36.hmac_intr_test.2868388162
Short name T645
Test name
Test status
Simulation time 68294702 ps
CPU time 0.82 seconds
Started Feb 09 08:16:06 AM UTC 25
Finished Feb 09 08:16:08 AM UTC 25
Peak memory 206176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2868388162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_T
EST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.2868388162
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/36.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/37.hmac_intr_test.382886818
Short name T647
Test name
Test status
Simulation time 22590520 ps
CPU time 0.85 seconds
Started Feb 09 08:16:06 AM UTC 25
Finished Feb 09 08:16:08 AM UTC 25
Peak memory 206176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382886818 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TE
ST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.382886818
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/37.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/38.hmac_intr_test.2535397815
Short name T646
Test name
Test status
Simulation time 37822290 ps
CPU time 0.78 seconds
Started Feb 09 08:16:06 AM UTC 25
Finished Feb 09 08:16:08 AM UTC 25
Peak memory 206176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535397815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_T
EST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.2535397815
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/38.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/39.hmac_intr_test.3223793780
Short name T648
Test name
Test status
Simulation time 36993892 ps
CPU time 0.79 seconds
Started Feb 09 08:16:06 AM UTC 25
Finished Feb 09 08:16:08 AM UTC 25
Peak memory 206112 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3223793780 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_T
EST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.3223793780
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/39.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_aliasing.2200074246
Short name T553
Test name
Test status
Simulation time 451884054 ps
CPU time 11.39 seconds
Started Feb 09 08:15:12 AM UTC 25
Finished Feb 09 08:15:25 AM UTC 25
Peak memory 209088 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2200074246 -assert nopostproc +UVM_TESTNAME=hmac_base_te
st +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.2200074246
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/4.hmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_bit_bash.3766517127
Short name T560
Test name
Test status
Simulation time 4390215876 ps
CPU time 19.64 seconds
Started Feb 09 08:15:12 AM UTC 25
Finished Feb 09 08:15:33 AM UTC 25
Peak memory 209092 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3766517127 -assert nopostproc +UVM_TESTNAME=hmac_base_te
st +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.3766517127
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/4.hmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_hw_reset.309058435
Short name T122
Test name
Test status
Simulation time 42063525 ps
CPU time 1.12 seconds
Started Feb 09 08:15:08 AM UTC 25
Finished Feb 09 08:15:10 AM UTC 25
Peak memory 207972 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309058435 -assert nopostproc +UVM_TESTNAME=hmac_base_tes
t +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.309058435
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/4.hmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.3827600645
Short name T551
Test name
Test status
Simulation time 120448970 ps
CPU time 3.94 seconds
Started Feb 09 08:15:12 AM UTC 25
Finished Feb 09 08:15:17 AM UTC 25
Peak memory 219744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382760064
5 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.3827600645
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_rw.3639906798
Short name T548
Test name
Test status
Simulation time 19908281 ps
CPU time 1.08 seconds
Started Feb 09 08:15:10 AM UTC 25
Finished Feb 09 08:15:12 AM UTC 25
Peak memory 207972 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639906798 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UV
M_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.3639906798
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/4.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_intr_test.270100642
Short name T545
Test name
Test status
Simulation time 29756908 ps
CPU time 0.78 seconds
Started Feb 09 08:15:08 AM UTC 25
Finished Feb 09 08:15:10 AM UTC 25
Peak memory 206180 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270100642 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TE
ST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.270100642
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/4.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_same_csr_outstanding.1820486264
Short name T137
Test name
Test status
Simulation time 487007242 ps
CPU time 2.62 seconds
Started Feb 09 08:15:12 AM UTC 25
Finished Feb 09 08:15:16 AM UTC 25
Peak memory 209156 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1820486264 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr_outstanding.1820486264
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/4.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_tl_errors.3747026479
Short name T549
Test name
Test status
Simulation time 186804055 ps
CPU time 3.49 seconds
Started Feb 09 08:15:08 AM UTC 25
Finished Feb 09 08:15:12 AM UTC 25
Peak memory 209264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747026479 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_T
EST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.3747026479
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/4.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_tl_intg_err.1626043437
Short name T546
Test name
Test status
Simulation time 53436662 ps
CPU time 2.32 seconds
Started Feb 09 08:15:08 AM UTC 25
Finished Feb 09 08:15:11 AM UTC 25
Peak memory 209408 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626043437 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.1626043437
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/4.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/40.hmac_intr_test.295534196
Short name T651
Test name
Test status
Simulation time 14641534 ps
CPU time 0.87 seconds
Started Feb 09 08:16:07 AM UTC 25
Finished Feb 09 08:16:09 AM UTC 25
Peak memory 206176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295534196 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TE
ST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.295534196
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/40.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/41.hmac_intr_test.1126169850
Short name T650
Test name
Test status
Simulation time 16671079 ps
CPU time 0.88 seconds
Started Feb 09 08:16:07 AM UTC 25
Finished Feb 09 08:16:09 AM UTC 25
Peak memory 206176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1126169850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_T
EST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.1126169850
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/41.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/42.hmac_intr_test.946164318
Short name T649
Test name
Test status
Simulation time 47280731 ps
CPU time 0.82 seconds
Started Feb 09 08:16:07 AM UTC 25
Finished Feb 09 08:16:09 AM UTC 25
Peak memory 206152 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=946164318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TE
ST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.946164318
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/42.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/43.hmac_intr_test.553332912
Short name T652
Test name
Test status
Simulation time 57124773 ps
CPU time 0.87 seconds
Started Feb 09 08:16:07 AM UTC 25
Finished Feb 09 08:16:09 AM UTC 25
Peak memory 206176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=553332912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TE
ST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.553332912
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/43.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/44.hmac_intr_test.381947402
Short name T653
Test name
Test status
Simulation time 31768225 ps
CPU time 0.86 seconds
Started Feb 09 08:16:07 AM UTC 25
Finished Feb 09 08:16:10 AM UTC 25
Peak memory 206176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=381947402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TE
ST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.381947402
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/44.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/45.hmac_intr_test.3822623888
Short name T655
Test name
Test status
Simulation time 76438670 ps
CPU time 0.92 seconds
Started Feb 09 08:16:09 AM UTC 25
Finished Feb 09 08:16:11 AM UTC 25
Peak memory 206112 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3822623888 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_T
EST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.3822623888
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/45.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/46.hmac_intr_test.2156475430
Short name T656
Test name
Test status
Simulation time 63025301 ps
CPU time 0.89 seconds
Started Feb 09 08:16:09 AM UTC 25
Finished Feb 09 08:16:11 AM UTC 25
Peak memory 206176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2156475430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_T
EST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.2156475430
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/46.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/47.hmac_intr_test.1481878385
Short name T654
Test name
Test status
Simulation time 31950263 ps
CPU time 0.79 seconds
Started Feb 09 08:16:09 AM UTC 25
Finished Feb 09 08:16:11 AM UTC 25
Peak memory 206176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481878385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_T
EST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.1481878385
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/47.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/48.hmac_intr_test.3105838415
Short name T657
Test name
Test status
Simulation time 20799064 ps
CPU time 0.79 seconds
Started Feb 09 08:16:09 AM UTC 25
Finished Feb 09 08:16:11 AM UTC 25
Peak memory 206176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3105838415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_T
EST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.3105838415
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/48.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/49.hmac_intr_test.3749447032
Short name T658
Test name
Test status
Simulation time 15360800 ps
CPU time 0.94 seconds
Started Feb 09 08:16:09 AM UTC 25
Finished Feb 09 08:16:11 AM UTC 25
Peak memory 206176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749447032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_T
EST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.3749447032
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/49.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.412098715
Short name T556
Test name
Test status
Simulation time 39494350 ps
CPU time 1.63 seconds
Started Feb 09 08:15:27 AM UTC 25
Finished Feb 09 08:15:30 AM UTC 25
Peak memory 207980 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=412098715
-assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.412098715
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_csr_rw.1496503531
Short name T125
Test name
Test status
Simulation time 33873327 ps
CPU time 1.15 seconds
Started Feb 09 08:15:16 AM UTC 25
Finished Feb 09 08:15:19 AM UTC 25
Peak memory 207972 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1496503531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UV
M_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.1496503531
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/5.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_intr_test.3852758281
Short name T550
Test name
Test status
Simulation time 26273311 ps
CPU time 0.87 seconds
Started Feb 09 08:15:14 AM UTC 25
Finished Feb 09 08:15:16 AM UTC 25
Peak memory 206036 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3852758281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_T
EST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.3852758281
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/5.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_same_csr_outstanding.3680841613
Short name T557
Test name
Test status
Simulation time 185983540 ps
CPU time 2.63 seconds
Started Feb 09 08:15:27 AM UTC 25
Finished Feb 09 08:15:31 AM UTC 25
Peak memory 209224 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3680841613 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr_outstanding.3680841613
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/5.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_tl_errors.2261954464
Short name T552
Test name
Test status
Simulation time 181897015 ps
CPU time 4.54 seconds
Started Feb 09 08:15:12 AM UTC 25
Finished Feb 09 08:15:18 AM UTC 25
Peak memory 209272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2261954464 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_T
EST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.2261954464
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/5.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_tl_intg_err.4009741983
Short name T154
Test name
Test status
Simulation time 231380742 ps
CPU time 6.11 seconds
Started Feb 09 08:15:14 AM UTC 25
Finished Feb 09 08:15:21 AM UTC 25
Peak memory 208904 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4009741983 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.4009741983
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/5.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3454691266
Short name T562
Test name
Test status
Simulation time 68013414 ps
CPU time 1.65 seconds
Started Feb 09 08:15:30 AM UTC 25
Finished Feb 09 08:15:33 AM UTC 25
Peak memory 207980 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345469126
6 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.3454691266
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_csr_rw.2129457506
Short name T559
Test name
Test status
Simulation time 28842976 ps
CPU time 1.46 seconds
Started Feb 09 08:15:29 AM UTC 25
Finished Feb 09 08:15:32 AM UTC 25
Peak memory 207972 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2129457506 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UV
M_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.2129457506
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/6.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_intr_test.3020885170
Short name T555
Test name
Test status
Simulation time 92667441 ps
CPU time 0.72 seconds
Started Feb 09 08:15:27 AM UTC 25
Finished Feb 09 08:15:29 AM UTC 25
Peak memory 206236 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020885170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_T
EST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.3020885170
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/6.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_same_csr_outstanding.1933203749
Short name T561
Test name
Test status
Simulation time 21682384 ps
CPU time 1.44 seconds
Started Feb 09 08:15:30 AM UTC 25
Finished Feb 09 08:15:33 AM UTC 25
Peak memory 208028 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1933203749 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr_outstanding.1933203749
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/6.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_tl_errors.2509555515
Short name T558
Test name
Test status
Simulation time 74155271 ps
CPU time 2.53 seconds
Started Feb 09 08:15:27 AM UTC 25
Finished Feb 09 08:15:31 AM UTC 25
Peak memory 209192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2509555515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_T
EST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.2509555515
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/6.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_tl_intg_err.3440295291
Short name T150
Test name
Test status
Simulation time 1270432624 ps
CPU time 3.91 seconds
Started Feb 09 08:15:27 AM UTC 25
Finished Feb 09 08:15:32 AM UTC 25
Peak memory 209376 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3440295291 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.3440295291
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/6.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.2527640139
Short name T572
Test name
Test status
Simulation time 98592675 ps
CPU time 4.66 seconds
Started Feb 09 08:15:33 AM UTC 25
Finished Feb 09 08:15:39 AM UTC 25
Peak memory 219708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252764013
9 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.2527640139
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_csr_rw.857417007
Short name T126
Test name
Test status
Simulation time 20974135 ps
CPU time 0.98 seconds
Started Feb 09 08:15:33 AM UTC 25
Finished Feb 09 08:15:35 AM UTC 25
Peak memory 207976 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=857417007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM
_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.857417007
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/7.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_intr_test.2178007862
Short name T564
Test name
Test status
Simulation time 18140847 ps
CPU time 0.93 seconds
Started Feb 09 08:15:33 AM UTC 25
Finished Feb 09 08:15:35 AM UTC 25
Peak memory 206236 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2178007862 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_T
EST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.2178007862
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/7.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3560929956
Short name T566
Test name
Test status
Simulation time 100874746 ps
CPU time 2.39 seconds
Started Feb 09 08:15:33 AM UTC 25
Finished Feb 09 08:15:36 AM UTC 25
Peak memory 209072 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3560929956 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr_outstanding.3560929956
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/7.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_tl_errors.525856299
Short name T565
Test name
Test status
Simulation time 126415499 ps
CPU time 4.19 seconds
Started Feb 09 08:15:30 AM UTC 25
Finished Feb 09 08:15:36 AM UTC 25
Peak memory 209276 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=525856299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TE
ST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.525856299
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/7.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_tl_intg_err.2527529123
Short name T151
Test name
Test status
Simulation time 883202025 ps
CPU time 4.75 seconds
Started Feb 09 08:15:30 AM UTC 25
Finished Feb 09 08:15:37 AM UTC 25
Peak memory 209436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527529123 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.2527529123
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/7.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.2467361903
Short name T568
Test name
Test status
Simulation time 70966859 ps
CPU time 1.71 seconds
Started Feb 09 08:15:35 AM UTC 25
Finished Feb 09 08:15:38 AM UTC 25
Peak memory 207980 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246736190
3 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.2467361903
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_csr_rw.3864034005
Short name T567
Test name
Test status
Simulation time 81721701 ps
CPU time 1.27 seconds
Started Feb 09 08:15:35 AM UTC 25
Finished Feb 09 08:15:38 AM UTC 25
Peak memory 207972 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3864034005 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UV
M_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.3864034005
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/8.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_intr_test.91680934
Short name T563
Test name
Test status
Simulation time 23561173 ps
CPU time 0.71 seconds
Started Feb 09 08:15:33 AM UTC 25
Finished Feb 09 08:15:35 AM UTC 25
Peak memory 206116 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91680934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TES
T_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.91680934
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/8.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_same_csr_outstanding.1601151727
Short name T570
Test name
Test status
Simulation time 123575447 ps
CPU time 2.06 seconds
Started Feb 09 08:15:35 AM UTC 25
Finished Feb 09 08:15:38 AM UTC 25
Peak memory 209348 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1601151727 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr_outstanding.1601151727
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/8.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_tl_errors.4052154414
Short name T571
Test name
Test status
Simulation time 211718238 ps
CPU time 4.38 seconds
Started Feb 09 08:15:33 AM UTC 25
Finished Feb 09 08:15:38 AM UTC 25
Peak memory 209540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052154414 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_T
EST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.4052154414
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/8.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_tl_intg_err.624294547
Short name T153
Test name
Test status
Simulation time 165927009 ps
CPU time 4.68 seconds
Started Feb 09 08:15:33 AM UTC 25
Finished Feb 09 08:15:39 AM UTC 25
Peak memory 209076 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=624294547 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.624294547
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/8.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.1762167898
Short name T575
Test name
Test status
Simulation time 480322154 ps
CPU time 1.85 seconds
Started Feb 09 08:15:37 AM UTC 25
Finished Feb 09 08:15:41 AM UTC 25
Peak memory 207980 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=176216789
8 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.1762167898
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_csr_rw.1638167855
Short name T127
Test name
Test status
Simulation time 21541224 ps
CPU time 0.92 seconds
Started Feb 09 08:15:36 AM UTC 25
Finished Feb 09 08:15:39 AM UTC 25
Peak memory 207972 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638167855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UV
M_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.1638167855
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/9.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_intr_test.4258325555
Short name T569
Test name
Test status
Simulation time 29032816 ps
CPU time 0.9 seconds
Started Feb 09 08:15:36 AM UTC 25
Finished Feb 09 08:15:38 AM UTC 25
Peak memory 206236 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4258325555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_T
EST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.4258325555
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/9.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_same_csr_outstanding.1100443529
Short name T578
Test name
Test status
Simulation time 138793371 ps
CPU time 2.96 seconds
Started Feb 09 08:15:37 AM UTC 25
Finished Feb 09 08:15:42 AM UTC 25
Peak memory 209272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1100443529 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr_outstanding.1100443529
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/9.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_tl_errors.3924727952
Short name T576
Test name
Test status
Simulation time 181425325 ps
CPU time 3.07 seconds
Started Feb 09 08:15:36 AM UTC 25
Finished Feb 09 08:15:41 AM UTC 25
Peak memory 209460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3924727952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_T
EST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.3924727952
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/9.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_tl_intg_err.1049314166
Short name T574
Test name
Test status
Simulation time 102358946 ps
CPU time 2.77 seconds
Started Feb 09 08:15:36 AM UTC 25
Finished Feb 09 08:15:40 AM UTC 25
Peak memory 209092 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1049314166 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.1049314166
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/9.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/0.hmac_back_pressure.2991501338
Short name T5
Test name
Test status
Simulation time 228001184 ps
CPU time 11.51 seconds
Started Feb 09 07:36:15 AM UTC 25
Finished Feb 09 07:36:28 AM UTC 25
Peak memory 207184 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2991501338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SE
Q=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.2991501338
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/0.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/0.hmac_burst_wr.1968481927
Short name T3
Test name
Test status
Simulation time 82813801 ps
CPU time 1.3 seconds
Started Feb 09 07:36:15 AM UTC 25
Finished Feb 09 07:36:18 AM UTC 25
Peak memory 206192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1968481927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 0.hmac_burst_wr.1968481927
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/0.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/0.hmac_datapath_stress.1271953583
Short name T140
Test name
Test status
Simulation time 2227214173 ps
CPU time 78.78 seconds
Started Feb 09 07:36:15 AM UTC 25
Finished Feb 09 07:37:36 AM UTC 25
Peak memory 428572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1271953583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SE
Q=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.1271953583
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/0.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/0.hmac_long_msg.977207258
Short name T25
Test name
Test status
Simulation time 10535291050 ps
CPU time 53.9 seconds
Started Feb 09 07:36:15 AM UTC 25
Finished Feb 09 07:37:11 AM UTC 25
Peak memory 207204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=977207258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 0.hmac_long_msg.977207258
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/0.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/0.hmac_sec_cm.1448394714
Short name T18
Test name
Test status
Simulation time 32604364 ps
CPU time 0.86 seconds
Started Feb 09 07:36:15 AM UTC 25
Finished Feb 09 07:36:18 AM UTC 25
Peak memory 235712 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448394714 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.1448394714
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/0.hmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/0.hmac_stress_all.2867766174
Short name T514
Test name
Test status
Simulation time 95324704588 ps
CPU time 3229.84 seconds
Started Feb 09 07:36:15 AM UTC 25
Finished Feb 09 08:30:38 AM UTC 25
Peak memory 813272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867766174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 0.hmac_stress_all.2867766174
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/0.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/0.hmac_test_hmac256_vectors.3915380277
Short name T174
Test name
Test status
Simulation time 7135273129 ps
CPU time 102.59 seconds
Started Feb 09 07:36:15 AM UTC 25
Finished Feb 09 07:38:01 AM UTC 25
Peak memory 207352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3915380277 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TE
ST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac256_vectors.3915380277
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/0.hmac_test_hmac256_vectors/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/0.hmac_test_hmac384_vectors.2934390311
Short name T138
Test name
Test status
Simulation time 26760940354 ps
CPU time 56.86 seconds
Started Feb 09 07:36:15 AM UTC 25
Finished Feb 09 07:37:14 AM UTC 25
Peak memory 207212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2934390311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TE
ST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac384_vectors.2934390311
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/0.hmac_test_hmac384_vectors/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/0.hmac_test_sha256_vectors.3268313852
Short name T41
Test name
Test status
Simulation time 48283984509 ps
CPU time 665.35 seconds
Started Feb 09 07:36:15 AM UTC 25
Finished Feb 09 07:47:29 AM UTC 25
Peak memory 211096 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3268313852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TE
ST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha256_vectors.3268313852
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/0.hmac_test_sha256_vectors/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/0.hmac_test_sha384_vectors.892041834
Short name T501
Test name
Test status
Simulation time 292057280159 ps
CPU time 2770.96 seconds
Started Feb 09 07:36:15 AM UTC 25
Finished Feb 09 08:22:57 AM UTC 25
Peak memory 227400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=892041834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TES
T_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha384_vectors.892041834
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/0.hmac_test_sha384_vectors/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/0.hmac_test_sha512_vectors.1613717857
Short name T510
Test name
Test status
Simulation time 223227034170 ps
CPU time 3010.98 seconds
Started Feb 09 07:36:15 AM UTC 25
Finished Feb 09 08:27:00 AM UTC 25
Peak memory 221400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613717857 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TE
ST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha512_vectors.1613717857
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/0.hmac_test_sha512_vectors/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/1.hmac_alert_test.1371857644
Short name T19
Test name
Test status
Simulation time 21160398 ps
CPU time 0.86 seconds
Started Feb 09 07:36:26 AM UTC 25
Finished Feb 09 07:36:27 AM UTC 25
Peak memory 203992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1371857644 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.1371857644
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/1.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/1.hmac_back_pressure.6323879
Short name T10
Test name
Test status
Simulation time 3430003410 ps
CPU time 46.43 seconds
Started Feb 09 07:36:18 AM UTC 25
Finished Feb 09 07:37:07 AM UTC 25
Peak memory 207208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6323879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.6323879
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/1.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/1.hmac_burst_wr.4174378842
Short name T7
Test name
Test status
Simulation time 6122727300 ps
CPU time 15.42 seconds
Started Feb 09 07:36:19 AM UTC 25
Finished Feb 09 07:36:36 AM UTC 25
Peak memory 207256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174378842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 1.hmac_burst_wr.4174378842
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/1.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/1.hmac_datapath_stress.3810782909
Short name T312
Test name
Test status
Simulation time 5479717667 ps
CPU time 1127.58 seconds
Started Feb 09 07:36:19 AM UTC 25
Finished Feb 09 07:55:18 AM UTC 25
Peak memory 764192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3810782909 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SE
Q=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.3810782909
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/1.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/1.hmac_error.1743993713
Short name T185
Test name
Test status
Simulation time 3728635036 ps
CPU time 240.63 seconds
Started Feb 09 07:36:19 AM UTC 25
Finished Feb 09 07:40:23 AM UTC 25
Peak memory 207092 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1743993713 -assert nopostproc +UVM_TESTNAME=hmac_base_tes
t +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.1743993713
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/1.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/1.hmac_sec_cm.3396265849
Short name T20
Test name
Test status
Simulation time 128145626 ps
CPU time 1.3 seconds
Started Feb 09 07:36:26 AM UTC 25
Finished Feb 09 07:36:28 AM UTC 25
Peak memory 235712 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3396265849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.3396265849
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/1.hmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/1.hmac_smoke.2281725199
Short name T4
Test name
Test status
Simulation time 1872900839 ps
CPU time 7.41 seconds
Started Feb 09 07:36:15 AM UTC 25
Finished Feb 09 07:36:24 AM UTC 25
Peak memory 207256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2281725199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.hmac_smoke.2281725199
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/1.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/1.hmac_stress_all.219782731
Short name T525
Test name
Test status
Simulation time 380700412416 ps
CPU time 4703.26 seconds
Started Feb 09 07:36:21 AM UTC 25
Finished Feb 09 08:55:30 AM UTC 25
Peak memory 840048 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=219782731 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 1.hmac_stress_all.219782731
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/1.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/1.hmac_stress_all_with_rand_reset.2400274992
Short name T13
Test name
Test status
Simulation time 47731738224 ps
CPU time 319.67 seconds
Started Feb 09 07:36:23 AM UTC 25
Finished Feb 09 07:41:47 AM UTC 25
Peak memory 358668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400274992 -assert nopostproc
+UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all_with_rand_reset.2400274992
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/1.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/1.hmac_test_hmac256_vectors.29911676
Short name T68
Test name
Test status
Simulation time 10941462162 ps
CPU time 74.97 seconds
Started Feb 09 07:36:19 AM UTC 25
Finished Feb 09 07:37:36 AM UTC 25
Peak memory 207412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29911676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST
_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac256_vectors.29911676
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/1.hmac_test_hmac256_vectors/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/1.hmac_test_hmac384_vectors.2629783082
Short name T139
Test name
Test status
Simulation time 8116087534 ps
CPU time 72.14 seconds
Started Feb 09 07:36:21 AM UTC 25
Finished Feb 09 07:37:35 AM UTC 25
Peak memory 207212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2629783082 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TE
ST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac384_vectors.2629783082
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/1.hmac_test_hmac384_vectors/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/1.hmac_test_hmac512_vectors.4084525781
Short name T179
Test name
Test status
Simulation time 9832684097 ps
CPU time 135.49 seconds
Started Feb 09 07:36:21 AM UTC 25
Finished Feb 09 07:38:39 AM UTC 25
Peak memory 207160 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4084525781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TE
ST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac512_vectors.4084525781
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/1.hmac_test_hmac512_vectors/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/1.hmac_test_sha256_vectors.3747336273
Short name T244
Test name
Test status
Simulation time 225758328944 ps
CPU time 750.69 seconds
Started Feb 09 07:36:19 AM UTC 25
Finished Feb 09 07:48:58 AM UTC 25
Peak memory 207264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747336273 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TE
ST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha256_vectors.3747336273
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/1.hmac_test_sha256_vectors/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/1.hmac_test_sha384_vectors.555636911
Short name T485
Test name
Test status
Simulation time 77687802096 ps
CPU time 2313.21 seconds
Started Feb 09 07:36:19 AM UTC 25
Finished Feb 09 08:15:16 AM UTC 25
Peak memory 221332 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=555636911 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TES
T_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha384_vectors.555636911
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/1.hmac_test_sha384_vectors/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/1.hmac_test_sha512_vectors.1903636869
Short name T504
Test name
Test status
Simulation time 1119130449899 ps
CPU time 2861.46 seconds
Started Feb 09 07:36:19 AM UTC 25
Finished Feb 09 08:24:31 AM UTC 25
Peak memory 227544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1903636869 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TE
ST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha512_vectors.1903636869
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/1.hmac_test_sha512_vectors/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/1.hmac_wipe_secret.556952662
Short name T22
Test name
Test status
Simulation time 6427797230 ps
CPU time 40.48 seconds
Started Feb 09 07:36:19 AM UTC 25
Finished Feb 09 07:37:01 AM UTC 25
Peak memory 207252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=556952662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secr
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 1.hmac_wipe_secret.556952662
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/1.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/10.hmac_alert_test.1018980992
Short name T195
Test name
Test status
Simulation time 15378613 ps
CPU time 0.86 seconds
Started Feb 09 07:41:48 AM UTC 25
Finished Feb 09 07:41:50 AM UTC 25
Peak memory 203996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1018980992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.1018980992
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/10.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/10.hmac_back_pressure.907455872
Short name T101
Test name
Test status
Simulation time 4073634109 ps
CPU time 62.56 seconds
Started Feb 09 07:41:10 AM UTC 25
Finished Feb 09 07:42:15 AM UTC 25
Peak memory 207256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907455872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ
=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.907455872
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/10.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/10.hmac_burst_wr.527923225
Short name T99
Test name
Test status
Simulation time 8769032978 ps
CPU time 35.56 seconds
Started Feb 09 07:41:23 AM UTC 25
Finished Feb 09 07:42:00 AM UTC 25
Peak memory 207212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=527923225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 10.hmac_burst_wr.527923225
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/10.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/10.hmac_datapath_stress.1258088547
Short name T203
Test name
Test status
Simulation time 678896448 ps
CPU time 146.01 seconds
Started Feb 09 07:41:18 AM UTC 25
Finished Feb 09 07:43:47 AM UTC 25
Peak memory 459020 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1258088547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SE
Q=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.1258088547
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/10.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/10.hmac_error.1246295387
Short name T211
Test name
Test status
Simulation time 31055301598 ps
CPU time 177.19 seconds
Started Feb 09 07:41:37 AM UTC 25
Finished Feb 09 07:44:37 AM UTC 25
Peak memory 207272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246295387 -assert nopostproc +UVM_TESTNAME=hmac_base_tes
t +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.1246295387
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/10.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/10.hmac_long_msg.99174983
Short name T193
Test name
Test status
Simulation time 3653298273 ps
CPU time 31.77 seconds
Started Feb 09 07:41:06 AM UTC 25
Finished Feb 09 07:41:39 AM UTC 25
Peak memory 207204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99174983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 10.hmac_long_msg.99174983
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/10.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/10.hmac_smoke.2971137725
Short name T190
Test name
Test status
Simulation time 174816195 ps
CPU time 3.3 seconds
Started Feb 09 07:41:05 AM UTC 25
Finished Feb 09 07:41:10 AM UTC 25
Peak memory 207272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2971137725 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 10.hmac_smoke.2971137725
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/10.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/10.hmac_stress_all.3884945390
Short name T94
Test name
Test status
Simulation time 16480508317 ps
CPU time 248.14 seconds
Started Feb 09 07:41:42 AM UTC 25
Finished Feb 09 07:45:54 AM UTC 25
Peak memory 207208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3884945390 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 10.hmac_stress_all.3884945390
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/10.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/10.hmac_wipe_secret.2050157445
Short name T144
Test name
Test status
Simulation time 51183084316 ps
CPU time 170.09 seconds
Started Feb 09 07:41:40 AM UTC 25
Finished Feb 09 07:44:33 AM UTC 25
Peak memory 207204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2050157445 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_sec
ret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 10.hmac_wipe_secret.2050157445
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/10.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/11.hmac_alert_test.823051047
Short name T103
Test name
Test status
Simulation time 15444641 ps
CPU time 0.94 seconds
Started Feb 09 07:42:35 AM UTC 25
Finished Feb 09 07:42:37 AM UTC 25
Peak memory 203992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=823051047 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.823051047
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/11.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/11.hmac_back_pressure.58167579
Short name T100
Test name
Test status
Simulation time 477498813 ps
CPU time 19.4 seconds
Started Feb 09 07:41:54 AM UTC 25
Finished Feb 09 07:42:15 AM UTC 25
Peak memory 207140 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=58167579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.58167579
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/11.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/11.hmac_datapath_stress.3680684551
Short name T253
Test name
Test status
Simulation time 3312503620 ps
CPU time 474.52 seconds
Started Feb 09 07:41:55 AM UTC 25
Finished Feb 09 07:49:55 AM UTC 25
Peak memory 457052 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3680684551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SE
Q=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.3680684551
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/11.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/11.hmac_error.43120363
Short name T196
Test name
Test status
Simulation time 1055714249 ps
CPU time 37.77 seconds
Started Feb 09 07:42:16 AM UTC 25
Finished Feb 09 07:42:56 AM UTC 25
Peak memory 207072 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=43120363 -assert nopostproc +UVM_TESTNAME=hmac_base_test
+UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 11.hmac_error.43120363
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/11.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/11.hmac_long_msg.2178691476
Short name T231
Test name
Test status
Simulation time 11352091474 ps
CPU time 262.51 seconds
Started Feb 09 07:41:51 AM UTC 25
Finished Feb 09 07:46:18 AM UTC 25
Peak memory 217668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2178691476 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 11.hmac_long_msg.2178691476
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/11.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/11.hmac_smoke.1274293769
Short name T1
Test name
Test status
Simulation time 885152268 ps
CPU time 1.75 seconds
Started Feb 09 07:41:50 AM UTC 25
Finished Feb 09 07:41:53 AM UTC 25
Peak memory 206328 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1274293769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 11.hmac_smoke.1274293769
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/11.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/11.hmac_wipe_secret.1269189353
Short name T143
Test name
Test status
Simulation time 6611819015 ps
CPU time 96.09 seconds
Started Feb 09 07:42:16 AM UTC 25
Finished Feb 09 07:43:55 AM UTC 25
Peak memory 207344 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269189353 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_sec
ret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 11.hmac_wipe_secret.1269189353
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/11.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/12.hmac_alert_test.3083103552
Short name T199
Test name
Test status
Simulation time 12620414 ps
CPU time 0.8 seconds
Started Feb 09 07:43:22 AM UTC 25
Finished Feb 09 07:43:24 AM UTC 25
Peak memory 203996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083103552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.3083103552
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/12.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/12.hmac_back_pressure.3676502214
Short name T200
Test name
Test status
Simulation time 3171252473 ps
CPU time 39.62 seconds
Started Feb 09 07:42:50 AM UTC 25
Finished Feb 09 07:43:32 AM UTC 25
Peak memory 207268 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3676502214 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SE
Q=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.3676502214
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/12.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/12.hmac_burst_wr.1910731178
Short name T166
Test name
Test status
Simulation time 1923384509 ps
CPU time 23.78 seconds
Started Feb 09 07:42:56 AM UTC 25
Finished Feb 09 07:43:21 AM UTC 25
Peak memory 215636 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1910731178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 12.hmac_burst_wr.1910731178
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/12.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/12.hmac_datapath_stress.1373469711
Short name T262
Test name
Test status
Simulation time 2861931548 ps
CPU time 461.44 seconds
Started Feb 09 07:42:50 AM UTC 25
Finished Feb 09 07:50:37 AM UTC 25
Peak memory 735504 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1373469711 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SE
Q=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.1373469711
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/12.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/12.hmac_error.2402473700
Short name T198
Test name
Test status
Simulation time 1411178688 ps
CPU time 25.2 seconds
Started Feb 09 07:42:56 AM UTC 25
Finished Feb 09 07:43:23 AM UTC 25
Peak memory 207208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2402473700 -assert nopostproc +UVM_TESTNAME=hmac_base_tes
t +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.2402473700
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/12.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/12.hmac_long_msg.2820623894
Short name T223
Test name
Test status
Simulation time 2441783998 ps
CPU time 159.97 seconds
Started Feb 09 07:42:40 AM UTC 25
Finished Feb 09 07:45:23 AM UTC 25
Peak memory 207344 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2820623894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 12.hmac_long_msg.2820623894
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/12.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/12.hmac_smoke.2086070440
Short name T106
Test name
Test status
Simulation time 878152680 ps
CPU time 15.05 seconds
Started Feb 09 07:42:38 AM UTC 25
Finished Feb 09 07:42:54 AM UTC 25
Peak memory 207136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2086070440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 12.hmac_smoke.2086070440
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/12.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/12.hmac_wipe_secret.3724267828
Short name T145
Test name
Test status
Simulation time 7468453311 ps
CPU time 107.92 seconds
Started Feb 09 07:42:57 AM UTC 25
Finished Feb 09 07:44:48 AM UTC 25
Peak memory 207256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3724267828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_sec
ret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 12.hmac_wipe_secret.3724267828
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/12.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/13.hmac_alert_test.1336407152
Short name T205
Test name
Test status
Simulation time 14260148 ps
CPU time 0.89 seconds
Started Feb 09 07:43:50 AM UTC 25
Finished Feb 09 07:43:53 AM UTC 25
Peak memory 203996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1336407152 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.1336407152
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/13.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/13.hmac_back_pressure.1269988183
Short name T202
Test name
Test status
Simulation time 98158702 ps
CPU time 7.29 seconds
Started Feb 09 07:43:29 AM UTC 25
Finished Feb 09 07:43:38 AM UTC 25
Peak memory 207140 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269988183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SE
Q=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.1269988183
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/13.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/13.hmac_burst_wr.195665259
Short name T208
Test name
Test status
Simulation time 4059011948 ps
CPU time 28.98 seconds
Started Feb 09 07:43:35 AM UTC 25
Finished Feb 09 07:44:05 AM UTC 25
Peak memory 207284 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195665259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 13.hmac_burst_wr.195665259
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/13.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/13.hmac_datapath_stress.4148585878
Short name T340
Test name
Test status
Simulation time 5448702263 ps
CPU time 894.28 seconds
Started Feb 09 07:43:33 AM UTC 25
Finished Feb 09 07:58:36 AM UTC 25
Peak memory 766252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4148585878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SE
Q=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.4148585878
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/13.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/13.hmac_error.4050080658
Short name T206
Test name
Test status
Simulation time 911492286 ps
CPU time 15.84 seconds
Started Feb 09 07:43:36 AM UTC 25
Finished Feb 09 07:43:53 AM UTC 25
Peak memory 207208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4050080658 -assert nopostproc +UVM_TESTNAME=hmac_base_tes
t +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.4050080658
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/13.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/13.hmac_long_msg.3495211896
Short name T209
Test name
Test status
Simulation time 6370476701 ps
CPU time 53.35 seconds
Started Feb 09 07:43:25 AM UTC 25
Finished Feb 09 07:44:20 AM UTC 25
Peak memory 207476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3495211896 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 13.hmac_long_msg.3495211896
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/13.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/13.hmac_smoke.4068885237
Short name T201
Test name
Test status
Simulation time 464614685 ps
CPU time 8.35 seconds
Started Feb 09 07:43:24 AM UTC 25
Finished Feb 09 07:43:34 AM UTC 25
Peak memory 207276 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4068885237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 13.hmac_smoke.4068885237
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/13.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/13.hmac_stress_all.1440785699
Short name T373
Test name
Test status
Simulation time 16289303343 ps
CPU time 1060.08 seconds
Started Feb 09 07:43:48 AM UTC 25
Finished Feb 09 08:01:40 AM UTC 25
Peak memory 710940 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1440785699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 13.hmac_stress_all.1440785699
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/13.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/13.hmac_wipe_secret.2451656505
Short name T107
Test name
Test status
Simulation time 22426460232 ps
CPU time 32.93 seconds
Started Feb 09 07:43:39 AM UTC 25
Finished Feb 09 07:44:13 AM UTC 25
Peak memory 207260 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2451656505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_sec
ret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 13.hmac_wipe_secret.2451656505
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/13.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/14.hmac_alert_test.570233812
Short name T210
Test name
Test status
Simulation time 38978029 ps
CPU time 0.91 seconds
Started Feb 09 07:44:21 AM UTC 25
Finished Feb 09 07:44:23 AM UTC 25
Peak memory 203992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570233812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.570233812
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/14.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/14.hmac_back_pressure.1451543635
Short name T32
Test name
Test status
Simulation time 1262676242 ps
CPU time 47.97 seconds
Started Feb 09 07:43:53 AM UTC 25
Finished Feb 09 07:44:43 AM UTC 25
Peak memory 207124 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451543635 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SE
Q=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.1451543635
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/14.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/14.hmac_burst_wr.4079679340
Short name T167
Test name
Test status
Simulation time 1780959801 ps
CPU time 49.43 seconds
Started Feb 09 07:44:02 AM UTC 25
Finished Feb 09 07:44:53 AM UTC 25
Peak memory 207204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4079679340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 14.hmac_burst_wr.4079679340
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/14.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/14.hmac_datapath_stress.1333290833
Short name T424
Test name
Test status
Simulation time 5947641215 ps
CPU time 1481.21 seconds
Started Feb 09 07:43:57 AM UTC 25
Finished Feb 09 08:08:54 AM UTC 25
Peak memory 721308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1333290833 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SE
Q=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.1333290833
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/14.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/14.hmac_error.215697809
Short name T226
Test name
Test status
Simulation time 26073792820 ps
CPU time 117.67 seconds
Started Feb 09 07:44:06 AM UTC 25
Finished Feb 09 07:46:06 AM UTC 25
Peak memory 207336 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=215697809 -assert nopostproc +UVM_TESTNAME=hmac_base_test
+UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 14.hmac_error.215697809
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/14.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/14.hmac_long_msg.1684184349
Short name T234
Test name
Test status
Simulation time 6109056830 ps
CPU time 198.48 seconds
Started Feb 09 07:43:53 AM UTC 25
Finished Feb 09 07:47:15 AM UTC 25
Peak memory 207212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1684184349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 14.hmac_long_msg.1684184349
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/14.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/14.hmac_smoke.4177108940
Short name T207
Test name
Test status
Simulation time 421050543 ps
CPU time 7.26 seconds
Started Feb 09 07:43:52 AM UTC 25
Finished Feb 09 07:44:01 AM UTC 25
Peak memory 207196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177108940 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 14.hmac_smoke.4177108940
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/14.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/14.hmac_stress_all.1985944430
Short name T527
Test name
Test status
Simulation time 69235739380 ps
CPU time 4534.13 seconds
Started Feb 09 07:44:18 AM UTC 25
Finished Feb 09 09:00:35 AM UTC 25
Peak memory 866536 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1985944430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 14.hmac_stress_all.1985944430
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/14.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/14.hmac_wipe_secret.771028521
Short name T225
Test name
Test status
Simulation time 4354273402 ps
CPU time 77.45 seconds
Started Feb 09 07:44:14 AM UTC 25
Finished Feb 09 07:45:33 AM UTC 25
Peak memory 207336 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=771028521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secr
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 14.hmac_wipe_secret.771028521
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/14.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/15.hmac_alert_test.1566724140
Short name T214
Test name
Test status
Simulation time 14893220 ps
CPU time 0.87 seconds
Started Feb 09 07:44:44 AM UTC 25
Finished Feb 09 07:44:46 AM UTC 25
Peak memory 203996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1566724140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.1566724140
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/15.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/15.hmac_back_pressure.192682648
Short name T218
Test name
Test status
Simulation time 2542716434 ps
CPU time 22.05 seconds
Started Feb 09 07:44:33 AM UTC 25
Finished Feb 09 07:44:57 AM UTC 25
Peak memory 207248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192682648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ
=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.192682648
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/15.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/15.hmac_burst_wr.3868200735
Short name T216
Test name
Test status
Simulation time 1586133859 ps
CPU time 9.16 seconds
Started Feb 09 07:44:39 AM UTC 25
Finished Feb 09 07:44:49 AM UTC 25
Peak memory 207116 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3868200735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 15.hmac_burst_wr.3868200735
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/15.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/15.hmac_datapath_stress.2117073030
Short name T422
Test name
Test status
Simulation time 77038226106 ps
CPU time 1425.11 seconds
Started Feb 09 07:44:35 AM UTC 25
Finished Feb 09 08:08:36 AM UTC 25
Peak memory 741744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2117073030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SE
Q=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.2117073030
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/15.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/15.hmac_error.1466226099
Short name T212
Test name
Test status
Simulation time 255853580 ps
CPU time 3.77 seconds
Started Feb 09 07:44:39 AM UTC 25
Finished Feb 09 07:44:44 AM UTC 25
Peak memory 207132 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1466226099 -assert nopostproc +UVM_TESTNAME=hmac_base_tes
t +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.1466226099
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/15.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/15.hmac_long_msg.3474201521
Short name T233
Test name
Test status
Simulation time 6447276581 ps
CPU time 113.5 seconds
Started Feb 09 07:44:28 AM UTC 25
Finished Feb 09 07:46:24 AM UTC 25
Peak memory 207272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474201521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 15.hmac_long_msg.3474201521
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/15.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/15.hmac_smoke.3479409699
Short name T213
Test name
Test status
Simulation time 4014496687 ps
CPU time 18.46 seconds
Started Feb 09 07:44:24 AM UTC 25
Finished Feb 09 07:44:44 AM UTC 25
Peak memory 207404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3479409699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 15.hmac_smoke.3479409699
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/15.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/15.hmac_stress_all.5831915
Short name T338
Test name
Test status
Simulation time 702969468545 ps
CPU time 815.21 seconds
Started Feb 09 07:44:44 AM UTC 25
Finished Feb 09 07:58:29 AM UTC 25
Peak memory 215620 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5831915 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 15.hmac_stress_all.5831915
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/15.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/15.hmac_wipe_secret.2409577768
Short name T217
Test name
Test status
Simulation time 91185056 ps
CPU time 7.01 seconds
Started Feb 09 07:44:44 AM UTC 25
Finished Feb 09 07:44:52 AM UTC 25
Peak memory 207196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2409577768 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_sec
ret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 15.hmac_wipe_secret.2409577768
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/15.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/16.hmac_alert_test.4192843061
Short name T221
Test name
Test status
Simulation time 36148309 ps
CPU time 0.89 seconds
Started Feb 09 07:45:16 AM UTC 25
Finished Feb 09 07:45:18 AM UTC 25
Peak memory 203996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4192843061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.4192843061
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/16.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/16.hmac_back_pressure.1786016271
Short name T219
Test name
Test status
Simulation time 903495969 ps
CPU time 17.91 seconds
Started Feb 09 07:44:50 AM UTC 25
Finished Feb 09 07:45:09 AM UTC 25
Peak memory 207196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1786016271 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SE
Q=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.1786016271
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/16.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/16.hmac_burst_wr.340948212
Short name T222
Test name
Test status
Simulation time 1196404118 ps
CPU time 22.87 seconds
Started Feb 09 07:44:54 AM UTC 25
Finished Feb 09 07:45:19 AM UTC 25
Peak memory 207144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=340948212 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 16.hmac_burst_wr.340948212
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/16.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/16.hmac_datapath_stress.1155909602
Short name T328
Test name
Test status
Simulation time 9080191048 ps
CPU time 758.8 seconds
Started Feb 09 07:44:53 AM UTC 25
Finished Feb 09 07:57:40 AM UTC 25
Peak memory 754008 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1155909602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SE
Q=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.1155909602
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/16.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/16.hmac_error.2150894779
Short name T51
Test name
Test status
Simulation time 14526129647 ps
CPU time 108.45 seconds
Started Feb 09 07:44:58 AM UTC 25
Finished Feb 09 07:46:48 AM UTC 25
Peak memory 207264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2150894779 -assert nopostproc +UVM_TESTNAME=hmac_base_tes
t +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.2150894779
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/16.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/16.hmac_long_msg.2371805973
Short name T59
Test name
Test status
Simulation time 6072875764 ps
CPU time 138.14 seconds
Started Feb 09 07:44:49 AM UTC 25
Finished Feb 09 07:47:10 AM UTC 25
Peak memory 207352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2371805973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 16.hmac_long_msg.2371805973
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/16.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/16.hmac_smoke.4231669463
Short name T220
Test name
Test status
Simulation time 2632644352 ps
CPU time 23.48 seconds
Started Feb 09 07:44:47 AM UTC 25
Finished Feb 09 07:45:12 AM UTC 25
Peak memory 215688 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4231669463 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 16.hmac_smoke.4231669463
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/16.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/16.hmac_stress_all.3199253784
Short name T449
Test name
Test status
Simulation time 56991501093 ps
CPU time 1517.99 seconds
Started Feb 09 07:45:13 AM UTC 25
Finished Feb 09 08:10:47 AM UTC 25
Peak memory 522520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3199253784 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 16.hmac_stress_all.3199253784
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/16.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/16.hmac_wipe_secret.2864825477
Short name T53
Test name
Test status
Simulation time 3674608625 ps
CPU time 100.29 seconds
Started Feb 09 07:45:11 AM UTC 25
Finished Feb 09 07:46:53 AM UTC 25
Peak memory 207264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2864825477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_sec
ret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 16.hmac_wipe_secret.2864825477
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/16.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/17.hmac_alert_test.1882462515
Short name T227
Test name
Test status
Simulation time 13011424 ps
CPU time 0.86 seconds
Started Feb 09 07:46:07 AM UTC 25
Finished Feb 09 07:46:09 AM UTC 25
Peak memory 203996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882462515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.1882462515
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/17.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/17.hmac_back_pressure.1061132849
Short name T33
Test name
Test status
Simulation time 1943878605 ps
CPU time 73.11 seconds
Started Feb 09 07:45:25 AM UTC 25
Finished Feb 09 07:46:40 AM UTC 25
Peak memory 223432 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061132849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SE
Q=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.1061132849
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/17.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/17.hmac_burst_wr.12469840
Short name T229
Test name
Test status
Simulation time 2299692304 ps
CPU time 38.36 seconds
Started Feb 09 07:45:32 AM UTC 25
Finished Feb 09 07:46:11 AM UTC 25
Peak memory 207404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12469840 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 17.hmac_burst_wr.12469840
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/17.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/17.hmac_datapath_stress.658551929
Short name T400
Test name
Test status
Simulation time 10584879383 ps
CPU time 1109.9 seconds
Started Feb 09 07:45:27 AM UTC 25
Finished Feb 09 08:04:08 AM UTC 25
Peak memory 749988 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=658551929 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ
=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.658551929
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/17.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/17.hmac_error.2760140634
Short name T228
Test name
Test status
Simulation time 4989158436 ps
CPU time 35.43 seconds
Started Feb 09 07:45:33 AM UTC 25
Finished Feb 09 07:46:10 AM UTC 25
Peak memory 207136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760140634 -assert nopostproc +UVM_TESTNAME=hmac_base_tes
t +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.2760140634
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/17.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/17.hmac_long_msg.917914936
Short name T46
Test name
Test status
Simulation time 8042977391 ps
CPU time 159.78 seconds
Started Feb 09 07:45:20 AM UTC 25
Finished Feb 09 07:48:02 AM UTC 25
Peak memory 207204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=917914936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 17.hmac_long_msg.917914936
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/17.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/17.hmac_smoke.1099339737
Short name T224
Test name
Test status
Simulation time 897455096 ps
CPU time 11.67 seconds
Started Feb 09 07:45:19 AM UTC 25
Finished Feb 09 07:45:32 AM UTC 25
Peak memory 207196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1099339737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 17.hmac_smoke.1099339737
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/17.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/17.hmac_stress_all.2819320142
Short name T279
Test name
Test status
Simulation time 15417066469 ps
CPU time 410.25 seconds
Started Feb 09 07:45:56 AM UTC 25
Finished Feb 09 07:52:51 AM UTC 25
Peak memory 217736 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2819320142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 17.hmac_stress_all.2819320142
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/17.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/17.hmac_wipe_secret.2196323226
Short name T55
Test name
Test status
Simulation time 5770131713 ps
CPU time 81.63 seconds
Started Feb 09 07:45:35 AM UTC 25
Finished Feb 09 07:46:59 AM UTC 25
Peak memory 207204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196323226 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_sec
ret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 17.hmac_wipe_secret.2196323226
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/17.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/18.hmac_alert_test.252293061
Short name T52
Test name
Test status
Simulation time 132289771 ps
CPU time 0.88 seconds
Started Feb 09 07:46:50 AM UTC 25
Finished Feb 09 07:46:52 AM UTC 25
Peak memory 203992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252293061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.252293061
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/18.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/18.hmac_burst_wr.3814776202
Short name T54
Test name
Test status
Simulation time 979472275 ps
CPU time 35.37 seconds
Started Feb 09 07:46:20 AM UTC 25
Finished Feb 09 07:46:57 AM UTC 25
Peak memory 207120 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814776202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 18.hmac_burst_wr.3814776202
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/18.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/18.hmac_datapath_stress.901391580
Short name T301
Test name
Test status
Simulation time 10155808201 ps
CPU time 467.93 seconds
Started Feb 09 07:46:17 AM UTC 25
Finished Feb 09 07:54:11 AM UTC 25
Peak memory 649492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=901391580 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ
=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.901391580
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/18.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/18.hmac_error.2183565347
Short name T237
Test name
Test status
Simulation time 45323696230 ps
CPU time 138.36 seconds
Started Feb 09 07:46:20 AM UTC 25
Finished Feb 09 07:48:41 AM UTC 25
Peak memory 207400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2183565347 -assert nopostproc +UVM_TESTNAME=hmac_base_tes
t +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.2183565347
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/18.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/18.hmac_long_msg.2395923211
Short name T57
Test name
Test status
Simulation time 3621847016 ps
CPU time 48.73 seconds
Started Feb 09 07:46:10 AM UTC 25
Finished Feb 09 07:47:01 AM UTC 25
Peak memory 207412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2395923211 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 18.hmac_long_msg.2395923211
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/18.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/18.hmac_smoke.345563143
Short name T232
Test name
Test status
Simulation time 355731232 ps
CPU time 6.44 seconds
Started Feb 09 07:46:10 AM UTC 25
Finished Feb 09 07:46:19 AM UTC 25
Peak memory 207284 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345563143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 18.hmac_smoke.345563143
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/18.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/18.hmac_stress_all.1663341262
Short name T337
Test name
Test status
Simulation time 28080191258 ps
CPU time 691.32 seconds
Started Feb 09 07:46:42 AM UTC 25
Finished Feb 09 07:58:21 AM UTC 25
Peak memory 452964 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1663341262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 18.hmac_stress_all.1663341262
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/18.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/18.hmac_wipe_secret.2411069166
Short name T240
Test name
Test status
Simulation time 7400665203 ps
CPU time 144.07 seconds
Started Feb 09 07:46:25 AM UTC 25
Finished Feb 09 07:48:52 AM UTC 25
Peak memory 207204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2411069166 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_sec
ret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 18.hmac_wipe_secret.2411069166
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/18.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/19.hmac_alert_test.3837822488
Short name T235
Test name
Test status
Simulation time 99534950 ps
CPU time 0.89 seconds
Started Feb 09 07:47:16 AM UTC 25
Finished Feb 09 07:47:18 AM UTC 25
Peak memory 203996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3837822488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.3837822488
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/19.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/19.hmac_back_pressure.3525808904
Short name T239
Test name
Test status
Simulation time 4588211864 ps
CPU time 106.42 seconds
Started Feb 09 07:46:58 AM UTC 25
Finished Feb 09 07:48:47 AM UTC 25
Peak memory 207212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3525808904 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SE
Q=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.3525808904
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/19.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/19.hmac_burst_wr.1714365214
Short name T47
Test name
Test status
Simulation time 22726987794 ps
CPU time 75.48 seconds
Started Feb 09 07:47:03 AM UTC 25
Finished Feb 09 07:48:20 AM UTC 25
Peak memory 215760 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1714365214 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 19.hmac_burst_wr.1714365214
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/19.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/19.hmac_datapath_stress.3297544159
Short name T305
Test name
Test status
Simulation time 29142421947 ps
CPU time 460.92 seconds
Started Feb 09 07:47:01 AM UTC 25
Finished Feb 09 07:54:47 AM UTC 25
Peak memory 661804 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297544159 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SE
Q=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.3297544159
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/19.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/19.hmac_error.2768219424
Short name T242
Test name
Test status
Simulation time 5381213745 ps
CPU time 108.67 seconds
Started Feb 09 07:47:03 AM UTC 25
Finished Feb 09 07:48:54 AM UTC 25
Peak memory 207260 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2768219424 -assert nopostproc +UVM_TESTNAME=hmac_base_tes
t +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.2768219424
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/19.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/19.hmac_long_msg.3183168925
Short name T248
Test name
Test status
Simulation time 2704479345 ps
CPU time 159.47 seconds
Started Feb 09 07:46:55 AM UTC 25
Finished Feb 09 07:49:37 AM UTC 25
Peak memory 215752 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3183168925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 19.hmac_long_msg.3183168925
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/19.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/19.hmac_smoke.1103215650
Short name T58
Test name
Test status
Simulation time 2470799396 ps
CPU time 14.87 seconds
Started Feb 09 07:46:53 AM UTC 25
Finished Feb 09 07:47:09 AM UTC 25
Peak memory 207200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1103215650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 19.hmac_smoke.1103215650
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/19.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/19.hmac_stress_all.2363808080
Short name T517
Test name
Test status
Simulation time 28177518711 ps
CPU time 2917.96 seconds
Started Feb 09 07:47:11 AM UTC 25
Finished Feb 09 08:36:20 AM UTC 25
Peak memory 801056 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2363808080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 19.hmac_stress_all.2363808080
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/19.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/19.hmac_wipe_secret.1903032662
Short name T42
Test name
Test status
Simulation time 329490931 ps
CPU time 21.97 seconds
Started Feb 09 07:47:11 AM UTC 25
Finished Feb 09 07:47:34 AM UTC 25
Peak memory 207132 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1903032662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_sec
ret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 19.hmac_wipe_secret.1903032662
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/19.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/2.hmac_back_pressure.2200034379
Short name T11
Test name
Test status
Simulation time 1460769712 ps
CPU time 19.88 seconds
Started Feb 09 07:36:29 AM UTC 25
Finished Feb 09 07:36:50 AM UTC 25
Peak memory 207200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2200034379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SE
Q=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.2200034379
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/2.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/2.hmac_burst_wr.810389450
Short name T8
Test name
Test status
Simulation time 1179935020 ps
CPU time 6.54 seconds
Started Feb 09 07:36:32 AM UTC 25
Finished Feb 09 07:36:39 AM UTC 25
Peak memory 207172 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=810389450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 2.hmac_burst_wr.810389450
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/2.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/2.hmac_datapath_stress.438804400
Short name T159
Test name
Test status
Simulation time 10414768433 ps
CPU time 412.05 seconds
Started Feb 09 07:36:30 AM UTC 25
Finished Feb 09 07:43:27 AM UTC 25
Peak memory 487768 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=438804400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ
=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.438804400
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/2.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/2.hmac_sec_cm.3142272622
Short name T76
Test name
Test status
Simulation time 82772469 ps
CPU time 1.63 seconds
Started Feb 09 07:37:02 AM UTC 25
Finished Feb 09 07:37:04 AM UTC 25
Peak memory 235716 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3142272622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.3142272622
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/2.hmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/2.hmac_smoke.2635673844
Short name T9
Test name
Test status
Simulation time 3803369189 ps
CPU time 16.32 seconds
Started Feb 09 07:36:29 AM UTC 25
Finished Feb 09 07:36:47 AM UTC 25
Peak memory 207228 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2635673844 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.hmac_smoke.2635673844
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/2.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/2.hmac_stress_all.1103519065
Short name T515
Test name
Test status
Simulation time 233094086783 ps
CPU time 3255.2 seconds
Started Feb 09 07:36:53 AM UTC 25
Finished Feb 09 08:31:40 AM UTC 25
Peak memory 821672 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1103519065 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 2.hmac_stress_all.1103519065
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/2.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/2.hmac_stress_all_with_rand_reset.1158000826
Short name T36
Test name
Test status
Simulation time 496960012810 ps
CPU time 8509.28 seconds
Started Feb 09 07:36:59 AM UTC 25
Finished Feb 09 10:00:13 AM UTC 25
Peak memory 936236 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158000826 -assert nopostproc
+UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all_with_rand_reset.1158000826
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/2.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/2.hmac_test_hmac256_vectors.1185238003
Short name T176
Test name
Test status
Simulation time 1607641461 ps
CPU time 72.29 seconds
Started Feb 09 07:36:48 AM UTC 25
Finished Feb 09 07:38:02 AM UTC 25
Peak memory 207344 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1185238003 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TE
ST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac256_vectors.1185238003
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/2.hmac_test_hmac256_vectors/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/2.hmac_test_hmac384_vectors.1539401758
Short name T175
Test name
Test status
Simulation time 17947196481 ps
CPU time 72.14 seconds
Started Feb 09 07:36:48 AM UTC 25
Finished Feb 09 07:38:02 AM UTC 25
Peak memory 207352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1539401758 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TE
ST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac384_vectors.1539401758
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/2.hmac_test_hmac384_vectors/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/2.hmac_test_hmac512_vectors.1672222373
Short name T178
Test name
Test status
Simulation time 5027745492 ps
CPU time 96.64 seconds
Started Feb 09 07:36:51 AM UTC 25
Finished Feb 09 07:38:30 AM UTC 25
Peak memory 207284 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672222373 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TE
ST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac512_vectors.1672222373
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/2.hmac_test_hmac512_vectors/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/2.hmac_test_sha256_vectors.706286046
Short name T243
Test name
Test status
Simulation time 91518388880 ps
CPU time 725.11 seconds
Started Feb 09 07:36:41 AM UTC 25
Finished Feb 09 07:48:55 AM UTC 25
Peak memory 207376 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=706286046 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TES
T_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha256_vectors.706286046
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/2.hmac_test_sha256_vectors/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/2.hmac_test_sha384_vectors.3406295055
Short name T482
Test name
Test status
Simulation time 394271939189 ps
CPU time 2244.78 seconds
Started Feb 09 07:36:41 AM UTC 25
Finished Feb 09 08:14:30 AM UTC 25
Peak memory 221260 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3406295055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TE
ST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha384_vectors.3406295055
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/2.hmac_test_sha384_vectors/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/2.hmac_test_sha512_vectors.2656585130
Short name T494
Test name
Test status
Simulation time 171311090755 ps
CPU time 2532.96 seconds
Started Feb 09 07:36:42 AM UTC 25
Finished Feb 09 08:19:23 AM UTC 25
Peak memory 221340 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2656585130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TE
ST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha512_vectors.2656585130
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/2.hmac_test_sha512_vectors/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/20.hmac_alert_test.250503444
Short name T49
Test name
Test status
Simulation time 12567053 ps
CPU time 0.9 seconds
Started Feb 09 07:48:21 AM UTC 25
Finished Feb 09 07:48:23 AM UTC 25
Peak memory 203992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=250503444 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.250503444
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/20.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/20.hmac_back_pressure.3682201218
Short name T64
Test name
Test status
Simulation time 3826696819 ps
CPU time 69.86 seconds
Started Feb 09 07:47:32 AM UTC 25
Finished Feb 09 07:48:44 AM UTC 25
Peak memory 215768 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682201218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SE
Q=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.3682201218
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/20.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/20.hmac_burst_wr.3408922105
Short name T48
Test name
Test status
Simulation time 1924443992 ps
CPU time 34.85 seconds
Started Feb 09 07:47:45 AM UTC 25
Finished Feb 09 07:48:22 AM UTC 25
Peak memory 207208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3408922105 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 20.hmac_burst_wr.3408922105
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/20.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/20.hmac_datapath_stress.1777717269
Short name T445
Test name
Test status
Simulation time 14053355734 ps
CPU time 1353.83 seconds
Started Feb 09 07:47:35 AM UTC 25
Finished Feb 09 08:10:22 AM UTC 25
Peak memory 762156 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1777717269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SE
Q=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.1777717269
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/20.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/20.hmac_error.3576705685
Short name T246
Test name
Test status
Simulation time 48646154032 ps
CPU time 94.48 seconds
Started Feb 09 07:47:45 AM UTC 25
Finished Feb 09 07:49:22 AM UTC 25
Peak memory 207396 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576705685 -assert nopostproc +UVM_TESTNAME=hmac_base_tes
t +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.3576705685
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/20.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/20.hmac_long_msg.2875941706
Short name T266
Test name
Test status
Simulation time 27387638867 ps
CPU time 221.36 seconds
Started Feb 09 07:47:28 AM UTC 25
Finished Feb 09 07:51:13 AM UTC 25
Peak memory 217808 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875941706 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 20.hmac_long_msg.2875941706
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/20.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/20.hmac_smoke.1445980298
Short name T44
Test name
Test status
Simulation time 3797070379 ps
CPU time 20.76 seconds
Started Feb 09 07:47:19 AM UTC 25
Finished Feb 09 07:47:41 AM UTC 25
Peak memory 207260 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445980298 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 20.hmac_smoke.1445980298
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/20.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/20.hmac_stress_all.4042657842
Short name T495
Test name
Test status
Simulation time 33501917208 ps
CPU time 1865.09 seconds
Started Feb 09 07:48:04 AM UTC 25
Finished Feb 09 08:19:28 AM UTC 25
Peak memory 723420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4042657842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 20.hmac_stress_all.4042657842
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/20.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/20.hmac_wipe_secret.4236736692
Short name T238
Test name
Test status
Simulation time 2400337120 ps
CPU time 48.06 seconds
Started Feb 09 07:47:56 AM UTC 25
Finished Feb 09 07:48:46 AM UTC 25
Peak memory 207332 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4236736692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_sec
ret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 20.hmac_wipe_secret.4236736692
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/20.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/21.hmac_alert_test.2641382305
Short name T245
Test name
Test status
Simulation time 17375654 ps
CPU time 0.85 seconds
Started Feb 09 07:48:56 AM UTC 25
Finished Feb 09 07:48:59 AM UTC 25
Peak memory 203780 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2641382305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.2641382305
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/21.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/21.hmac_back_pressure.2614965694
Short name T251
Test name
Test status
Simulation time 1146792494 ps
CPU time 85.12 seconds
Started Feb 09 07:48:26 AM UTC 25
Finished Feb 09 07:49:53 AM UTC 25
Peak memory 207148 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614965694 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SE
Q=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.2614965694
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/21.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/21.hmac_datapath_stress.3009590687
Short name T263
Test name
Test status
Simulation time 1047667630 ps
CPU time 133.72 seconds
Started Feb 09 07:48:42 AM UTC 25
Finished Feb 09 07:50:58 AM UTC 25
Peak memory 667544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3009590687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SE
Q=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.3009590687
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/21.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/21.hmac_error.3251911606
Short name T252
Test name
Test status
Simulation time 8404755942 ps
CPU time 64.93 seconds
Started Feb 09 07:48:48 AM UTC 25
Finished Feb 09 07:49:55 AM UTC 25
Peak memory 207180 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251911606 -assert nopostproc +UVM_TESTNAME=hmac_base_tes
t +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.3251911606
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/21.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/21.hmac_long_msg.369123300
Short name T254
Test name
Test status
Simulation time 2823175427 ps
CPU time 92.85 seconds
Started Feb 09 07:48:24 AM UTC 25
Finished Feb 09 07:49:59 AM UTC 25
Peak memory 207404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=369123300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 21.hmac_long_msg.369123300
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/21.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/21.hmac_smoke.2035727076
Short name T236
Test name
Test status
Simulation time 18278675 ps
CPU time 1.34 seconds
Started Feb 09 07:48:22 AM UTC 25
Finished Feb 09 07:48:25 AM UTC 25
Peak memory 206188 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2035727076 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 21.hmac_smoke.2035727076
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/21.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/21.hmac_stress_all.185689317
Short name T508
Test name
Test status
Simulation time 135413232118 ps
CPU time 2198.86 seconds
Started Feb 09 07:48:53 AM UTC 25
Finished Feb 09 08:25:55 AM UTC 25
Peak memory 778584 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=185689317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 21.hmac_stress_all.185689317
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/21.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/21.hmac_wipe_secret.1479924409
Short name T247
Test name
Test status
Simulation time 9963662881 ps
CPU time 44.2 seconds
Started Feb 09 07:48:48 AM UTC 25
Finished Feb 09 07:49:34 AM UTC 25
Peak memory 207164 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1479924409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_sec
ret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 21.hmac_wipe_secret.1479924409
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/21.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/22.hmac_alert_test.2765349197
Short name T249
Test name
Test status
Simulation time 11155214 ps
CPU time 0.86 seconds
Started Feb 09 07:49:39 AM UTC 25
Finished Feb 09 07:49:41 AM UTC 25
Peak memory 203996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2765349197 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.2765349197
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/22.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/22.hmac_back_pressure.1350359509
Short name T258
Test name
Test status
Simulation time 2701055361 ps
CPU time 79.84 seconds
Started Feb 09 07:49:01 AM UTC 25
Finished Feb 09 07:50:22 AM UTC 25
Peak memory 207336 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1350359509 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SE
Q=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.1350359509
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/22.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/22.hmac_burst_wr.1946210328
Short name T260
Test name
Test status
Simulation time 21484303919 ps
CPU time 75.11 seconds
Started Feb 09 07:49:17 AM UTC 25
Finished Feb 09 07:50:34 AM UTC 25
Peak memory 217744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1946210328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 22.hmac_burst_wr.1946210328
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/22.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/22.hmac_datapath_stress.2063314311
Short name T327
Test name
Test status
Simulation time 8855021766 ps
CPU time 508 seconds
Started Feb 09 07:49:05 AM UTC 25
Finished Feb 09 07:57:38 AM UTC 25
Peak memory 733456 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2063314311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SE
Q=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.2063314311
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/22.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/22.hmac_error.4116531119
Short name T250
Test name
Test status
Simulation time 6614147030 ps
CPU time 21.54 seconds
Started Feb 09 07:49:23 AM UTC 25
Finished Feb 09 07:49:46 AM UTC 25
Peak memory 207136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116531119 -assert nopostproc +UVM_TESTNAME=hmac_base_tes
t +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.4116531119
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/22.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/22.hmac_long_msg.2471801594
Short name T268
Test name
Test status
Simulation time 19344854424 ps
CPU time 143.13 seconds
Started Feb 09 07:49:00 AM UTC 25
Finished Feb 09 07:51:26 AM UTC 25
Peak memory 207212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2471801594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 22.hmac_long_msg.2471801594
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/22.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/22.hmac_smoke.3473155544
Short name T215
Test name
Test status
Simulation time 992361803 ps
CPU time 17.6 seconds
Started Feb 09 07:48:56 AM UTC 25
Finished Feb 09 07:49:16 AM UTC 25
Peak memory 207212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3473155544 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 22.hmac_smoke.3473155544
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/22.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/22.hmac_stress_all.1542000399
Short name T500
Test name
Test status
Simulation time 61086101892 ps
CPU time 1938.52 seconds
Started Feb 09 07:49:36 AM UTC 25
Finished Feb 09 08:22:16 AM UTC 25
Peak memory 719132 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1542000399 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 22.hmac_stress_all.1542000399
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/22.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/22.hmac_wipe_secret.999264374
Short name T265
Test name
Test status
Simulation time 30592929647 ps
CPU time 91.66 seconds
Started Feb 09 07:49:32 AM UTC 25
Finished Feb 09 07:51:06 AM UTC 25
Peak memory 207272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999264374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secr
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 22.hmac_wipe_secret.999264374
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/22.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/23.hmac_alert_test.1969138586
Short name T257
Test name
Test status
Simulation time 22061783 ps
CPU time 0.88 seconds
Started Feb 09 07:50:05 AM UTC 25
Finished Feb 09 07:50:07 AM UTC 25
Peak memory 203996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969138586 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.1969138586
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/23.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/23.hmac_back_pressure.3181922422
Short name T261
Test name
Test status
Simulation time 1566156329 ps
CPU time 43.59 seconds
Started Feb 09 07:49:51 AM UTC 25
Finished Feb 09 07:50:36 AM UTC 25
Peak memory 207144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181922422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SE
Q=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.3181922422
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/23.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/23.hmac_burst_wr.757706425
Short name T168
Test name
Test status
Simulation time 4325112583 ps
CPU time 50.13 seconds
Started Feb 09 07:49:57 AM UTC 25
Finished Feb 09 07:50:49 AM UTC 25
Peak memory 206924 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757706425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 23.hmac_burst_wr.757706425
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/23.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/23.hmac_datapath_stress.1314408720
Short name T292
Test name
Test status
Simulation time 1215483916 ps
CPU time 223.09 seconds
Started Feb 09 07:49:54 AM UTC 25
Finished Feb 09 07:53:40 AM UTC 25
Peak memory 635188 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1314408720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SE
Q=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.1314408720
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/23.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/23.hmac_error.3744294493
Short name T278
Test name
Test status
Simulation time 11801044059 ps
CPU time 164.92 seconds
Started Feb 09 07:49:57 AM UTC 25
Finished Feb 09 07:52:45 AM UTC 25
Peak memory 206932 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744294493 -assert nopostproc +UVM_TESTNAME=hmac_base_tes
t +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.3744294493
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/23.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/23.hmac_long_msg.717344087
Short name T270
Test name
Test status
Simulation time 7006935498 ps
CPU time 121.33 seconds
Started Feb 09 07:49:51 AM UTC 25
Finished Feb 09 07:51:55 AM UTC 25
Peak memory 207472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=717344087 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 23.hmac_long_msg.717344087
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/23.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/23.hmac_smoke.2326502900
Short name T255
Test name
Test status
Simulation time 788886878 ps
CPU time 17.69 seconds
Started Feb 09 07:49:42 AM UTC 25
Finished Feb 09 07:50:01 AM UTC 25
Peak memory 207196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2326502900 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 23.hmac_smoke.2326502900
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/23.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/23.hmac_stress_all.1060115231
Short name T513
Test name
Test status
Simulation time 23760110737 ps
CPU time 2386.66 seconds
Started Feb 09 07:50:05 AM UTC 25
Finished Feb 09 08:30:15 AM UTC 25
Peak memory 735568 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1060115231 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 23.hmac_stress_all.1060115231
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/23.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/23.hmac_wipe_secret.999763484
Short name T269
Test name
Test status
Simulation time 9074157435 ps
CPU time 98.05 seconds
Started Feb 09 07:50:01 AM UTC 25
Finished Feb 09 07:51:41 AM UTC 25
Peak memory 207180 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999763484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secr
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 23.hmac_wipe_secret.999763484
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/23.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/24.hmac_alert_test.838288172
Short name T264
Test name
Test status
Simulation time 70723329 ps
CPU time 0.87 seconds
Started Feb 09 07:51:00 AM UTC 25
Finished Feb 09 07:51:02 AM UTC 25
Peak memory 203992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=838288172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.838288172
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/24.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/24.hmac_back_pressure.2830494094
Short name T275
Test name
Test status
Simulation time 3086677406 ps
CPU time 107.61 seconds
Started Feb 09 07:50:27 AM UTC 25
Finished Feb 09 07:52:17 AM UTC 25
Peak memory 207380 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2830494094 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SE
Q=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.2830494094
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/24.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/24.hmac_burst_wr.2478789146
Short name T271
Test name
Test status
Simulation time 5108101474 ps
CPU time 86.25 seconds
Started Feb 09 07:50:35 AM UTC 25
Finished Feb 09 07:52:03 AM UTC 25
Peak memory 215628 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478789146 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 24.hmac_burst_wr.2478789146
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/24.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/24.hmac_datapath_stress.507735435
Short name T426
Test name
Test status
Simulation time 14279099226 ps
CPU time 1093.37 seconds
Started Feb 09 07:50:34 AM UTC 25
Finished Feb 09 08:08:58 AM UTC 25
Peak memory 774484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=507735435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ
=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.507735435
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/24.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/24.hmac_error.4278816447
Short name T287
Test name
Test status
Simulation time 20540580445 ps
CPU time 164.54 seconds
Started Feb 09 07:50:37 AM UTC 25
Finished Feb 09 07:53:25 AM UTC 25
Peak memory 207336 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278816447 -assert nopostproc +UVM_TESTNAME=hmac_base_tes
t +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.4278816447
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/24.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/24.hmac_long_msg.3449043734
Short name T277
Test name
Test status
Simulation time 10228344998 ps
CPU time 117.04 seconds
Started Feb 09 07:50:24 AM UTC 25
Finished Feb 09 07:52:23 AM UTC 25
Peak memory 207204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3449043734 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 24.hmac_long_msg.3449043734
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/24.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/24.hmac_smoke.1896555681
Short name T259
Test name
Test status
Simulation time 809818108 ps
CPU time 16.6 seconds
Started Feb 09 07:50:08 AM UTC 25
Finished Feb 09 07:50:26 AM UTC 25
Peak memory 207208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1896555681 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 24.hmac_smoke.1896555681
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/24.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/24.hmac_stress_all.3057778796
Short name T505
Test name
Test status
Simulation time 15862889263 ps
CPU time 2036.22 seconds
Started Feb 09 07:50:50 AM UTC 25
Finished Feb 09 08:25:06 AM UTC 25
Peak memory 760216 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3057778796 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 24.hmac_stress_all.3057778796
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/24.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/24.hmac_wipe_secret.12196392
Short name T283
Test name
Test status
Simulation time 16886288000 ps
CPU time 138.35 seconds
Started Feb 09 07:50:39 AM UTC 25
Finished Feb 09 07:53:00 AM UTC 25
Peak memory 207176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12196392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secre
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 24.hmac_wipe_secret.12196392
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/24.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/25.hmac_alert_test.1611406533
Short name T274
Test name
Test status
Simulation time 16272395 ps
CPU time 0.87 seconds
Started Feb 09 07:52:12 AM UTC 25
Finished Feb 09 07:52:14 AM UTC 25
Peak memory 203996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1611406533 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.1611406533
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/25.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/25.hmac_back_pressure.2368365830
Short name T290
Test name
Test status
Simulation time 1564118523 ps
CPU time 134.93 seconds
Started Feb 09 07:51:15 AM UTC 25
Finished Feb 09 07:53:32 AM UTC 25
Peak memory 207280 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2368365830 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SE
Q=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.2368365830
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/25.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/25.hmac_burst_wr.2408521126
Short name T272
Test name
Test status
Simulation time 10613642312 ps
CPU time 42.08 seconds
Started Feb 09 07:51:28 AM UTC 25
Finished Feb 09 07:52:11 AM UTC 25
Peak memory 215612 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408521126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 25.hmac_burst_wr.2408521126
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/25.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/25.hmac_datapath_stress.3195980939
Short name T472
Test name
Test status
Simulation time 23061715490 ps
CPU time 1321.63 seconds
Started Feb 09 07:51:24 AM UTC 25
Finished Feb 09 08:13:38 AM UTC 25
Peak memory 772444 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195980939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SE
Q=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.3195980939
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/25.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/25.hmac_error.561091330
Short name T295
Test name
Test status
Simulation time 26032722389 ps
CPU time 127.13 seconds
Started Feb 09 07:51:42 AM UTC 25
Finished Feb 09 07:53:52 AM UTC 25
Peak memory 207264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=561091330 -assert nopostproc +UVM_TESTNAME=hmac_base_test
+UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 25.hmac_error.561091330
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/25.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/25.hmac_long_msg.3643563050
Short name T294
Test name
Test status
Simulation time 29674925048 ps
CPU time 161.18 seconds
Started Feb 09 07:51:08 AM UTC 25
Finished Feb 09 07:53:52 AM UTC 25
Peak memory 207352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3643563050 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 25.hmac_long_msg.3643563050
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/25.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/25.hmac_smoke.4095608731
Short name T267
Test name
Test status
Simulation time 295010744 ps
CPU time 18.08 seconds
Started Feb 09 07:51:03 AM UTC 25
Finished Feb 09 07:51:22 AM UTC 25
Peak memory 207200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095608731 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 25.hmac_smoke.4095608731
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/25.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/25.hmac_stress_all.154304689
Short name T354
Test name
Test status
Simulation time 37776534414 ps
CPU time 455.04 seconds
Started Feb 09 07:52:04 AM UTC 25
Finished Feb 09 07:59:45 AM UTC 25
Peak memory 207284 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154304689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 25.hmac_stress_all.154304689
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/25.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/25.hmac_wipe_secret.910214023
Short name T273
Test name
Test status
Simulation time 654425698 ps
CPU time 14.98 seconds
Started Feb 09 07:51:56 AM UTC 25
Finished Feb 09 07:52:12 AM UTC 25
Peak memory 207192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=910214023 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secr
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 25.hmac_wipe_secret.910214023
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/25.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/26.hmac_alert_test.2410362558
Short name T282
Test name
Test status
Simulation time 39434387 ps
CPU time 0.8 seconds
Started Feb 09 07:52:58 AM UTC 25
Finished Feb 09 07:53:00 AM UTC 25
Peak memory 203996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2410362558 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.2410362558
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/26.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/26.hmac_back_pressure.897364911
Short name T284
Test name
Test status
Simulation time 810547120 ps
CPU time 48.39 seconds
Started Feb 09 07:52:19 AM UTC 25
Finished Feb 09 07:53:09 AM UTC 25
Peak memory 207276 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=897364911 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ
=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.897364911
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/26.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/26.hmac_burst_wr.695629065
Short name T281
Test name
Test status
Simulation time 1902056623 ps
CPU time 33.17 seconds
Started Feb 09 07:52:24 AM UTC 25
Finished Feb 09 07:52:59 AM UTC 25
Peak memory 207260 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=695629065 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 26.hmac_burst_wr.695629065
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/26.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/26.hmac_datapath_stress.2860436556
Short name T351
Test name
Test status
Simulation time 4942323598 ps
CPU time 431.07 seconds
Started Feb 09 07:52:21 AM UTC 25
Finished Feb 09 07:59:37 AM UTC 25
Peak memory 512412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2860436556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SE
Q=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.2860436556
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/26.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/26.hmac_error.2373822059
Short name T280
Test name
Test status
Simulation time 362555042 ps
CPU time 5.78 seconds
Started Feb 09 07:52:50 AM UTC 25
Finished Feb 09 07:52:57 AM UTC 25
Peak memory 207132 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2373822059 -assert nopostproc +UVM_TESTNAME=hmac_base_tes
t +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.2373822059
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/26.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/26.hmac_long_msg.74349117
Short name T308
Test name
Test status
Simulation time 2935207520 ps
CPU time 165.79 seconds
Started Feb 09 07:52:16 AM UTC 25
Finished Feb 09 07:55:04 AM UTC 25
Peak memory 207208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74349117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 26.hmac_long_msg.74349117
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/26.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/26.hmac_smoke.142904692
Short name T276
Test name
Test status
Simulation time 1069325084 ps
CPU time 5.33 seconds
Started Feb 09 07:52:14 AM UTC 25
Finished Feb 09 07:52:20 AM UTC 25
Peak memory 207140 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=142904692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 26.hmac_smoke.142904692
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/26.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/26.hmac_stress_all.865204083
Short name T470
Test name
Test status
Simulation time 338144069231 ps
CPU time 1215.04 seconds
Started Feb 09 07:52:54 AM UTC 25
Finished Feb 09 08:13:22 AM UTC 25
Peak memory 647448 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865204083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 26.hmac_stress_all.865204083
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/26.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/26.hmac_wipe_secret.1932136194
Short name T306
Test name
Test status
Simulation time 8021749427 ps
CPU time 117.53 seconds
Started Feb 09 07:52:50 AM UTC 25
Finished Feb 09 07:54:50 AM UTC 25
Peak memory 207176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932136194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_sec
ret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 26.hmac_wipe_secret.1932136194
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/26.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/27.hmac_alert_test.1046814164
Short name T289
Test name
Test status
Simulation time 11025478 ps
CPU time 0.85 seconds
Started Feb 09 07:53:27 AM UTC 25
Finished Feb 09 07:53:29 AM UTC 25
Peak memory 203996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1046814164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.1046814164
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/27.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/27.hmac_back_pressure.3182359344
Short name T296
Test name
Test status
Simulation time 732059362 ps
CPU time 54.46 seconds
Started Feb 09 07:53:02 AM UTC 25
Finished Feb 09 07:53:58 AM UTC 25
Peak memory 207136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3182359344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SE
Q=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.3182359344
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/27.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/27.hmac_burst_wr.1072771304
Short name T300
Test name
Test status
Simulation time 9870214071 ps
CPU time 55.76 seconds
Started Feb 09 07:53:12 AM UTC 25
Finished Feb 09 07:54:09 AM UTC 25
Peak memory 207268 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1072771304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 27.hmac_burst_wr.1072771304
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/27.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/27.hmac_datapath_stress.3147586830
Short name T364
Test name
Test status
Simulation time 3588139158 ps
CPU time 448.92 seconds
Started Feb 09 07:53:10 AM UTC 25
Finished Feb 09 08:00:44 AM UTC 25
Peak memory 659720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3147586830 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SE
Q=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.3147586830
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/27.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/27.hmac_error.4076231197
Short name T288
Test name
Test status
Simulation time 96507841 ps
CPU time 8.27 seconds
Started Feb 09 07:53:17 AM UTC 25
Finished Feb 09 07:53:26 AM UTC 25
Peak memory 207072 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076231197 -assert nopostproc +UVM_TESTNAME=hmac_base_tes
t +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.4076231197
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/27.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/27.hmac_long_msg.4146298706
Short name T286
Test name
Test status
Simulation time 213579719 ps
CPU time 12.33 seconds
Started Feb 09 07:53:02 AM UTC 25
Finished Feb 09 07:53:16 AM UTC 25
Peak memory 207340 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4146298706 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 27.hmac_long_msg.4146298706
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/27.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/27.hmac_smoke.2747026737
Short name T285
Test name
Test status
Simulation time 1644010243 ps
CPU time 9.91 seconds
Started Feb 09 07:53:00 AM UTC 25
Finished Feb 09 07:53:11 AM UTC 25
Peak memory 207140 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2747026737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 27.hmac_smoke.2747026737
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/27.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/27.hmac_stress_all.3916869434
Short name T448
Test name
Test status
Simulation time 267776261857 ps
CPU time 1021.78 seconds
Started Feb 09 07:53:26 AM UTC 25
Finished Feb 09 08:10:40 AM UTC 25
Peak memory 223744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3916869434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 27.hmac_stress_all.3916869434
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/27.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/27.hmac_wipe_secret.487445647
Short name T297
Test name
Test status
Simulation time 4960690582 ps
CPU time 35.44 seconds
Started Feb 09 07:53:21 AM UTC 25
Finished Feb 09 07:53:58 AM UTC 25
Peak memory 207256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=487445647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secr
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 27.hmac_wipe_secret.487445647
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/27.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/28.hmac_alert_test.596058773
Short name T298
Test name
Test status
Simulation time 87607516 ps
CPU time 0.81 seconds
Started Feb 09 07:54:00 AM UTC 25
Finished Feb 09 07:54:02 AM UTC 25
Peak memory 203964 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596058773 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.596058773
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/28.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/28.hmac_back_pressure.2055174304
Short name T314
Test name
Test status
Simulation time 1545705925 ps
CPU time 109.27 seconds
Started Feb 09 07:53:35 AM UTC 25
Finished Feb 09 07:55:27 AM UTC 25
Peak memory 207144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2055174304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SE
Q=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.2055174304
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/28.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/28.hmac_burst_wr.549819426
Short name T302
Test name
Test status
Simulation time 3929781962 ps
CPU time 31.55 seconds
Started Feb 09 07:53:46 AM UTC 25
Finished Feb 09 07:54:19 AM UTC 25
Peak memory 207440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=549819426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 28.hmac_burst_wr.549819426
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/28.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/28.hmac_datapath_stress.3262400499
Short name T319
Test name
Test status
Simulation time 2353916465 ps
CPU time 112.9 seconds
Started Feb 09 07:53:42 AM UTC 25
Finished Feb 09 07:55:37 AM UTC 25
Peak memory 459180 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262400499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SE
Q=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.3262400499
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/28.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/28.hmac_error.2655343333
Short name T315
Test name
Test status
Simulation time 19982955188 ps
CPU time 91.52 seconds
Started Feb 09 07:53:54 AM UTC 25
Finished Feb 09 07:55:28 AM UTC 25
Peak memory 207260 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655343333 -assert nopostproc +UVM_TESTNAME=hmac_base_tes
t +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.2655343333
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/28.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/28.hmac_long_msg.344241269
Short name T293
Test name
Test status
Simulation time 452499608 ps
CPU time 9.22 seconds
Started Feb 09 07:53:34 AM UTC 25
Finished Feb 09 07:53:45 AM UTC 25
Peak memory 207140 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=344241269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 28.hmac_long_msg.344241269
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/28.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/28.hmac_smoke.762755013
Short name T291
Test name
Test status
Simulation time 245687626 ps
CPU time 3.51 seconds
Started Feb 09 07:53:30 AM UTC 25
Finished Feb 09 07:53:35 AM UTC 25
Peak memory 207200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=762755013 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 28.hmac_smoke.762755013
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/28.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/28.hmac_stress_all.1824432776
Short name T518
Test name
Test status
Simulation time 128745189232 ps
CPU time 2617.73 seconds
Started Feb 09 07:54:00 AM UTC 25
Finished Feb 09 08:38:04 AM UTC 25
Peak memory 790916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824432776 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 28.hmac_stress_all.1824432776
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/28.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/28.hmac_wipe_secret.983064678
Short name T299
Test name
Test status
Simulation time 1823129033 ps
CPU time 12.71 seconds
Started Feb 09 07:53:54 AM UTC 25
Finished Feb 09 07:54:08 AM UTC 25
Peak memory 207128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=983064678 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secr
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 28.hmac_wipe_secret.983064678
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/28.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/29.hmac_alert_test.3965360909
Short name T307
Test name
Test status
Simulation time 12785132 ps
CPU time 0.84 seconds
Started Feb 09 07:54:49 AM UTC 25
Finished Feb 09 07:54:51 AM UTC 25
Peak memory 203996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965360909 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.3965360909
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/29.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/29.hmac_back_pressure.322134725
Short name T310
Test name
Test status
Simulation time 671916679 ps
CPU time 57.38 seconds
Started Feb 09 07:54:10 AM UTC 25
Finished Feb 09 07:55:09 AM UTC 25
Peak memory 207128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322134725 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ
=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.322134725
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/29.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/29.hmac_burst_wr.2065012389
Short name T304
Test name
Test status
Simulation time 351431248 ps
CPU time 11.1 seconds
Started Feb 09 07:54:13 AM UTC 25
Finished Feb 09 07:54:25 AM UTC 25
Peak memory 207288 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2065012389 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 29.hmac_burst_wr.2065012389
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/29.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/29.hmac_datapath_stress.2975992283
Short name T407
Test name
Test status
Simulation time 12497910800 ps
CPU time 647.36 seconds
Started Feb 09 07:54:10 AM UTC 25
Finished Feb 09 08:05:04 AM UTC 25
Peak memory 727364 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2975992283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SE
Q=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.2975992283
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/29.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/29.hmac_error.2521773354
Short name T311
Test name
Test status
Simulation time 3398070252 ps
CPU time 53.65 seconds
Started Feb 09 07:54:20 AM UTC 25
Finished Feb 09 07:55:15 AM UTC 25
Peak memory 207336 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521773354 -assert nopostproc +UVM_TESTNAME=hmac_base_tes
t +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.2521773354
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/29.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/29.hmac_long_msg.759433299
Short name T316
Test name
Test status
Simulation time 10412595271 ps
CPU time 81.87 seconds
Started Feb 09 07:54:05 AM UTC 25
Finished Feb 09 07:55:29 AM UTC 25
Peak memory 207204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=759433299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 29.hmac_long_msg.759433299
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/29.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/29.hmac_smoke.152958221
Short name T303
Test name
Test status
Simulation time 288808251 ps
CPU time 13.84 seconds
Started Feb 09 07:54:05 AM UTC 25
Finished Feb 09 07:54:21 AM UTC 25
Peak memory 207340 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152958221 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 29.hmac_smoke.152958221
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/29.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/29.hmac_stress_all.2323402094
Short name T520
Test name
Test status
Simulation time 40294336448 ps
CPU time 2864.66 seconds
Started Feb 09 07:54:26 AM UTC 25
Finished Feb 09 08:42:40 AM UTC 25
Peak memory 774568 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323402094 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 29.hmac_stress_all.2323402094
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/29.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/29.hmac_wipe_secret.2015922535
Short name T313
Test name
Test status
Simulation time 2478307599 ps
CPU time 57.55 seconds
Started Feb 09 07:54:22 AM UTC 25
Finished Feb 09 07:55:21 AM UTC 25
Peak memory 207200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2015922535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_sec
ret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 29.hmac_wipe_secret.2015922535
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/29.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/3.hmac_alert_test.2724525450
Short name T73
Test name
Test status
Simulation time 12966474 ps
CPU time 0.91 seconds
Started Feb 09 07:37:38 AM UTC 25
Finished Feb 09 07:37:40 AM UTC 25
Peak memory 203348 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2724525450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.2724525450
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/3.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/3.hmac_back_pressure.3194239792
Short name T30
Test name
Test status
Simulation time 465417929 ps
CPU time 34.87 seconds
Started Feb 09 07:37:08 AM UTC 25
Finished Feb 09 07:37:44 AM UTC 25
Peak memory 207136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3194239792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SE
Q=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.3194239792
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/3.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/3.hmac_burst_wr.648944141
Short name T28
Test name
Test status
Simulation time 196358431 ps
CPU time 7.63 seconds
Started Feb 09 07:37:13 AM UTC 25
Finished Feb 09 07:37:22 AM UTC 25
Peak memory 207308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=648944141 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 3.hmac_burst_wr.648944141
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/3.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/3.hmac_datapath_stress.3042920301
Short name T241
Test name
Test status
Simulation time 68662887913 ps
CPU time 697.03 seconds
Started Feb 09 07:37:09 AM UTC 25
Finished Feb 09 07:48:53 AM UTC 25
Peak memory 694616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3042920301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SE
Q=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.3042920301
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/3.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/3.hmac_error.4288043407
Short name T69
Test name
Test status
Simulation time 33637887766 ps
CPU time 103.87 seconds
Started Feb 09 07:37:13 AM UTC 25
Finished Feb 09 07:38:59 AM UTC 25
Peak memory 207348 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4288043407 -assert nopostproc +UVM_TESTNAME=hmac_base_tes
t +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.4288043407
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/3.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/3.hmac_long_msg.3533778336
Short name T172
Test name
Test status
Simulation time 2432618165 ps
CPU time 125.27 seconds
Started Feb 09 07:37:06 AM UTC 25
Finished Feb 09 07:39:14 AM UTC 25
Peak memory 207204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533778336 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 3.hmac_long_msg.3533778336
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/3.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/3.hmac_smoke.1166007598
Short name T157
Test name
Test status
Simulation time 32827466 ps
CPU time 2.15 seconds
Started Feb 09 07:37:05 AM UTC 25
Finished Feb 09 07:37:08 AM UTC 25
Peak memory 207220 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1166007598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 3.hmac_smoke.1166007598
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/3.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/3.hmac_stress_all.268666062
Short name T97
Test name
Test status
Simulation time 74897310556 ps
CPU time 2206.77 seconds
Started Feb 09 07:37:23 AM UTC 25
Finished Feb 09 08:14:32 AM UTC 25
Peak memory 778516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268666062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 3.hmac_stress_all.268666062
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/3.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/3.hmac_stress_all_with_rand_reset.3547478287
Short name T38
Test name
Test status
Simulation time 369478749388 ps
CPU time 2492.18 seconds
Started Feb 09 07:37:23 AM UTC 25
Finished Feb 09 08:19:22 AM UTC 25
Peak memory 756060 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3547478287 -assert nopostproc
+UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all_with_rand_reset.3547478287
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/3.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/3.hmac_test_hmac256_vectors.1198449286
Short name T177
Test name
Test status
Simulation time 12260568666 ps
CPU time 51.4 seconds
Started Feb 09 07:37:18 AM UTC 25
Finished Feb 09 07:38:11 AM UTC 25
Peak memory 207212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198449286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TE
ST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac256_vectors.1198449286
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/3.hmac_test_hmac256_vectors/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/3.hmac_test_hmac384_vectors.2685575041
Short name T87
Test name
Test status
Simulation time 13077014171 ps
CPU time 132.63 seconds
Started Feb 09 07:37:18 AM UTC 25
Finished Feb 09 07:39:33 AM UTC 25
Peak memory 207412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2685575041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TE
ST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac384_vectors.2685575041
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/3.hmac_test_hmac384_vectors/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/3.hmac_test_hmac512_vectors.2444525542
Short name T173
Test name
Test status
Simulation time 2134010179 ps
CPU time 67.2 seconds
Started Feb 09 07:37:23 AM UTC 25
Finished Feb 09 07:38:32 AM UTC 25
Peak memory 207288 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2444525542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TE
ST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac512_vectors.2444525542
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/3.hmac_test_hmac512_vectors/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/3.hmac_test_sha256_vectors.2731157119
Short name T43
Test name
Test status
Simulation time 41747650808 ps
CPU time 618.68 seconds
Started Feb 09 07:37:15 AM UTC 25
Finished Feb 09 07:47:41 AM UTC 25
Peak memory 207068 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731157119 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TE
ST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha256_vectors.2731157119
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/3.hmac_test_sha256_vectors/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/3.hmac_test_sha384_vectors.3715040820
Short name T497
Test name
Test status
Simulation time 163446794255 ps
CPU time 2516.39 seconds
Started Feb 09 07:37:15 AM UTC 25
Finished Feb 09 08:19:39 AM UTC 25
Peak memory 225556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3715040820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TE
ST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha384_vectors.3715040820
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/3.hmac_test_sha384_vectors/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/3.hmac_test_sha512_vectors.2536074548
Short name T496
Test name
Test status
Simulation time 133861686090 ps
CPU time 2508.18 seconds
Started Feb 09 07:37:16 AM UTC 25
Finished Feb 09 08:19:32 AM UTC 25
Peak memory 215684 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2536074548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TE
ST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha512_vectors.2536074548
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/3.hmac_test_sha512_vectors/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/3.hmac_wipe_secret.306079615
Short name T24
Test name
Test status
Simulation time 1645867443 ps
CPU time 36.08 seconds
Started Feb 09 07:37:15 AM UTC 25
Finished Feb 09 07:37:52 AM UTC 25
Peak memory 207092 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306079615 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secr
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 3.hmac_wipe_secret.306079615
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/3.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/30.hmac_alert_test.122420557
Short name T317
Test name
Test status
Simulation time 29549860 ps
CPU time 0.77 seconds
Started Feb 09 07:55:29 AM UTC 25
Finished Feb 09 07:55:31 AM UTC 25
Peak memory 203992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=122420557 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.122420557
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/30.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/30.hmac_back_pressure.3872749248
Short name T16
Test name
Test status
Simulation time 6450566651 ps
CPU time 91.16 seconds
Started Feb 09 07:55:06 AM UTC 25
Finished Feb 09 07:56:39 AM UTC 25
Peak memory 207208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3872749248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SE
Q=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.3872749248
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/30.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/30.hmac_burst_wr.954139789
Short name T169
Test name
Test status
Simulation time 2409552581 ps
CPU time 37.46 seconds
Started Feb 09 07:55:11 AM UTC 25
Finished Feb 09 07:55:50 AM UTC 25
Peak memory 215824 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=954139789 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 30.hmac_burst_wr.954139789
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/30.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/30.hmac_datapath_stress.293105855
Short name T362
Test name
Test status
Simulation time 6309470713 ps
CPU time 327.66 seconds
Started Feb 09 07:55:07 AM UTC 25
Finished Feb 09 08:00:39 AM UTC 25
Peak memory 500048 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293105855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ
=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.293105855
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/30.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/30.hmac_error.2384963168
Short name T323
Test name
Test status
Simulation time 58516589075 ps
CPU time 112.31 seconds
Started Feb 09 07:55:16 AM UTC 25
Finished Feb 09 07:57:11 AM UTC 25
Peak memory 207340 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2384963168 -assert nopostproc +UVM_TESTNAME=hmac_base_tes
t +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.2384963168
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/30.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/30.hmac_long_msg.111427217
Short name T333
Test name
Test status
Simulation time 127965502152 ps
CPU time 178.38 seconds
Started Feb 09 07:54:52 AM UTC 25
Finished Feb 09 07:57:53 AM UTC 25
Peak memory 207264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=111427217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 30.hmac_long_msg.111427217
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/30.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/30.hmac_smoke.816279840
Short name T309
Test name
Test status
Simulation time 468943144 ps
CPU time 13.21 seconds
Started Feb 09 07:54:52 AM UTC 25
Finished Feb 09 07:55:06 AM UTC 25
Peak memory 207284 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=816279840 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 30.hmac_smoke.816279840
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/30.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/30.hmac_stress_all.3693309720
Short name T509
Test name
Test status
Simulation time 48853898018 ps
CPU time 1821.44 seconds
Started Feb 09 07:55:23 AM UTC 25
Finished Feb 09 08:26:03 AM UTC 25
Peak memory 807396 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693309720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 30.hmac_stress_all.3693309720
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/30.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/30.hmac_wipe_secret.3607781051
Short name T329
Test name
Test status
Simulation time 2374623704 ps
CPU time 137.63 seconds
Started Feb 09 07:55:21 AM UTC 25
Finished Feb 09 07:57:41 AM UTC 25
Peak memory 207248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3607781051 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_sec
ret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 30.hmac_wipe_secret.3607781051
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/30.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/31.hmac_alert_test.3438237001
Short name T322
Test name
Test status
Simulation time 35639153 ps
CPU time 0.85 seconds
Started Feb 09 07:56:59 AM UTC 25
Finished Feb 09 07:57:01 AM UTC 25
Peak memory 203996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3438237001 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.3438237001
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/31.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/31.hmac_back_pressure.3835713339
Short name T320
Test name
Test status
Simulation time 994230752 ps
CPU time 65.2 seconds
Started Feb 09 07:55:32 AM UTC 25
Finished Feb 09 07:56:39 AM UTC 25
Peak memory 207208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3835713339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SE
Q=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.3835713339
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/31.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/31.hmac_burst_wr.2598779455
Short name T321
Test name
Test status
Simulation time 14741475601 ps
CPU time 78.46 seconds
Started Feb 09 07:55:38 AM UTC 25
Finished Feb 09 07:56:58 AM UTC 25
Peak memory 207260 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598779455 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 31.hmac_burst_wr.2598779455
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/31.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/31.hmac_datapath_stress.1747139523
Short name T410
Test name
Test status
Simulation time 3268891002 ps
CPU time 605.83 seconds
Started Feb 09 07:55:33 AM UTC 25
Finished Feb 09 08:05:45 AM UTC 25
Peak memory 709020 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1747139523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SE
Q=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.1747139523
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/31.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/31.hmac_error.1098889673
Short name T326
Test name
Test status
Simulation time 5253136757 ps
CPU time 95.22 seconds
Started Feb 09 07:55:50 AM UTC 25
Finished Feb 09 07:57:28 AM UTC 25
Peak memory 207200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1098889673 -assert nopostproc +UVM_TESTNAME=hmac_base_tes
t +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.1098889673
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/31.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/31.hmac_long_msg.324578864
Short name T331
Test name
Test status
Simulation time 102342777321 ps
CPU time 129.3 seconds
Started Feb 09 07:55:30 AM UTC 25
Finished Feb 09 07:57:42 AM UTC 25
Peak memory 207284 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324578864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 31.hmac_long_msg.324578864
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/31.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/31.hmac_smoke.1545820057
Short name T318
Test name
Test status
Simulation time 31578004 ps
CPU time 1.26 seconds
Started Feb 09 07:55:29 AM UTC 25
Finished Feb 09 07:55:31 AM UTC 25
Peak memory 206480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545820057 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 31.hmac_smoke.1545820057
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/31.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/31.hmac_stress_all.2212166869
Short name T521
Test name
Test status
Simulation time 365107337386 ps
CPU time 2853.97 seconds
Started Feb 09 07:56:42 AM UTC 25
Finished Feb 09 08:44:43 AM UTC 25
Peak memory 790816 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2212166869 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 31.hmac_stress_all.2212166869
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/31.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/31.hmac_wipe_secret.4214840188
Short name T330
Test name
Test status
Simulation time 20211112431 ps
CPU time 59.77 seconds
Started Feb 09 07:56:40 AM UTC 25
Finished Feb 09 07:57:41 AM UTC 25
Peak memory 207204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4214840188 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_sec
ret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 31.hmac_wipe_secret.4214840188
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/31.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/32.hmac_alert_test.1356648344
Short name T332
Test name
Test status
Simulation time 41766864 ps
CPU time 0.76 seconds
Started Feb 09 07:57:46 AM UTC 25
Finished Feb 09 07:57:48 AM UTC 25
Peak memory 203984 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356648344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.1356648344
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/32.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/32.hmac_back_pressure.43784400
Short name T336
Test name
Test status
Simulation time 1476804248 ps
CPU time 49.43 seconds
Started Feb 09 07:57:16 AM UTC 25
Finished Feb 09 07:58:07 AM UTC 25
Peak memory 207200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=43784400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.43784400
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/32.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/32.hmac_burst_wr.692847675
Short name T339
Test name
Test status
Simulation time 3597454234 ps
CPU time 63.45 seconds
Started Feb 09 07:57:28 AM UTC 25
Finished Feb 09 07:58:34 AM UTC 25
Peak memory 207264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=692847675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 32.hmac_burst_wr.692847675
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/32.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/32.hmac_datapath_stress.3194540614
Short name T489
Test name
Test status
Simulation time 25166343615 ps
CPU time 1173.53 seconds
Started Feb 09 07:57:19 AM UTC 25
Finished Feb 09 08:17:04 AM UTC 25
Peak memory 715228 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3194540614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SE
Q=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.3194540614
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/32.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/32.hmac_error.4134635694
Short name T353
Test name
Test status
Simulation time 1637365192 ps
CPU time 116.78 seconds
Started Feb 09 07:57:41 AM UTC 25
Finished Feb 09 07:59:40 AM UTC 25
Peak memory 207276 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4134635694 -assert nopostproc +UVM_TESTNAME=hmac_base_tes
t +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.4134635694
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/32.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/32.hmac_long_msg.4060838895
Short name T325
Test name
Test status
Simulation time 273259481 ps
CPU time 5.36 seconds
Started Feb 09 07:57:12 AM UTC 25
Finished Feb 09 07:57:18 AM UTC 25
Peak memory 207140 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060838895 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 32.hmac_long_msg.4060838895
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/32.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/32.hmac_smoke.2439455643
Short name T324
Test name
Test status
Simulation time 960742362 ps
CPU time 11.14 seconds
Started Feb 09 07:57:02 AM UTC 25
Finished Feb 09 07:57:15 AM UTC 25
Peak memory 207252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2439455643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 32.hmac_smoke.2439455643
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/32.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/32.hmac_stress_all.2863333738
Short name T96
Test name
Test status
Simulation time 105247506505 ps
CPU time 386.14 seconds
Started Feb 09 07:57:46 AM UTC 25
Finished Feb 09 08:04:17 AM UTC 25
Peak memory 207300 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2863333738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 32.hmac_stress_all.2863333738
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/32.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/32.hmac_wipe_secret.4064134749
Short name T355
Test name
Test status
Simulation time 1738010315 ps
CPU time 119.28 seconds
Started Feb 09 07:57:46 AM UTC 25
Finished Feb 09 07:59:47 AM UTC 25
Peak memory 207280 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4064134749 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_sec
ret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 32.hmac_wipe_secret.4064134749
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/32.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/33.hmac_alert_test.1367914975
Short name T341
Test name
Test status
Simulation time 23746981 ps
CPU time 0.87 seconds
Started Feb 09 07:58:35 AM UTC 25
Finished Feb 09 07:58:37 AM UTC 25
Peak memory 203996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367914975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.1367914975
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/33.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/33.hmac_back_pressure.3364200347
Short name T335
Test name
Test status
Simulation time 150557910 ps
CPU time 6.35 seconds
Started Feb 09 07:57:55 AM UTC 25
Finished Feb 09 07:58:02 AM UTC 25
Peak memory 207208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3364200347 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SE
Q=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.3364200347
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/33.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/33.hmac_burst_wr.1742878507
Short name T344
Test name
Test status
Simulation time 8146894594 ps
CPU time 46.6 seconds
Started Feb 09 07:58:03 AM UTC 25
Finished Feb 09 07:58:51 AM UTC 25
Peak memory 215644 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1742878507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 33.hmac_burst_wr.1742878507
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/33.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/33.hmac_datapath_stress.1716183371
Short name T481
Test name
Test status
Simulation time 21804582525 ps
CPU time 975.36 seconds
Started Feb 09 07:58:01 AM UTC 25
Finished Feb 09 08:14:26 AM UTC 25
Peak memory 737556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1716183371 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SE
Q=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.1716183371
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/33.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/33.hmac_error.1680877542
Short name T356
Test name
Test status
Simulation time 38338733444 ps
CPU time 99.01 seconds
Started Feb 09 07:58:08 AM UTC 25
Finished Feb 09 07:59:50 AM UTC 25
Peak memory 207332 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1680877542 -assert nopostproc +UVM_TESTNAME=hmac_base_tes
t +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.1680877542
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/33.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/33.hmac_long_msg.1281312591
Short name T348
Test name
Test status
Simulation time 21660744655 ps
CPU time 99.96 seconds
Started Feb 09 07:57:49 AM UTC 25
Finished Feb 09 07:59:31 AM UTC 25
Peak memory 207272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281312591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 33.hmac_long_msg.1281312591
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/33.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/33.hmac_smoke.4071100697
Short name T334
Test name
Test status
Simulation time 6233412398 ps
CPU time 12.48 seconds
Started Feb 09 07:57:46 AM UTC 25
Finished Feb 09 07:57:59 AM UTC 25
Peak memory 207236 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071100697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 33.hmac_smoke.4071100697
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/33.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/33.hmac_stress_all.1397907453
Short name T415
Test name
Test status
Simulation time 16388957371 ps
CPU time 496.82 seconds
Started Feb 09 07:58:34 AM UTC 25
Finished Feb 09 08:06:57 AM UTC 25
Peak memory 207404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1397907453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 33.hmac_stress_all.1397907453
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/33.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/33.hmac_wipe_secret.3519318664
Short name T343
Test name
Test status
Simulation time 996994010 ps
CPU time 23.11 seconds
Started Feb 09 07:58:25 AM UTC 25
Finished Feb 09 07:58:50 AM UTC 25
Peak memory 207196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3519318664 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_sec
ret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 33.hmac_wipe_secret.3519318664
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/33.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/34.hmac_alert_test.3776360092
Short name T349
Test name
Test status
Simulation time 40927961 ps
CPU time 0.86 seconds
Started Feb 09 07:59:32 AM UTC 25
Finished Feb 09 07:59:34 AM UTC 25
Peak memory 203996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3776360092 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.3776360092
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/34.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/34.hmac_back_pressure.4175733128
Short name T347
Test name
Test status
Simulation time 626519654 ps
CPU time 39.98 seconds
Started Feb 09 07:58:42 AM UTC 25
Finished Feb 09 07:59:24 AM UTC 25
Peak memory 207144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4175733128 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SE
Q=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.4175733128
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/34.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/34.hmac_burst_wr.1621647531
Short name T350
Test name
Test status
Simulation time 652492831 ps
CPU time 43.77 seconds
Started Feb 09 07:58:51 AM UTC 25
Finished Feb 09 07:59:37 AM UTC 25
Peak memory 207124 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1621647531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 34.hmac_burst_wr.1621647531
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/34.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/34.hmac_datapath_stress.2874777861
Short name T370
Test name
Test status
Simulation time 4404078764 ps
CPU time 150.37 seconds
Started Feb 09 07:58:50 AM UTC 25
Finished Feb 09 08:01:23 AM UTC 25
Peak memory 420112 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874777861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SE
Q=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.2874777861
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/34.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/34.hmac_error.1086213857
Short name T368
Test name
Test status
Simulation time 4635118733 ps
CPU time 139.87 seconds
Started Feb 09 07:58:55 AM UTC 25
Finished Feb 09 08:01:18 AM UTC 25
Peak memory 207332 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1086213857 -assert nopostproc +UVM_TESTNAME=hmac_base_tes
t +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.1086213857
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/34.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/34.hmac_long_msg.2590136594
Short name T372
Test name
Test status
Simulation time 13554051596 ps
CPU time 177.5 seconds
Started Feb 09 07:58:39 AM UTC 25
Finished Feb 09 08:01:40 AM UTC 25
Peak memory 207212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2590136594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 34.hmac_long_msg.2590136594
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/34.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/34.hmac_smoke.1412021069
Short name T346
Test name
Test status
Simulation time 543751966 ps
CPU time 15.69 seconds
Started Feb 09 07:58:39 AM UTC 25
Finished Feb 09 07:58:56 AM UTC 25
Peak memory 207200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412021069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 34.hmac_smoke.1412021069
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/34.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/34.hmac_stress_all.1746846721
Short name T50
Test name
Test status
Simulation time 30111017648 ps
CPU time 2714.04 seconds
Started Feb 09 07:59:25 AM UTC 25
Finished Feb 09 08:45:06 AM UTC 25
Peak memory 760288 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1746846721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 34.hmac_stress_all.1746846721
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/34.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/34.hmac_wipe_secret.760392883
Short name T363
Test name
Test status
Simulation time 9887960292 ps
CPU time 101.68 seconds
Started Feb 09 07:58:57 AM UTC 25
Finished Feb 09 08:00:41 AM UTC 25
Peak memory 207260 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=760392883 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secr
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 34.hmac_wipe_secret.760392883
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/34.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/35.hmac_alert_test.2849268221
Short name T358
Test name
Test status
Simulation time 14659216 ps
CPU time 0.86 seconds
Started Feb 09 08:00:14 AM UTC 25
Finished Feb 09 08:00:16 AM UTC 25
Peak memory 203996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849268221 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.2849268221
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/35.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/35.hmac_back_pressure.1511879319
Short name T359
Test name
Test status
Simulation time 1333774372 ps
CPU time 49.72 seconds
Started Feb 09 07:59:39 AM UTC 25
Finished Feb 09 08:00:30 AM UTC 25
Peak memory 207120 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1511879319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SE
Q=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.1511879319
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/35.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/35.hmac_burst_wr.2392022462
Short name T360
Test name
Test status
Simulation time 3856327430 ps
CPU time 48.43 seconds
Started Feb 09 07:59:41 AM UTC 25
Finished Feb 09 08:00:31 AM UTC 25
Peak memory 215696 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2392022462 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 35.hmac_burst_wr.2392022462
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/35.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/35.hmac_datapath_stress.2947523796
Short name T375
Test name
Test status
Simulation time 3257607233 ps
CPU time 132.16 seconds
Started Feb 09 07:59:40 AM UTC 25
Finished Feb 09 08:01:54 AM UTC 25
Peak memory 461188 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2947523796 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SE
Q=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.2947523796
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/35.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/35.hmac_error.3690657403
Short name T357
Test name
Test status
Simulation time 520985574 ps
CPU time 19.99 seconds
Started Feb 09 07:59:49 AM UTC 25
Finished Feb 09 08:00:11 AM UTC 25
Peak memory 207196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3690657403 -assert nopostproc +UVM_TESTNAME=hmac_base_tes
t +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.3690657403
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/35.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/35.hmac_long_msg.849763554
Short name T374
Test name
Test status
Simulation time 9398346335 ps
CPU time 120.99 seconds
Started Feb 09 07:59:39 AM UTC 25
Finished Feb 09 08:01:42 AM UTC 25
Peak memory 217732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=849763554 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 35.hmac_long_msg.849763554
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/35.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/35.hmac_smoke.2292793401
Short name T352
Test name
Test status
Simulation time 559739393 ps
CPU time 2.2 seconds
Started Feb 09 07:59:36 AM UTC 25
Finished Feb 09 07:59:39 AM UTC 25
Peak memory 207272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292793401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 35.hmac_smoke.2292793401
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/35.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/35.hmac_stress_all.1669625013
Short name T531
Test name
Test status
Simulation time 25109706128 ps
CPU time 4938.58 seconds
Started Feb 09 07:59:51 AM UTC 25
Finished Feb 09 09:23:02 AM UTC 25
Peak memory 882980 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1669625013 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 35.hmac_stress_all.1669625013
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/35.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/35.hmac_wipe_secret.1847561479
Short name T381
Test name
Test status
Simulation time 3596875345 ps
CPU time 151.51 seconds
Started Feb 09 07:59:49 AM UTC 25
Finished Feb 09 08:02:24 AM UTC 25
Peak memory 207260 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847561479 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_sec
ret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 35.hmac_wipe_secret.1847561479
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/35.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/36.hmac_alert_test.2733467108
Short name T367
Test name
Test status
Simulation time 15782141 ps
CPU time 0.89 seconds
Started Feb 09 08:01:09 AM UTC 25
Finished Feb 09 08:01:11 AM UTC 25
Peak memory 203996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2733467108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.2733467108
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/36.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/36.hmac_back_pressure.1674065314
Short name T365
Test name
Test status
Simulation time 8515275160 ps
CPU time 30.34 seconds
Started Feb 09 08:00:32 AM UTC 25
Finished Feb 09 08:01:03 AM UTC 25
Peak memory 207204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1674065314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SE
Q=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.1674065314
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/36.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/36.hmac_burst_wr.3430004672
Short name T371
Test name
Test status
Simulation time 803712503 ps
CPU time 51.41 seconds
Started Feb 09 08:00:41 AM UTC 25
Finished Feb 09 08:01:34 AM UTC 25
Peak memory 215644 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430004672 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 36.hmac_burst_wr.3430004672
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/36.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/36.hmac_datapath_stress.2074117881
Short name T421
Test name
Test status
Simulation time 4394524807 ps
CPU time 451.59 seconds
Started Feb 09 08:00:37 AM UTC 25
Finished Feb 09 08:08:13 AM UTC 25
Peak memory 694520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2074117881 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SE
Q=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.2074117881
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/36.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/36.hmac_error.2291006283
Short name T377
Test name
Test status
Simulation time 8501004893 ps
CPU time 84.88 seconds
Started Feb 09 08:00:42 AM UTC 25
Finished Feb 09 08:02:09 AM UTC 25
Peak memory 207200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2291006283 -assert nopostproc +UVM_TESTNAME=hmac_base_tes
t +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.2291006283
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/36.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/36.hmac_long_msg.616590812
Short name T389
Test name
Test status
Simulation time 12901936916 ps
CPU time 177.54 seconds
Started Feb 09 08:00:32 AM UTC 25
Finished Feb 09 08:03:32 AM UTC 25
Peak memory 223604 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=616590812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 36.hmac_long_msg.616590812
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/36.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/36.hmac_smoke.3979996963
Short name T361
Test name
Test status
Simulation time 2725394320 ps
CPU time 17.72 seconds
Started Feb 09 08:00:17 AM UTC 25
Finished Feb 09 08:00:36 AM UTC 25
Peak memory 207340 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3979996963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 36.hmac_smoke.3979996963
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/36.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/36.hmac_stress_all.2869826267
Short name T522
Test name
Test status
Simulation time 505598419412 ps
CPU time 2712.55 seconds
Started Feb 09 08:01:05 AM UTC 25
Finished Feb 09 08:46:44 AM UTC 25
Peak memory 792892 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2869826267 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 36.hmac_stress_all.2869826267
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/36.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/36.hmac_wipe_secret.3990225270
Short name T366
Test name
Test status
Simulation time 587092348 ps
CPU time 21.49 seconds
Started Feb 09 08:00:45 AM UTC 25
Finished Feb 09 08:01:08 AM UTC 25
Peak memory 207132 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3990225270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_sec
ret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 36.hmac_wipe_secret.3990225270
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/36.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/37.hmac_alert_test.983598736
Short name T376
Test name
Test status
Simulation time 16623115 ps
CPU time 0.78 seconds
Started Feb 09 08:01:56 AM UTC 25
Finished Feb 09 08:01:58 AM UTC 25
Peak memory 203992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=983598736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.983598736
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/37.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/37.hmac_back_pressure.153954393
Short name T379
Test name
Test status
Simulation time 1001153123 ps
CPU time 58.65 seconds
Started Feb 09 08:01:22 AM UTC 25
Finished Feb 09 08:02:22 AM UTC 25
Peak memory 207340 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=153954393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ
=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.153954393
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/37.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/37.hmac_burst_wr.523581629
Short name T382
Test name
Test status
Simulation time 4710446682 ps
CPU time 52.41 seconds
Started Feb 09 08:01:34 AM UTC 25
Finished Feb 09 08:02:28 AM UTC 25
Peak memory 207244 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=523581629 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 37.hmac_burst_wr.523581629
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/37.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/37.hmac_datapath_stress.910804328
Short name T443
Test name
Test status
Simulation time 11516943484 ps
CPU time 526.21 seconds
Started Feb 09 08:01:24 AM UTC 25
Finished Feb 09 08:10:16 AM UTC 25
Peak memory 754088 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=910804328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ
=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.910804328
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/37.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/37.hmac_error.1329415378
Short name T388
Test name
Test status
Simulation time 6016685766 ps
CPU time 104.56 seconds
Started Feb 09 08:01:45 AM UTC 25
Finished Feb 09 08:03:32 AM UTC 25
Peak memory 207256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1329415378 -assert nopostproc +UVM_TESTNAME=hmac_base_tes
t +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.1329415378
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/37.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/37.hmac_long_msg.2890973589
Short name T386
Test name
Test status
Simulation time 2072057474 ps
CPU time 114.67 seconds
Started Feb 09 08:01:20 AM UTC 25
Finished Feb 09 08:03:17 AM UTC 25
Peak memory 207288 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2890973589 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 37.hmac_long_msg.2890973589
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/37.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/37.hmac_smoke.4156319736
Short name T369
Test name
Test status
Simulation time 391990736 ps
CPU time 7.87 seconds
Started Feb 09 08:01:12 AM UTC 25
Finished Feb 09 08:01:21 AM UTC 25
Peak memory 207336 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156319736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 37.hmac_smoke.4156319736
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/37.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/37.hmac_stress_all.1746890837
Short name T383
Test name
Test status
Simulation time 33397447803 ps
CPU time 64.73 seconds
Started Feb 09 08:01:45 AM UTC 25
Finished Feb 09 08:02:52 AM UTC 25
Peak memory 207340 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1746890837 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 37.hmac_stress_all.1746890837
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/37.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/37.hmac_wipe_secret.1070179543
Short name T109
Test name
Test status
Simulation time 7813465627 ps
CPU time 113.34 seconds
Started Feb 09 08:01:45 AM UTC 25
Finished Feb 09 08:03:41 AM UTC 25
Peak memory 207264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1070179543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_sec
ret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 37.hmac_wipe_secret.1070179543
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/37.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/38.hmac_alert_test.3221485826
Short name T385
Test name
Test status
Simulation time 11328905 ps
CPU time 0.86 seconds
Started Feb 09 08:03:13 AM UTC 25
Finished Feb 09 08:03:15 AM UTC 25
Peak memory 203996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3221485826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.3221485826
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/38.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/38.hmac_back_pressure.2840929715
Short name T380
Test name
Test status
Simulation time 1064487890 ps
CPU time 12.07 seconds
Started Feb 09 08:02:10 AM UTC 25
Finished Feb 09 08:02:24 AM UTC 25
Peak memory 207200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840929715 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SE
Q=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.2840929715
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/38.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/38.hmac_burst_wr.3602878638
Short name T392
Test name
Test status
Simulation time 8141058211 ps
CPU time 76.1 seconds
Started Feb 09 08:02:24 AM UTC 25
Finished Feb 09 08:03:42 AM UTC 25
Peak memory 215636 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3602878638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 38.hmac_burst_wr.3602878638
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/38.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/38.hmac_datapath_stress.4067102901
Short name T446
Test name
Test status
Simulation time 5074467142 ps
CPU time 477.27 seconds
Started Feb 09 08:02:23 AM UTC 25
Finished Feb 09 08:10:26 AM UTC 25
Peak memory 477584 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4067102901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SE
Q=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.4067102901
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/38.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/38.hmac_error.2364070215
Short name T405
Test name
Test status
Simulation time 123312843790 ps
CPU time 127.69 seconds
Started Feb 09 08:02:26 AM UTC 25
Finished Feb 09 08:04:36 AM UTC 25
Peak memory 207400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364070215 -assert nopostproc +UVM_TESTNAME=hmac_base_tes
t +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.2364070215
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/38.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/38.hmac_long_msg.2251647688
Short name T394
Test name
Test status
Simulation time 27121418869 ps
CPU time 100.66 seconds
Started Feb 09 08:02:10 AM UTC 25
Finished Feb 09 08:03:53 AM UTC 25
Peak memory 207416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2251647688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 38.hmac_long_msg.2251647688
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/38.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/38.hmac_smoke.1352964298
Short name T378
Test name
Test status
Simulation time 349320679 ps
CPU time 9.01 seconds
Started Feb 09 08:01:59 AM UTC 25
Finished Feb 09 08:02:09 AM UTC 25
Peak memory 207196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1352964298 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 38.hmac_smoke.1352964298
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/38.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/38.hmac_stress_all.1503904298
Short name T524
Test name
Test status
Simulation time 409074673364 ps
CPU time 2642.29 seconds
Started Feb 09 08:02:54 AM UTC 25
Finished Feb 09 08:47:23 AM UTC 25
Peak memory 823772 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1503904298 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 38.hmac_stress_all.1503904298
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/38.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/38.hmac_wipe_secret.3655786821
Short name T384
Test name
Test status
Simulation time 2623123950 ps
CPU time 41.08 seconds
Started Feb 09 08:02:29 AM UTC 25
Finished Feb 09 08:03:12 AM UTC 25
Peak memory 207260 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3655786821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_sec
ret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 38.hmac_wipe_secret.3655786821
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/38.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/39.hmac_alert_test.614960564
Short name T393
Test name
Test status
Simulation time 14605192 ps
CPU time 0.8 seconds
Started Feb 09 08:03:43 AM UTC 25
Finished Feb 09 08:03:46 AM UTC 25
Peak memory 203992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614960564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.614960564
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/39.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/39.hmac_back_pressure.549163068
Short name T391
Test name
Test status
Simulation time 431056181 ps
CPU time 7.93 seconds
Started Feb 09 08:03:28 AM UTC 25
Finished Feb 09 08:03:37 AM UTC 25
Peak memory 207108 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=549163068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ
=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.549163068
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/39.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/39.hmac_burst_wr.518657763
Short name T398
Test name
Test status
Simulation time 4848249597 ps
CPU time 24.66 seconds
Started Feb 09 08:03:34 AM UTC 25
Finished Feb 09 08:04:00 AM UTC 25
Peak memory 207244 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518657763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 39.hmac_burst_wr.518657763
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/39.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/39.hmac_datapath_stress.1617545750
Short name T473
Test name
Test status
Simulation time 18072973931 ps
CPU time 616.01 seconds
Started Feb 09 08:03:34 AM UTC 25
Finished Feb 09 08:13:57 AM UTC 25
Peak memory 747852 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1617545750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SE
Q=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.1617545750
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/39.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/39.hmac_error.3545873646
Short name T412
Test name
Test status
Simulation time 25800168635 ps
CPU time 189.81 seconds
Started Feb 09 08:03:37 AM UTC 25
Finished Feb 09 08:06:50 AM UTC 25
Peak memory 207196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545873646 -assert nopostproc +UVM_TESTNAME=hmac_base_tes
t +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.3545873646
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/39.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/39.hmac_long_msg.4206965267
Short name T390
Test name
Test status
Simulation time 699034774 ps
CPU time 16.87 seconds
Started Feb 09 08:03:18 AM UTC 25
Finished Feb 09 08:03:36 AM UTC 25
Peak memory 207220 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206965267 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 39.hmac_long_msg.4206965267
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/39.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/39.hmac_smoke.3153879247
Short name T387
Test name
Test status
Simulation time 913176153 ps
CPU time 10.31 seconds
Started Feb 09 08:03:16 AM UTC 25
Finished Feb 09 08:03:28 AM UTC 25
Peak memory 207196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3153879247 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 39.hmac_smoke.3153879247
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/39.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/39.hmac_stress_all.784440283
Short name T395
Test name
Test status
Simulation time 640438753 ps
CPU time 10.83 seconds
Started Feb 09 08:03:42 AM UTC 25
Finished Feb 09 08:03:55 AM UTC 25
Peak memory 207144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=784440283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 39.hmac_stress_all.784440283
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/39.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/39.hmac_wipe_secret.820038511
Short name T396
Test name
Test status
Simulation time 14006410780 ps
CPU time 16.51 seconds
Started Feb 09 08:03:38 AM UTC 25
Finished Feb 09 08:03:56 AM UTC 25
Peak memory 207312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820038511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secr
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 39.hmac_wipe_secret.820038511
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/39.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/4.hmac_alert_test.2052877422
Short name T74
Test name
Test status
Simulation time 17141980 ps
CPU time 0.9 seconds
Started Feb 09 07:38:26 AM UTC 25
Finished Feb 09 07:38:29 AM UTC 25
Peak memory 203992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2052877422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.2052877422
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/4.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/4.hmac_back_pressure.209143385
Short name T61
Test name
Test status
Simulation time 4142130140 ps
CPU time 60.9 seconds
Started Feb 09 07:37:39 AM UTC 25
Finished Feb 09 07:38:42 AM UTC 25
Peak memory 207204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=209143385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ
=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.209143385
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/4.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/4.hmac_burst_wr.3126430324
Short name T29
Test name
Test status
Simulation time 13661580060 ps
CPU time 59.32 seconds
Started Feb 09 07:37:40 AM UTC 25
Finished Feb 09 07:38:42 AM UTC 25
Peak memory 207264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126430324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 4.hmac_burst_wr.3126430324
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/4.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/4.hmac_datapath_stress.1739289892
Short name T423
Test name
Test status
Simulation time 8491952861 ps
CPU time 1840.14 seconds
Started Feb 09 07:37:39 AM UTC 25
Finished Feb 09 08:08:38 AM UTC 25
Peak memory 813532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739289892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SE
Q=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.1739289892
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/4.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/4.hmac_error.4025099325
Short name T70
Test name
Test status
Simulation time 6442683906 ps
CPU time 95.94 seconds
Started Feb 09 07:37:45 AM UTC 25
Finished Feb 09 07:39:23 AM UTC 25
Peak memory 207412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4025099325 -assert nopostproc +UVM_TESTNAME=hmac_base_tes
t +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.4025099325
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/4.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/4.hmac_long_msg.1502319744
Short name T164
Test name
Test status
Simulation time 40851153825 ps
CPU time 163.12 seconds
Started Feb 09 07:37:38 AM UTC 25
Finished Feb 09 07:40:24 AM UTC 25
Peak memory 215604 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1502319744 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 4.hmac_long_msg.1502319744
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/4.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/4.hmac_sec_cm.3159521633
Short name T78
Test name
Test status
Simulation time 36659777 ps
CPU time 1.2 seconds
Started Feb 09 07:38:24 AM UTC 25
Finished Feb 09 07:38:26 AM UTC 25
Peak memory 235712 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159521633 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.3159521633
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/4.hmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/4.hmac_smoke.3652036992
Short name T34
Test name
Test status
Simulation time 972552525 ps
CPU time 15.54 seconds
Started Feb 09 07:37:38 AM UTC 25
Finished Feb 09 07:37:55 AM UTC 25
Peak memory 207148 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3652036992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 4.hmac_smoke.3652036992
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/4.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/4.hmac_stress_all.2240386030
Short name T161
Test name
Test status
Simulation time 10256726001 ps
CPU time 70.25 seconds
Started Feb 09 07:38:06 AM UTC 25
Finished Feb 09 07:39:18 AM UTC 25
Peak memory 215612 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2240386030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 4.hmac_stress_all.2240386030
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/4.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/4.hmac_stress_all_with_rand_reset.1401102185
Short name T14
Test name
Test status
Simulation time 112308548127 ps
CPU time 896.23 seconds
Started Feb 09 07:38:12 AM UTC 25
Finished Feb 09 07:53:18 AM UTC 25
Peak memory 233972 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401102185 -assert nopostproc
+UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all_with_rand_reset.1401102185
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/4.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/4.hmac_test_hmac256_vectors.472638403
Short name T181
Test name
Test status
Simulation time 51995495841 ps
CPU time 57.13 seconds
Started Feb 09 07:38:04 AM UTC 25
Finished Feb 09 07:39:03 AM UTC 25
Peak memory 207212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=472638403 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TES
T_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac256_vectors.472638403
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/4.hmac_test_hmac256_vectors/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/4.hmac_test_hmac384_vectors.1764718937
Short name T88
Test name
Test status
Simulation time 2298461656 ps
CPU time 91.47 seconds
Started Feb 09 07:38:04 AM UTC 25
Finished Feb 09 07:39:37 AM UTC 25
Peak memory 207284 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1764718937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TE
ST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac384_vectors.1764718937
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/4.hmac_test_hmac384_vectors/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/4.hmac_test_hmac512_vectors.721015890
Short name T184
Test name
Test status
Simulation time 5707251345 ps
CPU time 119.84 seconds
Started Feb 09 07:38:04 AM UTC 25
Finished Feb 09 07:40:06 AM UTC 25
Peak memory 207212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=721015890 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TES
T_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac512_vectors.721015890
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/4.hmac_test_hmac512_vectors/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/4.hmac_test_sha256_vectors.643468840
Short name T256
Test name
Test status
Simulation time 49584682529 ps
CPU time 719.49 seconds
Started Feb 09 07:37:54 AM UTC 25
Finished Feb 09 07:50:02 AM UTC 25
Peak memory 207204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=643468840 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TES
T_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha256_vectors.643468840
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/4.hmac_test_sha256_vectors/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/4.hmac_test_sha384_vectors.3698255391
Short name T499
Test name
Test status
Simulation time 286100232906 ps
CPU time 2626.47 seconds
Started Feb 09 07:37:56 AM UTC 25
Finished Feb 09 08:22:11 AM UTC 25
Peak memory 221260 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3698255391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TE
ST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha384_vectors.3698255391
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/4.hmac_test_sha384_vectors/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/4.hmac_test_sha512_vectors.1446135601
Short name T493
Test name
Test status
Simulation time 161730794006 ps
CPU time 2453.02 seconds
Started Feb 09 07:38:01 AM UTC 25
Finished Feb 09 08:19:21 AM UTC 25
Peak memory 215624 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1446135601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TE
ST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha512_vectors.1446135601
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/4.hmac_test_sha512_vectors/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/4.hmac_wipe_secret.2984002400
Short name T146
Test name
Test status
Simulation time 6999235857 ps
CPU time 78.91 seconds
Started Feb 09 07:37:47 AM UTC 25
Finished Feb 09 07:39:08 AM UTC 25
Peak memory 207348 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2984002400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_sec
ret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 4.hmac_wipe_secret.2984002400
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/4.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/40.hmac_alert_test.2305319700
Short name T402
Test name
Test status
Simulation time 16418845 ps
CPU time 0.82 seconds
Started Feb 09 08:04:13 AM UTC 25
Finished Feb 09 08:04:15 AM UTC 25
Peak memory 203996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2305319700 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.2305319700
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/40.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/40.hmac_back_pressure.2172281641
Short name T17
Test name
Test status
Simulation time 1871424767 ps
CPU time 28.38 seconds
Started Feb 09 08:03:55 AM UTC 25
Finished Feb 09 08:04:25 AM UTC 25
Peak memory 223452 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2172281641 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SE
Q=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.2172281641
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/40.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/40.hmac_burst_wr.862011347
Short name T401
Test name
Test status
Simulation time 855534588 ps
CPU time 12.43 seconds
Started Feb 09 08:03:59 AM UTC 25
Finished Feb 09 08:04:12 AM UTC 25
Peak memory 207196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=862011347 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 40.hmac_burst_wr.862011347
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/40.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/40.hmac_datapath_stress.2542089705
Short name T512
Test name
Test status
Simulation time 47768367496 ps
CPU time 1508.62 seconds
Started Feb 09 08:03:56 AM UTC 25
Finished Feb 09 08:29:20 AM UTC 25
Peak memory 803312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2542089705 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SE
Q=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.2542089705
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/40.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/40.hmac_error.756765248
Short name T403
Test name
Test status
Simulation time 214097721 ps
CPU time 15.97 seconds
Started Feb 09 08:04:02 AM UTC 25
Finished Feb 09 08:04:19 AM UTC 25
Peak memory 207144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=756765248 -assert nopostproc +UVM_TESTNAME=hmac_base_test
+UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 40.hmac_error.756765248
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/40.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/40.hmac_long_msg.2282877434
Short name T399
Test name
Test status
Simulation time 501097831 ps
CPU time 11.71 seconds
Started Feb 09 08:03:54 AM UTC 25
Finished Feb 09 08:04:07 AM UTC 25
Peak memory 207196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2282877434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 40.hmac_long_msg.2282877434
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/40.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/40.hmac_smoke.3750519343
Short name T397
Test name
Test status
Simulation time 2601801681 ps
CPU time 9.83 seconds
Started Feb 09 08:03:47 AM UTC 25
Finished Feb 09 08:03:58 AM UTC 25
Peak memory 207272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750519343 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 40.hmac_smoke.3750519343
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/40.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/40.hmac_stress_all.2988215911
Short name T465
Test name
Test status
Simulation time 8718730293 ps
CPU time 507.84 seconds
Started Feb 09 08:04:11 AM UTC 25
Finished Feb 09 08:12:45 AM UTC 25
Peak memory 672000 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988215911 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 40.hmac_stress_all.2988215911
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/40.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/40.hmac_wipe_secret.2616934460
Short name T110
Test name
Test status
Simulation time 9453911679 ps
CPU time 96.58 seconds
Started Feb 09 08:04:11 AM UTC 25
Finished Feb 09 08:05:50 AM UTC 25
Peak memory 207204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2616934460 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_sec
ret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 40.hmac_wipe_secret.2616934460
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/40.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/41.hmac_alert_test.1433673210
Short name T409
Test name
Test status
Simulation time 14824154 ps
CPU time 0.77 seconds
Started Feb 09 08:05:29 AM UTC 25
Finished Feb 09 08:05:31 AM UTC 25
Peak memory 203996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1433673210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.1433673210
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/41.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/41.hmac_back_pressure.960423434
Short name T408
Test name
Test status
Simulation time 1677616319 ps
CPU time 66.19 seconds
Started Feb 09 08:04:20 AM UTC 25
Finished Feb 09 08:05:28 AM UTC 25
Peak memory 207064 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=960423434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ
=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.960423434
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/41.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/41.hmac_burst_wr.386826150
Short name T406
Test name
Test status
Simulation time 215958307 ps
CPU time 16.12 seconds
Started Feb 09 08:04:29 AM UTC 25
Finished Feb 09 08:04:47 AM UTC 25
Peak memory 207200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=386826150 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 41.hmac_burst_wr.386826150
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/41.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/41.hmac_datapath_stress.157955816
Short name T487
Test name
Test status
Simulation time 5844991461 ps
CPU time 656.22 seconds
Started Feb 09 08:04:26 AM UTC 25
Finished Feb 09 08:15:30 AM UTC 25
Peak memory 723404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157955816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ
=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.157955816
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/41.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/41.hmac_error.3783434290
Short name T419
Test name
Test status
Simulation time 14278515540 ps
CPU time 183.76 seconds
Started Feb 09 08:04:38 AM UTC 25
Finished Feb 09 08:07:45 AM UTC 25
Peak memory 207204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3783434290 -assert nopostproc +UVM_TESTNAME=hmac_base_tes
t +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.3783434290
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/41.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/41.hmac_long_msg.412800714
Short name T413
Test name
Test status
Simulation time 8507309679 ps
CPU time 147.41 seconds
Started Feb 09 08:04:20 AM UTC 25
Finished Feb 09 08:06:50 AM UTC 25
Peak memory 207080 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=412800714 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 41.hmac_long_msg.412800714
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/41.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/41.hmac_smoke.2684144603
Short name T404
Test name
Test status
Simulation time 164411617 ps
CPU time 11.11 seconds
Started Feb 09 08:04:16 AM UTC 25
Finished Feb 09 08:04:29 AM UTC 25
Peak memory 207196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2684144603 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 41.hmac_smoke.2684144603
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/41.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/41.hmac_stress_all.2246099647
Short name T519
Test name
Test status
Simulation time 312610479901 ps
CPU time 2029.1 seconds
Started Feb 09 08:05:07 AM UTC 25
Finished Feb 09 08:39:17 AM UTC 25
Peak memory 756164 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2246099647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 41.hmac_stress_all.2246099647
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/41.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/41.hmac_wipe_secret.2018643552
Short name T414
Test name
Test status
Simulation time 9741729820 ps
CPU time 120.61 seconds
Started Feb 09 08:04:47 AM UTC 25
Finished Feb 09 08:06:50 AM UTC 25
Peak memory 207176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2018643552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_sec
ret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 41.hmac_wipe_secret.2018643552
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/41.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/42.hmac_alert_test.2198818534
Short name T416
Test name
Test status
Simulation time 90665896 ps
CPU time 0.78 seconds
Started Feb 09 08:07:17 AM UTC 25
Finished Feb 09 08:07:19 AM UTC 25
Peak memory 203996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198818534 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.2198818534
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/42.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/42.hmac_back_pressure.2983997936
Short name T418
Test name
Test status
Simulation time 5390550313 ps
CPU time 109.44 seconds
Started Feb 09 08:05:51 AM UTC 25
Finished Feb 09 08:07:43 AM UTC 25
Peak memory 215680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2983997936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SE
Q=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.2983997936
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/42.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/42.hmac_burst_wr.3058309680
Short name T420
Test name
Test status
Simulation time 5890288615 ps
CPU time 61.7 seconds
Started Feb 09 08:06:53 AM UTC 25
Finished Feb 09 08:07:57 AM UTC 25
Peak memory 215672 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3058309680 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 42.hmac_burst_wr.3058309680
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/42.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/42.hmac_datapath_stress.415575518
Short name T503
Test name
Test status
Simulation time 38999830422 ps
CPU time 1066.9 seconds
Started Feb 09 08:05:51 AM UTC 25
Finished Feb 09 08:23:49 AM UTC 25
Peak memory 774420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=415575518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ
=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.415575518
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/42.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/42.hmac_error.977290949
Short name T450
Test name
Test status
Simulation time 16932446436 ps
CPU time 237.7 seconds
Started Feb 09 08:06:53 AM UTC 25
Finished Feb 09 08:10:55 AM UTC 25
Peak memory 207192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=977290949 -assert nopostproc +UVM_TESTNAME=hmac_base_test
+UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 42.hmac_error.977290949
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/42.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/42.hmac_long_msg.2742209747
Short name T429
Test name
Test status
Simulation time 14037599786 ps
CPU time 198.04 seconds
Started Feb 09 08:05:47 AM UTC 25
Finished Feb 09 08:09:08 AM UTC 25
Peak memory 215828 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2742209747 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 42.hmac_long_msg.2742209747
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/42.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/42.hmac_smoke.785161555
Short name T411
Test name
Test status
Simulation time 1155079480 ps
CPU time 17.17 seconds
Started Feb 09 08:05:32 AM UTC 25
Finished Feb 09 08:05:51 AM UTC 25
Peak memory 207140 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=785161555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 42.hmac_smoke.785161555
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/42.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/42.hmac_stress_all.587942332
Short name T523
Test name
Test status
Simulation time 219032021254 ps
CPU time 2371.93 seconds
Started Feb 09 08:07:01 AM UTC 25
Finished Feb 09 08:46:57 AM UTC 25
Peak memory 735508 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=587942332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 42.hmac_stress_all.587942332
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/42.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/42.hmac_wipe_secret.2750894771
Short name T435
Test name
Test status
Simulation time 7952619721 ps
CPU time 159.68 seconds
Started Feb 09 08:06:53 AM UTC 25
Finished Feb 09 08:09:36 AM UTC 25
Peak memory 207204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2750894771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_sec
ret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 42.hmac_wipe_secret.2750894771
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/42.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/43.hmac_alert_test.1008583481
Short name T427
Test name
Test status
Simulation time 23258919 ps
CPU time 0.79 seconds
Started Feb 09 08:08:57 AM UTC 25
Finished Feb 09 08:08:59 AM UTC 25
Peak memory 203996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1008583481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.1008583481
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/43.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/43.hmac_back_pressure.2489408226
Short name T432
Test name
Test status
Simulation time 4020518227 ps
CPU time 99.29 seconds
Started Feb 09 08:07:45 AM UTC 25
Finished Feb 09 08:09:27 AM UTC 25
Peak memory 207208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2489408226 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SE
Q=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.2489408226
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/43.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/43.hmac_burst_wr.4200238836
Short name T170
Test name
Test status
Simulation time 1928088749 ps
CPU time 89.23 seconds
Started Feb 09 08:07:58 AM UTC 25
Finished Feb 09 08:09:29 AM UTC 25
Peak memory 207324 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4200238836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 43.hmac_burst_wr.4200238836
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/43.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/43.hmac_datapath_stress.1646919607
Short name T502
Test name
Test status
Simulation time 17280741768 ps
CPU time 932.37 seconds
Started Feb 09 08:07:47 AM UTC 25
Finished Feb 09 08:23:29 AM UTC 25
Peak memory 745744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1646919607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SE
Q=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.1646919607
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/43.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/43.hmac_error.4021352190
Short name T433
Test name
Test status
Simulation time 14695871157 ps
CPU time 75.67 seconds
Started Feb 09 08:08:15 AM UTC 25
Finished Feb 09 08:09:33 AM UTC 25
Peak memory 207260 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4021352190 -assert nopostproc +UVM_TESTNAME=hmac_base_tes
t +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.4021352190
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/43.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/43.hmac_long_msg.1486323505
Short name T425
Test name
Test status
Simulation time 8837344702 ps
CPU time 86.82 seconds
Started Feb 09 08:07:25 AM UTC 25
Finished Feb 09 08:08:54 AM UTC 25
Peak memory 207284 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1486323505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 43.hmac_long_msg.1486323505
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/43.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/43.hmac_smoke.1556657136
Short name T417
Test name
Test status
Simulation time 170916980 ps
CPU time 2.72 seconds
Started Feb 09 08:07:20 AM UTC 25
Finished Feb 09 08:07:24 AM UTC 25
Peak memory 207136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1556657136 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 43.hmac_smoke.1556657136
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/43.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/43.hmac_stress_all.1231881686
Short name T516
Test name
Test status
Simulation time 612586876969 ps
CPU time 1394.14 seconds
Started Feb 09 08:08:44 AM UTC 25
Finished Feb 09 08:32:13 AM UTC 25
Peak memory 737556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1231881686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 43.hmac_stress_all.1231881686
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/43.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/43.hmac_wipe_secret.2903199789
Short name T428
Test name
Test status
Simulation time 2597140027 ps
CPU time 18.92 seconds
Started Feb 09 08:08:40 AM UTC 25
Finished Feb 09 08:09:00 AM UTC 25
Peak memory 207260 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2903199789 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_sec
ret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 43.hmac_wipe_secret.2903199789
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/43.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/44.hmac_alert_test.3071489794
Short name T434
Test name
Test status
Simulation time 19473329 ps
CPU time 0.81 seconds
Started Feb 09 08:09:31 AM UTC 25
Finished Feb 09 08:09:33 AM UTC 25
Peak memory 203996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3071489794 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.3071489794
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/44.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/44.hmac_back_pressure.3431751737
Short name T440
Test name
Test status
Simulation time 4815013261 ps
CPU time 64.47 seconds
Started Feb 09 08:09:01 AM UTC 25
Finished Feb 09 08:10:07 AM UTC 25
Peak memory 207244 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3431751737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SE
Q=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.3431751737
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/44.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/44.hmac_burst_wr.2428975233
Short name T439
Test name
Test status
Simulation time 3285641822 ps
CPU time 51.37 seconds
Started Feb 09 08:09:10 AM UTC 25
Finished Feb 09 08:10:04 AM UTC 25
Peak memory 207408 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2428975233 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 44.hmac_burst_wr.2428975233
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/44.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/44.hmac_datapath_stress.3013209768
Short name T456
Test name
Test status
Simulation time 922723039 ps
CPU time 160.91 seconds
Started Feb 09 08:09:01 AM UTC 25
Finished Feb 09 08:11:45 AM UTC 25
Peak memory 401752 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3013209768 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SE
Q=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.3013209768
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/44.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/44.hmac_error.921002447
Short name T454
Test name
Test status
Simulation time 6854630334 ps
CPU time 136.68 seconds
Started Feb 09 08:09:13 AM UTC 25
Finished Feb 09 08:11:33 AM UTC 25
Peak memory 207340 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=921002447 -assert nopostproc +UVM_TESTNAME=hmac_base_test
+UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 44.hmac_error.921002447
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/44.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/44.hmac_long_msg.375804691
Short name T430
Test name
Test status
Simulation time 143390279 ps
CPU time 10.38 seconds
Started Feb 09 08:09:01 AM UTC 25
Finished Feb 09 08:09:13 AM UTC 25
Peak memory 207212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=375804691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 44.hmac_long_msg.375804691
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/44.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/44.hmac_smoke.2924490218
Short name T431
Test name
Test status
Simulation time 989958110 ps
CPU time 16.59 seconds
Started Feb 09 08:08:57 AM UTC 25
Finished Feb 09 08:09:15 AM UTC 25
Peak memory 207140 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2924490218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 44.hmac_smoke.2924490218
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/44.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/44.hmac_stress_all.4291728690
Short name T112
Test name
Test status
Simulation time 11688565387 ps
CPU time 685.14 seconds
Started Feb 09 08:09:28 AM UTC 25
Finished Feb 09 08:21:02 AM UTC 25
Peak memory 207472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4291728690 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 44.hmac_stress_all.4291728690
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/44.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/44.hmac_wipe_secret.3400159322
Short name T441
Test name
Test status
Simulation time 5212057865 ps
CPU time 53.88 seconds
Started Feb 09 08:09:16 AM UTC 25
Finished Feb 09 08:10:11 AM UTC 25
Peak memory 207344 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3400159322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_sec
ret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 44.hmac_wipe_secret.3400159322
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/44.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/45.hmac_alert_test.1174084131
Short name T442
Test name
Test status
Simulation time 99798174 ps
CPU time 0.85 seconds
Started Feb 09 08:10:12 AM UTC 25
Finished Feb 09 08:10:14 AM UTC 25
Peak memory 203996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1174084131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.1174084131
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/45.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/45.hmac_back_pressure.3762751281
Short name T436
Test name
Test status
Simulation time 571818739 ps
CPU time 10.14 seconds
Started Feb 09 08:09:38 AM UTC 25
Finished Feb 09 08:09:49 AM UTC 25
Peak memory 207144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3762751281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SE
Q=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.3762751281
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/45.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/45.hmac_burst_wr.1203070760
Short name T438
Test name
Test status
Simulation time 1086567719 ps
CPU time 5.7 seconds
Started Feb 09 08:09:52 AM UTC 25
Finished Feb 09 08:09:59 AM UTC 25
Peak memory 207048 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1203070760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 45.hmac_burst_wr.1203070760
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/45.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/45.hmac_datapath_stress.563984219
Short name T492
Test name
Test status
Simulation time 6081475824 ps
CPU time 461.78 seconds
Started Feb 09 08:09:50 AM UTC 25
Finished Feb 09 08:17:37 AM UTC 25
Peak memory 733604 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=563984219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ
=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.563984219
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/45.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/45.hmac_error.3896141409
Short name T460
Test name
Test status
Simulation time 1995629860 ps
CPU time 129.96 seconds
Started Feb 09 08:10:00 AM UTC 25
Finished Feb 09 08:12:13 AM UTC 25
Peak memory 207196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896141409 -assert nopostproc +UVM_TESTNAME=hmac_base_tes
t +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.3896141409
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/45.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/45.hmac_long_msg.4111868213
Short name T455
Test name
Test status
Simulation time 2168323377 ps
CPU time 118.16 seconds
Started Feb 09 08:09:34 AM UTC 25
Finished Feb 09 08:11:35 AM UTC 25
Peak memory 207284 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4111868213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 45.hmac_long_msg.4111868213
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/45.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/45.hmac_smoke.1520909519
Short name T437
Test name
Test status
Simulation time 548422203 ps
CPU time 15.89 seconds
Started Feb 09 08:09:34 AM UTC 25
Finished Feb 09 08:09:51 AM UTC 25
Peak memory 207276 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520909519 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 45.hmac_smoke.1520909519
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/45.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/45.hmac_stress_all.2612806824
Short name T507
Test name
Test status
Simulation time 132636698246 ps
CPU time 900.08 seconds
Started Feb 09 08:10:09 AM UTC 25
Finished Feb 09 08:25:20 AM UTC 25
Peak memory 215636 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2612806824 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 45.hmac_stress_all.2612806824
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/45.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/45.hmac_wipe_secret.1618287658
Short name T459
Test name
Test status
Simulation time 2001161333 ps
CPU time 123.52 seconds
Started Feb 09 08:10:04 AM UTC 25
Finished Feb 09 08:12:10 AM UTC 25
Peak memory 207216 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1618287658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_sec
ret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 45.hmac_wipe_secret.1618287658
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/45.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/46.hmac_alert_test.3142639946
Short name T451
Test name
Test status
Simulation time 16254928 ps
CPU time 0.87 seconds
Started Feb 09 08:10:56 AM UTC 25
Finished Feb 09 08:10:58 AM UTC 25
Peak memory 203996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3142639946 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.3142639946
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/46.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/46.hmac_back_pressure.1818492047
Short name T458
Test name
Test status
Simulation time 3434211863 ps
CPU time 103.94 seconds
Started Feb 09 08:10:21 AM UTC 25
Finished Feb 09 08:12:07 AM UTC 25
Peak memory 215696 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1818492047 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SE
Q=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.1818492047
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/46.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/46.hmac_burst_wr.3395646976
Short name T447
Test name
Test status
Simulation time 1784446301 ps
CPU time 8.03 seconds
Started Feb 09 08:10:29 AM UTC 25
Finished Feb 09 08:10:38 AM UTC 25
Peak memory 207340 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3395646976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 46.hmac_burst_wr.3395646976
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/46.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/46.hmac_datapath_stress.1617482739
Short name T511
Test name
Test status
Simulation time 4893179694 ps
CPU time 1010.78 seconds
Started Feb 09 08:10:25 AM UTC 25
Finished Feb 09 08:27:27 AM UTC 25
Peak memory 735564 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1617482739 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SE
Q=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.1617482739
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/46.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/46.hmac_error.3272252793
Short name T467
Test name
Test status
Simulation time 14394851934 ps
CPU time 143.88 seconds
Started Feb 09 08:10:39 AM UTC 25
Finished Feb 09 08:13:05 AM UTC 25
Peak memory 207268 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3272252793 -assert nopostproc +UVM_TESTNAME=hmac_base_tes
t +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.3272252793
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/46.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/46.hmac_long_msg.229786074
Short name T463
Test name
Test status
Simulation time 16165431291 ps
CPU time 143.21 seconds
Started Feb 09 08:10:18 AM UTC 25
Finished Feb 09 08:12:43 AM UTC 25
Peak memory 207344 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229786074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 46.hmac_long_msg.229786074
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/46.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/46.hmac_smoke.2960263944
Short name T444
Test name
Test status
Simulation time 498843648 ps
CPU time 3.25 seconds
Started Feb 09 08:10:15 AM UTC 25
Finished Feb 09 08:10:20 AM UTC 25
Peak memory 207272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2960263944 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 46.hmac_smoke.2960263944
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/46.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/46.hmac_stress_all.1263063563
Short name T528
Test name
Test status
Simulation time 79668566366 ps
CPU time 3505.93 seconds
Started Feb 09 08:10:54 AM UTC 25
Finished Feb 09 09:09:56 AM UTC 25
Peak memory 805084 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1263063563 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 46.hmac_stress_all.1263063563
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/46.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/46.hmac_wipe_secret.1197846992
Short name T111
Test name
Test status
Simulation time 45139327238 ps
CPU time 118.11 seconds
Started Feb 09 08:10:46 AM UTC 25
Finished Feb 09 08:12:46 AM UTC 25
Peak memory 207180 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1197846992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_sec
ret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 46.hmac_wipe_secret.1197846992
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/46.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/47.hmac_alert_test.1535574354
Short name T461
Test name
Test status
Simulation time 12152977 ps
CPU time 0.83 seconds
Started Feb 09 08:12:12 AM UTC 25
Finished Feb 09 08:12:14 AM UTC 25
Peak memory 203996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1535574354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.1535574354
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/47.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/47.hmac_back_pressure.532499424
Short name T464
Test name
Test status
Simulation time 3773884418 ps
CPU time 72.91 seconds
Started Feb 09 08:11:28 AM UTC 25
Finished Feb 09 08:12:43 AM UTC 25
Peak memory 207196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=532499424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ
=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.532499424
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/47.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/47.hmac_burst_wr.1652096576
Short name T457
Test name
Test status
Simulation time 4966587411 ps
CPU time 26.98 seconds
Started Feb 09 08:11:37 AM UTC 25
Finished Feb 09 08:12:05 AM UTC 25
Peak memory 207264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1652096576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 47.hmac_burst_wr.1652096576
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/47.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/47.hmac_datapath_stress.2326272119
Short name T490
Test name
Test status
Simulation time 6410221837 ps
CPU time 337.76 seconds
Started Feb 09 08:11:34 AM UTC 25
Finished Feb 09 08:17:16 AM UTC 25
Peak memory 704912 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2326272119 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SE
Q=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.2326272119
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/47.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/47.hmac_error.1410042612
Short name T466
Test name
Test status
Simulation time 42053423490 ps
CPU time 65.72 seconds
Started Feb 09 08:11:46 AM UTC 25
Finished Feb 09 08:12:54 AM UTC 25
Peak memory 207200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410042612 -assert nopostproc +UVM_TESTNAME=hmac_base_tes
t +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.1410042612
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/47.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/47.hmac_long_msg.2714054224
Short name T453
Test name
Test status
Simulation time 716800548 ps
CPU time 12.73 seconds
Started Feb 09 08:11:13 AM UTC 25
Finished Feb 09 08:11:27 AM UTC 25
Peak memory 207192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2714054224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 47.hmac_long_msg.2714054224
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/47.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/47.hmac_smoke.3045626662
Short name T452
Test name
Test status
Simulation time 3148252666 ps
CPU time 12.37 seconds
Started Feb 09 08:10:59 AM UTC 25
Finished Feb 09 08:11:13 AM UTC 25
Peak memory 207200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045626662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 47.hmac_smoke.3045626662
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/47.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/47.hmac_stress_all.3509799138
Short name T529
Test name
Test status
Simulation time 163205342637 ps
CPU time 3469.06 seconds
Started Feb 09 08:12:08 AM UTC 25
Finished Feb 09 09:10:30 AM UTC 25
Peak memory 813212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3509799138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 47.hmac_stress_all.3509799138
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/47.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/47.hmac_wipe_secret.918116131
Short name T480
Test name
Test status
Simulation time 17638227380 ps
CPU time 134.01 seconds
Started Feb 09 08:12:06 AM UTC 25
Finished Feb 09 08:14:23 AM UTC 25
Peak memory 207260 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=918116131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secr
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 47.hmac_wipe_secret.918116131
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/47.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/48.hmac_alert_test.2572512573
Short name T468
Test name
Test status
Simulation time 63191420 ps
CPU time 0.82 seconds
Started Feb 09 08:13:06 AM UTC 25
Finished Feb 09 08:13:08 AM UTC 25
Peak memory 203996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572512573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.2572512573
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/48.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/48.hmac_back_pressure.504762359
Short name T471
Test name
Test status
Simulation time 849434890 ps
CPU time 60.72 seconds
Started Feb 09 08:12:35 AM UTC 25
Finished Feb 09 08:13:38 AM UTC 25
Peak memory 207136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=504762359 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ
=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.504762359
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/48.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/48.hmac_burst_wr.80135640
Short name T476
Test name
Test status
Simulation time 4778897026 ps
CPU time 84.28 seconds
Started Feb 09 08:12:45 AM UTC 25
Finished Feb 09 08:14:12 AM UTC 25
Peak memory 207208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80135640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 48.hmac_burst_wr.80135640
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/48.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/48.hmac_datapath_stress.3650854779
Short name T498
Test name
Test status
Simulation time 2597887585 ps
CPU time 421.56 seconds
Started Feb 09 08:12:45 AM UTC 25
Finished Feb 09 08:19:52 AM UTC 25
Peak memory 532836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3650854779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SE
Q=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.3650854779
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/48.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/48.hmac_error.3380739048
Short name T484
Test name
Test status
Simulation time 2287301649 ps
CPU time 132.37 seconds
Started Feb 09 08:12:49 AM UTC 25
Finished Feb 09 08:15:04 AM UTC 25
Peak memory 206876 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3380739048 -assert nopostproc +UVM_TESTNAME=hmac_base_tes
t +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.3380739048
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/48.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/48.hmac_long_msg.634077872
Short name T483
Test name
Test status
Simulation time 1963290735 ps
CPU time 134.88 seconds
Started Feb 09 08:12:15 AM UTC 25
Finished Feb 09 08:14:32 AM UTC 25
Peak memory 207348 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=634077872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 48.hmac_long_msg.634077872
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/48.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/48.hmac_smoke.3708418174
Short name T462
Test name
Test status
Simulation time 8937579329 ps
CPU time 18.61 seconds
Started Feb 09 08:12:14 AM UTC 25
Finished Feb 09 08:12:34 AM UTC 25
Peak memory 207204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3708418174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 48.hmac_smoke.3708418174
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/48.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/48.hmac_stress_all.2659451401
Short name T526
Test name
Test status
Simulation time 177463415444 ps
CPU time 2642.23 seconds
Started Feb 09 08:12:55 AM UTC 25
Finished Feb 09 08:57:23 AM UTC 25
Peak memory 735508 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2659451401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 48.hmac_stress_all.2659451401
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/48.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/48.hmac_wipe_secret.194573679
Short name T478
Test name
Test status
Simulation time 4523354029 ps
CPU time 88.69 seconds
Started Feb 09 08:12:49 AM UTC 25
Finished Feb 09 08:14:20 AM UTC 25
Peak memory 207104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=194573679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secr
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 48.hmac_wipe_secret.194573679
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/48.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/49.hmac_alert_test.1096917890
Short name T477
Test name
Test status
Simulation time 118348920 ps
CPU time 0.84 seconds
Started Feb 09 08:14:12 AM UTC 25
Finished Feb 09 08:14:14 AM UTC 25
Peak memory 203996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096917890 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.1096917890
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/49.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/49.hmac_back_pressure.3302187006
Short name T486
Test name
Test status
Simulation time 6182814877 ps
CPU time 113.84 seconds
Started Feb 09 08:13:31 AM UTC 25
Finished Feb 09 08:15:27 AM UTC 25
Peak memory 217920 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3302187006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SE
Q=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.3302187006
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/49.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/49.hmac_burst_wr.336052672
Short name T474
Test name
Test status
Simulation time 359987477 ps
CPU time 16.31 seconds
Started Feb 09 08:13:42 AM UTC 25
Finished Feb 09 08:13:59 AM UTC 25
Peak memory 207144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=336052672 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 49.hmac_burst_wr.336052672
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/49.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/49.hmac_datapath_stress.2484251739
Short name T506
Test name
Test status
Simulation time 21555505329 ps
CPU time 686.33 seconds
Started Feb 09 08:13:41 AM UTC 25
Finished Feb 09 08:25:16 AM UTC 25
Peak memory 530764 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2484251739 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SE
Q=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.2484251739
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/49.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/49.hmac_error.3349072271
Short name T491
Test name
Test status
Simulation time 7017530081 ps
CPU time 199.91 seconds
Started Feb 09 08:14:00 AM UTC 25
Finished Feb 09 08:17:23 AM UTC 25
Peak memory 207200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3349072271 -assert nopostproc +UVM_TESTNAME=hmac_base_tes
t +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.3349072271
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/49.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/49.hmac_long_msg.348054582
Short name T475
Test name
Test status
Simulation time 482507656 ps
CPU time 36.1 seconds
Started Feb 09 08:13:23 AM UTC 25
Finished Feb 09 08:14:00 AM UTC 25
Peak memory 207344 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=348054582 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 49.hmac_long_msg.348054582
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/49.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/49.hmac_smoke.322169715
Short name T469
Test name
Test status
Simulation time 170321996 ps
CPU time 10.58 seconds
Started Feb 09 08:13:09 AM UTC 25
Finished Feb 09 08:13:21 AM UTC 25
Peak memory 207176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322169715 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 49.hmac_smoke.322169715
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/49.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/49.hmac_stress_all.2001641260
Short name T488
Test name
Test status
Simulation time 1979952881 ps
CPU time 118.07 seconds
Started Feb 09 08:14:01 AM UTC 25
Finished Feb 09 08:16:02 AM UTC 25
Peak memory 207204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2001641260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 49.hmac_stress_all.2001641260
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/49.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/49.hmac_wipe_secret.3586322569
Short name T479
Test name
Test status
Simulation time 1522234303 ps
CPU time 21.22 seconds
Started Feb 09 08:14:00 AM UTC 25
Finished Feb 09 08:14:23 AM UTC 25
Peak memory 207136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586322569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_sec
ret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 49.hmac_wipe_secret.3586322569
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/49.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/5.hmac_alert_test.4290174269
Short name T180
Test name
Test status
Simulation time 19552704 ps
CPU time 0.87 seconds
Started Feb 09 07:38:57 AM UTC 25
Finished Feb 09 07:38:59 AM UTC 25
Peak memory 203992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4290174269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.4290174269
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/5.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/5.hmac_back_pressure.777552080
Short name T62
Test name
Test status
Simulation time 915136969 ps
CPU time 35.61 seconds
Started Feb 09 07:38:32 AM UTC 25
Finished Feb 09 07:39:09 AM UTC 25
Peak memory 207140 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=777552080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ
=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.777552080
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/5.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/5.hmac_burst_wr.3673005379
Short name T171
Test name
Test status
Simulation time 482504219 ps
CPU time 3.88 seconds
Started Feb 09 07:38:41 AM UTC 25
Finished Feb 09 07:38:46 AM UTC 25
Peak memory 207136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673005379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 5.hmac_burst_wr.3673005379
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/5.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/5.hmac_datapath_stress.2390411849
Short name T345
Test name
Test status
Simulation time 5889162739 ps
CPU time 1206.07 seconds
Started Feb 09 07:38:33 AM UTC 25
Finished Feb 09 07:58:52 AM UTC 25
Peak memory 731496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390411849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SE
Q=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.2390411849
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/5.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/5.hmac_error.1408878699
Short name T75
Test name
Test status
Simulation time 517443369 ps
CPU time 13.7 seconds
Started Feb 09 07:38:42 AM UTC 25
Finished Feb 09 07:38:57 AM UTC 25
Peak memory 207220 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1408878699 -assert nopostproc +UVM_TESTNAME=hmac_base_tes
t +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.1408878699
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/5.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/5.hmac_long_msg.196773349
Short name T194
Test name
Test status
Simulation time 11231679348 ps
CPU time 187.78 seconds
Started Feb 09 07:38:29 AM UTC 25
Finished Feb 09 07:41:41 AM UTC 25
Peak memory 223652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=196773349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 5.hmac_long_msg.196773349
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/5.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/5.hmac_stress_all.3295639339
Short name T66
Test name
Test status
Simulation time 17924969425 ps
CPU time 654.5 seconds
Started Feb 09 07:38:44 AM UTC 25
Finished Feb 09 07:49:46 AM UTC 25
Peak memory 430552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295639339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 5.hmac_stress_all.3295639339
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/5.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/5.hmac_stress_all_with_rand_reset.3555716525
Short name T84
Test name
Test status
Simulation time 253729699083 ps
CPU time 2513.44 seconds
Started Feb 09 07:38:47 AM UTC 25
Finished Feb 09 08:21:05 AM UTC 25
Peak memory 758248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3555716525 -assert nopostproc
+UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all_with_rand_reset.3555716525
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/5.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/5.hmac_wipe_secret.2349539235
Short name T141
Test name
Test status
Simulation time 4800569610 ps
CPU time 113.87 seconds
Started Feb 09 07:38:44 AM UTC 25
Finished Feb 09 07:40:40 AM UTC 25
Peak memory 207208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2349539235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_sec
ret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 5.hmac_wipe_secret.2349539235
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/5.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/6.hmac_alert_test.2457896635
Short name T182
Test name
Test status
Simulation time 42006519 ps
CPU time 0.9 seconds
Started Feb 09 07:39:16 AM UTC 25
Finished Feb 09 07:39:18 AM UTC 25
Peak memory 203992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457896635 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.2457896635
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/6.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/6.hmac_back_pressure.16913914
Short name T63
Test name
Test status
Simulation time 2210557996 ps
CPU time 44.65 seconds
Started Feb 09 07:39:01 AM UTC 25
Finished Feb 09 07:39:47 AM UTC 25
Peak memory 215704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16913914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.16913914
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/6.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/6.hmac_burst_wr.331430258
Short name T165
Test name
Test status
Simulation time 4520987874 ps
CPU time 57.25 seconds
Started Feb 09 07:39:05 AM UTC 25
Finished Feb 09 07:40:04 AM UTC 25
Peak memory 215744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=331430258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 6.hmac_burst_wr.331430258
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/6.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/6.hmac_datapath_stress.3507124775
Short name T160
Test name
Test status
Simulation time 5229809427 ps
CPU time 311.32 seconds
Started Feb 09 07:39:01 AM UTC 25
Finished Feb 09 07:44:17 AM UTC 25
Peak memory 684304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507124775 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SE
Q=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.3507124775
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/6.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/6.hmac_error.3367690913
Short name T204
Test name
Test status
Simulation time 71665070932 ps
CPU time 280.03 seconds
Started Feb 09 07:39:05 AM UTC 25
Finished Feb 09 07:43:49 AM UTC 25
Peak memory 207348 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3367690913 -assert nopostproc +UVM_TESTNAME=hmac_base_tes
t +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.3367690913
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/6.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/6.hmac_long_msg.3509974160
Short name T102
Test name
Test status
Simulation time 41401309475 ps
CPU time 205.51 seconds
Started Feb 09 07:39:01 AM UTC 25
Finished Feb 09 07:42:29 AM UTC 25
Peak memory 215632 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3509974160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 6.hmac_long_msg.3509974160
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/6.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/6.hmac_smoke.2500857279
Short name T158
Test name
Test status
Simulation time 275577466 ps
CPU time 16.52 seconds
Started Feb 09 07:38:58 AM UTC 25
Finished Feb 09 07:39:15 AM UTC 25
Peak memory 207220 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2500857279 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 6.hmac_smoke.2500857279
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/6.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/6.hmac_stress_all.4236026914
Short name T95
Test name
Test status
Simulation time 217593120994 ps
CPU time 804.75 seconds
Started Feb 09 07:39:11 AM UTC 25
Finished Feb 09 07:52:45 AM UTC 25
Peak memory 207284 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4236026914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 6.hmac_stress_all.4236026914
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/6.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/6.hmac_stress_all_with_rand_reset.1792300983
Short name T85
Test name
Test status
Simulation time 388516708097 ps
CPU time 7814.84 seconds
Started Feb 09 07:39:16 AM UTC 25
Finished Feb 09 09:50:47 AM UTC 25
Peak memory 840104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1792300983 -assert nopostproc
+UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all_with_rand_reset.1792300983
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/6.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/6.hmac_wipe_secret.1809229865
Short name T142
Test name
Test status
Simulation time 2179470378 ps
CPU time 142.94 seconds
Started Feb 09 07:39:09 AM UTC 25
Finished Feb 09 07:41:35 AM UTC 25
Peak memory 207264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1809229865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_sec
ret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.hmac_wipe_secret.1809229865
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/6.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/7.hmac_alert_test.3916768661
Short name T90
Test name
Test status
Simulation time 26651664 ps
CPU time 0.9 seconds
Started Feb 09 07:39:38 AM UTC 25
Finished Feb 09 07:39:41 AM UTC 25
Peak memory 203992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3916768661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.3916768661
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/7.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/7.hmac_back_pressure.1303278689
Short name T162
Test name
Test status
Simulation time 1333809487 ps
CPU time 72.34 seconds
Started Feb 09 07:39:19 AM UTC 25
Finished Feb 09 07:40:33 AM UTC 25
Peak memory 207204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1303278689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SE
Q=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.1303278689
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/7.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/7.hmac_burst_wr.611681893
Short name T89
Test name
Test status
Simulation time 1132690921 ps
CPU time 14.71 seconds
Started Feb 09 07:39:25 AM UTC 25
Finished Feb 09 07:39:41 AM UTC 25
Peak memory 207192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=611681893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 7.hmac_burst_wr.611681893
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/7.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/7.hmac_datapath_stress.3489328591
Short name T56
Test name
Test status
Simulation time 2977535261 ps
CPU time 455.55 seconds
Started Feb 09 07:39:19 AM UTC 25
Finished Feb 09 07:47:00 AM UTC 25
Peak memory 655636 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489328591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SE
Q=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.3489328591
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/7.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/7.hmac_error.2637693218
Short name T93
Test name
Test status
Simulation time 25653806974 ps
CPU time 28 seconds
Started Feb 09 07:39:28 AM UTC 25
Finished Feb 09 07:39:57 AM UTC 25
Peak memory 207412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2637693218 -assert nopostproc +UVM_TESTNAME=hmac_base_tes
t +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.2637693218
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/7.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/7.hmac_long_msg.2257419996
Short name T183
Test name
Test status
Simulation time 1198586602 ps
CPU time 8.19 seconds
Started Feb 09 07:39:18 AM UTC 25
Finished Feb 09 07:39:27 AM UTC 25
Peak memory 207136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2257419996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 7.hmac_long_msg.2257419996
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/7.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/7.hmac_smoke.2914533194
Short name T86
Test name
Test status
Simulation time 830875044 ps
CPU time 11.4 seconds
Started Feb 09 07:39:16 AM UTC 25
Finished Feb 09 07:39:29 AM UTC 25
Peak memory 207284 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2914533194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 7.hmac_smoke.2914533194
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/7.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/7.hmac_stress_all.3726634895
Short name T530
Test name
Test status
Simulation time 115596790886 ps
CPU time 5630.96 seconds
Started Feb 09 07:39:29 AM UTC 25
Finished Feb 09 09:14:16 AM UTC 25
Peak memory 856300 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3726634895 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 7.hmac_stress_all.3726634895
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/7.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/7.hmac_stress_all_with_rand_reset.2920904819
Short name T37
Test name
Test status
Simulation time 81355977487 ps
CPU time 2252.41 seconds
Started Feb 09 07:39:34 AM UTC 25
Finished Feb 09 08:17:30 AM UTC 25
Peak memory 721304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2920904819 -assert nopostproc
+UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all_with_rand_reset.2920904819
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/7.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/7.hmac_wipe_secret.1292429087
Short name T92
Test name
Test status
Simulation time 551338547 ps
CPU time 20.79 seconds
Started Feb 09 07:39:29 AM UTC 25
Finished Feb 09 07:39:52 AM UTC 25
Peak memory 207212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1292429087 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_sec
ret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 7.hmac_wipe_secret.1292429087
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/7.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/8.hmac_alert_test.603027198
Short name T186
Test name
Test status
Simulation time 13622183 ps
CPU time 0.89 seconds
Started Feb 09 07:40:26 AM UTC 25
Finished Feb 09 07:40:28 AM UTC 25
Peak memory 204048 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=603027198 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.603027198
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/8.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/8.hmac_burst_wr.3072387409
Short name T39
Test name
Test status
Simulation time 5732032294 ps
CPU time 51.62 seconds
Started Feb 09 07:39:52 AM UTC 25
Finished Feb 09 07:40:46 AM UTC 25
Peak memory 207200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3072387409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 8.hmac_burst_wr.3072387409
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/8.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/8.hmac_datapath_stress.2941948447
Short name T342
Test name
Test status
Simulation time 5389896750 ps
CPU time 1116.66 seconds
Started Feb 09 07:39:50 AM UTC 25
Finished Feb 09 07:58:38 AM UTC 25
Peak memory 786724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2941948447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SE
Q=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.2941948447
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/8.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/8.hmac_error.2763491169
Short name T105
Test name
Test status
Simulation time 11379873840 ps
CPU time 167.09 seconds
Started Feb 09 07:39:58 AM UTC 25
Finished Feb 09 07:42:48 AM UTC 25
Peak memory 207208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2763491169 -assert nopostproc +UVM_TESTNAME=hmac_base_tes
t +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.2763491169
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/8.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/8.hmac_long_msg.1596724400
Short name T104
Test name
Test status
Simulation time 38959288455 ps
CPU time 173.76 seconds
Started Feb 09 07:39:42 AM UTC 25
Finished Feb 09 07:42:38 AM UTC 25
Peak memory 215632 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596724400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 8.hmac_long_msg.1596724400
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/8.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/8.hmac_smoke.1401203627
Short name T91
Test name
Test status
Simulation time 331936379 ps
CPU time 6.22 seconds
Started Feb 09 07:39:42 AM UTC 25
Finished Feb 09 07:39:49 AM UTC 25
Peak memory 207196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401203627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 8.hmac_smoke.1401203627
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/8.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/8.hmac_stress_all.1097853708
Short name T82
Test name
Test status
Simulation time 18853553675 ps
CPU time 253.49 seconds
Started Feb 09 07:40:08 AM UTC 25
Finished Feb 09 07:44:26 AM UTC 25
Peak memory 209320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097853708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 8.hmac_stress_all.1097853708
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/8.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/8.hmac_wipe_secret.525371023
Short name T98
Test name
Test status
Simulation time 27039188287 ps
CPU time 107.22 seconds
Started Feb 09 07:40:05 AM UTC 25
Finished Feb 09 07:41:54 AM UTC 25
Peak memory 207200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=525371023 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secr
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 8.hmac_wipe_secret.525371023
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/8.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/9.hmac_alert_test.2570087904
Short name T189
Test name
Test status
Simulation time 24414082 ps
CPU time 0.85 seconds
Started Feb 09 07:41:03 AM UTC 25
Finished Feb 09 07:41:05 AM UTC 25
Peak memory 203992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2570087904 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.2570087904
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/9.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/9.hmac_back_pressure.2867680842
Short name T188
Test name
Test status
Simulation time 809892915 ps
CPU time 14.93 seconds
Started Feb 09 07:40:39 AM UTC 25
Finished Feb 09 07:40:56 AM UTC 25
Peak memory 207220 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867680842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SE
Q=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.2867680842
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/9.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/9.hmac_burst_wr.1756503138
Short name T40
Test name
Test status
Simulation time 274265383 ps
CPU time 16.9 seconds
Started Feb 09 07:40:46 AM UTC 25
Finished Feb 09 07:41:04 AM UTC 25
Peak memory 207208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1756503138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 9.hmac_burst_wr.1756503138
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/9.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/9.hmac_datapath_stress.4281718522
Short name T230
Test name
Test status
Simulation time 3893307674 ps
CPU time 329.9 seconds
Started Feb 09 07:40:41 AM UTC 25
Finished Feb 09 07:46:15 AM UTC 25
Peak memory 688600 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281718522 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SE
Q=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.4281718522
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/9.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/9.hmac_error.3056102947
Short name T197
Test name
Test status
Simulation time 2268079570 ps
CPU time 123.83 seconds
Started Feb 09 07:40:55 AM UTC 25
Finished Feb 09 07:43:01 AM UTC 25
Peak memory 207408 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056102947 -assert nopostproc +UVM_TESTNAME=hmac_base_tes
t +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.3056102947
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/9.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/9.hmac_long_msg.3363035807
Short name T192
Test name
Test status
Simulation time 681115167 ps
CPU time 44.96 seconds
Started Feb 09 07:40:34 AM UTC 25
Finished Feb 09 07:41:21 AM UTC 25
Peak memory 207280 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3363035807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 9.hmac_long_msg.3363035807
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/9.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/9.hmac_smoke.2664606501
Short name T187
Test name
Test status
Simulation time 250654287 ps
CPU time 7.55 seconds
Started Feb 09 07:40:30 AM UTC 25
Finished Feb 09 07:40:38 AM UTC 25
Peak memory 207144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664606501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 9.hmac_smoke.2664606501
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/9.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/9.hmac_stress_all.1550765393
Short name T45
Test name
Test status
Simulation time 18897024665 ps
CPU time 410.64 seconds
Started Feb 09 07:40:58 AM UTC 25
Finished Feb 09 07:47:54 AM UTC 25
Peak memory 207208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1550765393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 9.hmac_stress_all.1550765393
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/9.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/9.hmac_stress_all_with_rand_reset.495748101
Short name T83
Test name
Test status
Simulation time 137885445080 ps
CPU time 771.78 seconds
Started Feb 09 07:41:01 AM UTC 25
Finished Feb 09 07:54:02 AM UTC 25
Peak memory 745880 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/src/low
risc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=495748101 -assert nopostproc +
UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all_with_rand_reset.495748101
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/9.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default/9.hmac_wipe_secret.1737899884
Short name T191
Test name
Test status
Simulation time 1534705342 ps
CPU time 19.42 seconds
Started Feb 09 07:40:57 AM UTC 25
Finished Feb 09 07:41:17 AM UTC 25
Peak memory 207140 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl
i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1737899884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_sec
ret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/hmac-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 9.hmac_wipe_secret.1737899884
Directory /workspaces/repo/scratch/os_regression/hmac-sim-vcs/9.hmac_wipe_secret/latest
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