Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
89.41 95.76 94.06 100.00 73.68 91.67 99.49 71.18


Total test records in report: 604
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T516 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.339996327 May 16 02:27:02 PM PDT 24 May 16 02:27:23 PM PDT 24 2338179309 ps
T517 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.3236146852 May 16 02:27:24 PM PDT 24 May 16 02:27:29 PM PDT 24 91558699 ps
T518 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.711081008 May 16 02:27:25 PM PDT 24 May 16 02:27:32 PM PDT 24 76488527 ps
T54 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.3624130452 May 16 02:27:33 PM PDT 24 May 16 02:27:42 PM PDT 24 885244172 ps
T519 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.2327870399 May 16 02:27:13 PM PDT 24 May 16 02:27:18 PM PDT 24 37407881 ps
T520 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.1135746463 May 16 02:27:13 PM PDT 24 May 16 02:27:19 PM PDT 24 36100314 ps
T521 /workspace/coverage/cover_reg_top/21.hmac_intr_test.3607090893 May 16 02:27:42 PM PDT 24 May 16 02:27:48 PM PDT 24 19303888 ps
T522 /workspace/coverage/cover_reg_top/3.hmac_intr_test.62312872 May 16 02:27:05 PM PDT 24 May 16 02:27:10 PM PDT 24 43341650 ps
T99 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.145057791 May 16 02:27:25 PM PDT 24 May 16 02:27:30 PM PDT 24 63324156 ps
T523 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.1016446216 May 16 02:27:31 PM PDT 24 May 16 02:27:39 PM PDT 24 183754677 ps
T524 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.1916395000 May 16 02:27:13 PM PDT 24 May 16 02:27:18 PM PDT 24 115535151 ps
T525 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.1882253073 May 16 02:27:04 PM PDT 24 May 16 02:27:12 PM PDT 24 3641490733 ps
T526 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.4218707621 May 16 02:27:04 PM PDT 24 May 16 02:27:09 PM PDT 24 22190758 ps
T527 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.672831089 May 16 02:27:32 PM PDT 24 May 16 02:27:40 PM PDT 24 40727343 ps
T528 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.1844044556 May 16 02:27:33 PM PDT 24 May 16 02:27:43 PM PDT 24 758820289 ps
T100 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.317288852 May 16 02:27:07 PM PDT 24 May 16 02:27:21 PM PDT 24 797966466 ps
T529 /workspace/coverage/cover_reg_top/45.hmac_intr_test.4123929647 May 16 02:27:42 PM PDT 24 May 16 02:27:48 PM PDT 24 48332609 ps
T530 /workspace/coverage/cover_reg_top/11.hmac_intr_test.1358312110 May 16 02:27:26 PM PDT 24 May 16 02:27:31 PM PDT 24 17580570 ps
T531 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.267952361 May 16 02:27:13 PM PDT 24 May 16 02:27:18 PM PDT 24 102862932 ps
T532 /workspace/coverage/cover_reg_top/24.hmac_intr_test.3682082024 May 16 02:27:45 PM PDT 24 May 16 02:27:51 PM PDT 24 127241267 ps
T533 /workspace/coverage/cover_reg_top/46.hmac_intr_test.3975723742 May 16 02:27:45 PM PDT 24 May 16 02:27:51 PM PDT 24 11583016 ps
T534 /workspace/coverage/cover_reg_top/5.hmac_intr_test.593970537 May 16 02:27:12 PM PDT 24 May 16 02:27:15 PM PDT 24 133352780 ps
T101 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.783185615 May 16 02:27:26 PM PDT 24 May 16 02:27:32 PM PDT 24 24689322 ps
T535 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.123811699 May 16 02:27:31 PM PDT 24 May 16 02:27:38 PM PDT 24 195704456 ps
T128 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.2252259471 May 16 02:27:32 PM PDT 24 May 16 02:27:41 PM PDT 24 761134435 ps
T104 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.1582347288 May 16 02:27:08 PM PDT 24 May 16 02:27:12 PM PDT 24 36888807 ps
T536 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.3122099593 May 16 02:27:02 PM PDT 24 May 16 02:27:07 PM PDT 24 25308283 ps
T103 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.3842682604 May 16 02:27:02 PM PDT 24 May 16 02:27:15 PM PDT 24 622477474 ps
T537 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.4174300276 May 16 02:27:33 PM PDT 24 May 16 02:27:41 PM PDT 24 33957361 ps
T130 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.2575759101 May 16 02:27:21 PM PDT 24 May 16 02:27:26 PM PDT 24 664739218 ps
T134 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.526511493 May 16 02:27:14 PM PDT 24 May 16 02:27:20 PM PDT 24 62202852 ps
T538 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.2489664823 May 16 02:27:22 PM PDT 24 May 16 02:27:26 PM PDT 24 170307099 ps
T539 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.1941660903 May 16 02:27:25 PM PDT 24 May 16 02:27:32 PM PDT 24 516049348 ps
T540 /workspace/coverage/cover_reg_top/27.hmac_intr_test.4187944274 May 16 02:27:43 PM PDT 24 May 16 02:27:50 PM PDT 24 18553247 ps
T541 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.3512133863 May 16 02:27:15 PM PDT 24 May 16 02:27:19 PM PDT 24 38533891 ps
T542 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.586440897 May 16 02:27:23 PM PDT 24 May 16 02:27:28 PM PDT 24 183233219 ps
T543 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.27989434 May 16 02:27:43 PM PDT 24 May 16 02:27:50 PM PDT 24 46790157 ps
T135 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.1765299442 May 16 02:27:07 PM PDT 24 May 16 02:27:15 PM PDT 24 1074703039 ps
T544 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.2102856736 May 16 02:27:03 PM PDT 24 May 16 02:27:08 PM PDT 24 44061864 ps
T545 /workspace/coverage/cover_reg_top/19.hmac_intr_test.2134227066 May 16 02:27:43 PM PDT 24 May 16 02:27:50 PM PDT 24 14125198 ps
T546 /workspace/coverage/cover_reg_top/48.hmac_intr_test.3975366436 May 16 02:27:44 PM PDT 24 May 16 02:27:51 PM PDT 24 21067510 ps
T547 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.1006216292 May 16 02:27:22 PM PDT 24 May 16 02:27:27 PM PDT 24 59415639 ps
T548 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.1438047857 May 16 02:27:31 PM PDT 24 May 16 02:27:39 PM PDT 24 77607791 ps
T549 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.1474687924 May 16 02:27:24 PM PDT 24 May 16 02:27:30 PM PDT 24 47513265 ps
T550 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.3294406969 May 16 02:27:05 PM PDT 24 May 16 02:27:11 PM PDT 24 211066592 ps
T551 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.2656439157 May 16 02:27:32 PM PDT 24 May 16 02:27:39 PM PDT 24 105853024 ps
T552 /workspace/coverage/cover_reg_top/33.hmac_intr_test.3435401974 May 16 02:27:41 PM PDT 24 May 16 02:27:47 PM PDT 24 16440987 ps
T553 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.1974406976 May 16 02:27:25 PM PDT 24 May 16 02:27:31 PM PDT 24 221424673 ps
T554 /workspace/coverage/cover_reg_top/16.hmac_intr_test.2128684965 May 16 02:27:32 PM PDT 24 May 16 02:27:38 PM PDT 24 50742710 ps
T555 /workspace/coverage/cover_reg_top/38.hmac_intr_test.3392711662 May 16 02:27:42 PM PDT 24 May 16 02:27:49 PM PDT 24 191770646 ps
T556 /workspace/coverage/cover_reg_top/17.hmac_intr_test.1916918134 May 16 02:27:32 PM PDT 24 May 16 02:27:38 PM PDT 24 43564429 ps
T557 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.1760103291 May 16 02:27:25 PM PDT 24 May 16 02:27:32 PM PDT 24 750313327 ps
T558 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.1132446777 May 16 02:27:22 PM PDT 24 May 16 02:27:27 PM PDT 24 160347745 ps
T559 /workspace/coverage/cover_reg_top/23.hmac_intr_test.375921262 May 16 02:27:41 PM PDT 24 May 16 02:27:48 PM PDT 24 36910378 ps
T560 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.2428875405 May 16 02:27:24 PM PDT 24 May 16 02:27:30 PM PDT 24 127544602 ps
T561 /workspace/coverage/cover_reg_top/6.hmac_intr_test.371235673 May 16 02:27:13 PM PDT 24 May 16 02:27:17 PM PDT 24 13685098 ps
T562 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.1095617627 May 16 02:27:02 PM PDT 24 May 16 02:27:08 PM PDT 24 32352928 ps
T563 /workspace/coverage/cover_reg_top/7.hmac_intr_test.2625950609 May 16 02:27:14 PM PDT 24 May 16 02:27:18 PM PDT 24 36676330 ps
T564 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.4150782197 May 16 02:27:31 PM PDT 24 May 16 02:27:39 PM PDT 24 149318651 ps
T565 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.503823077 May 16 02:27:35 PM PDT 24 May 16 02:27:43 PM PDT 24 199552659 ps
T566 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.1284552611 May 16 02:27:13 PM PDT 24 May 16 02:27:18 PM PDT 24 82508085 ps
T105 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.608813203 May 16 02:27:32 PM PDT 24 May 16 02:27:38 PM PDT 24 56706538 ps
T567 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.4226401014 May 16 02:27:10 PM PDT 24 May 16 02:27:14 PM PDT 24 31170747 ps
T106 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.340831336 May 16 02:27:30 PM PDT 24 May 16 02:27:36 PM PDT 24 53882440 ps
T568 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2799553551 May 16 02:27:03 PM PDT 24 May 16 02:27:09 PM PDT 24 40282304 ps
T569 /workspace/coverage/cover_reg_top/15.hmac_intr_test.3710999507 May 16 02:27:32 PM PDT 24 May 16 02:27:38 PM PDT 24 55358992 ps
T570 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.4149040628 May 16 02:27:03 PM PDT 24 May 16 02:27:10 PM PDT 24 95725405 ps
T571 /workspace/coverage/cover_reg_top/30.hmac_intr_test.2450698724 May 16 02:27:44 PM PDT 24 May 16 02:27:51 PM PDT 24 50230948 ps
T572 /workspace/coverage/cover_reg_top/9.hmac_intr_test.371697623 May 16 02:27:21 PM PDT 24 May 16 02:27:24 PM PDT 24 11532449 ps
T573 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.2457081968 May 16 02:27:04 PM PDT 24 May 16 02:27:09 PM PDT 24 81324235 ps
T574 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.2746266386 May 16 02:27:13 PM PDT 24 May 16 02:27:32 PM PDT 24 4375910730 ps
T575 /workspace/coverage/cover_reg_top/25.hmac_intr_test.2631997158 May 16 02:27:43 PM PDT 24 May 16 02:27:49 PM PDT 24 17585060 ps
T576 /workspace/coverage/cover_reg_top/1.hmac_intr_test.2759379936 May 16 02:27:00 PM PDT 24 May 16 02:27:04 PM PDT 24 14605373 ps
T577 /workspace/coverage/cover_reg_top/41.hmac_intr_test.470212122 May 16 02:27:44 PM PDT 24 May 16 02:27:50 PM PDT 24 14549551 ps
T578 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.3580376826 May 16 02:27:25 PM PDT 24 May 16 02:27:30 PM PDT 24 35313921 ps
T579 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.3465361513 May 16 02:27:14 PM PDT 24 May 16 02:27:22 PM PDT 24 282251041 ps
T580 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.3529429465 May 16 02:27:01 PM PDT 24 May 16 02:27:11 PM PDT 24 349323858 ps
T581 /workspace/coverage/cover_reg_top/44.hmac_intr_test.2927380803 May 16 02:27:42 PM PDT 24 May 16 02:27:48 PM PDT 24 24426322 ps
T582 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.828775939 May 16 02:27:33 PM PDT 24 May 16 02:27:40 PM PDT 24 35349213 ps
T583 /workspace/coverage/cover_reg_top/14.hmac_intr_test.2881772803 May 16 02:27:31 PM PDT 24 May 16 02:27:37 PM PDT 24 22360818 ps
T584 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.1256151569 May 16 02:27:24 PM PDT 24 May 16 02:27:29 PM PDT 24 24382466 ps
T585 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.1522420377 May 16 02:27:13 PM PDT 24 May 16 02:27:18 PM PDT 24 49387520 ps
T586 /workspace/coverage/cover_reg_top/10.hmac_intr_test.2977942844 May 16 02:27:23 PM PDT 24 May 16 02:27:28 PM PDT 24 21297023 ps
T587 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.1486277981 May 16 02:27:32 PM PDT 24 May 16 02:27:39 PM PDT 24 43925213 ps
T131 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.2434121608 May 16 02:27:24 PM PDT 24 May 16 02:27:31 PM PDT 24 1298960786 ps
T588 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.2059280285 May 16 02:27:24 PM PDT 24 May 16 02:40:57 PM PDT 24 82643042686 ps
T589 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.3083452539 May 16 02:27:04 PM PDT 24 May 16 02:27:12 PM PDT 24 338459820 ps
T590 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.862380933 May 16 02:27:24 PM PDT 24 May 16 02:27:30 PM PDT 24 62197129 ps
T591 /workspace/coverage/cover_reg_top/40.hmac_intr_test.3501235698 May 16 02:27:47 PM PDT 24 May 16 02:27:52 PM PDT 24 13787214 ps
T592 /workspace/coverage/cover_reg_top/26.hmac_intr_test.3647673119 May 16 02:27:43 PM PDT 24 May 16 02:27:50 PM PDT 24 27642251 ps
T593 /workspace/coverage/cover_reg_top/31.hmac_intr_test.2928948748 May 16 02:27:42 PM PDT 24 May 16 02:27:48 PM PDT 24 198028222 ps
T594 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.512591859 May 16 02:27:31 PM PDT 24 May 16 02:27:39 PM PDT 24 78739436 ps
T595 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.2548415026 May 16 02:27:01 PM PDT 24 May 16 02:27:11 PM PDT 24 232356390 ps
T596 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.973782828 May 16 02:27:09 PM PDT 24 May 16 02:27:19 PM PDT 24 683411213 ps
T597 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.307935357 May 16 02:27:25 PM PDT 24 May 16 02:27:32 PM PDT 24 1627113716 ps
T598 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.3580212055 May 16 02:27:09 PM PDT 24 May 16 02:27:13 PM PDT 24 405642449 ps
T132 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.1524928662 May 16 02:27:04 PM PDT 24 May 16 02:27:12 PM PDT 24 141803400 ps
T599 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.544549854 May 16 02:27:13 PM PDT 24 May 16 02:27:18 PM PDT 24 153774577 ps
T600 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.2204633761 May 16 02:27:14 PM PDT 24 May 16 02:27:20 PM PDT 24 42383177 ps
T136 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.1206910608 May 16 02:27:15 PM PDT 24 May 16 02:27:23 PM PDT 24 170929464 ps
T601 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.4191978529 May 16 02:27:30 PM PDT 24 May 16 02:27:38 PM PDT 24 40821286 ps
T602 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.2713216632 May 16 02:27:45 PM PDT 24 May 16 02:27:52 PM PDT 24 198016451 ps
T603 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.1582011257 May 16 02:27:14 PM PDT 24 May 16 02:27:19 PM PDT 24 54333670 ps
T604 /workspace/coverage/cover_reg_top/29.hmac_intr_test.2487735891 May 16 02:27:44 PM PDT 24 May 16 02:27:50 PM PDT 24 60534074 ps

Test location /workspace/coverage/default/25.hmac_datapath_stress.1542601676
Short name T3
Test name
Test status
Simulation time 13485910076 ps
CPU time 882.84 seconds
Started May 16 02:29:38 PM PDT 24
Finished May 16 02:44:23 PM PDT 24
Peak memory 745372 kb
Host smart-1a44fbb9-1394-478a-8713-10d2ba67cd94
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1542601676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.1542601676
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/154.hmac_stress_all_with_rand_reset.1043525218
Short name T11
Test name
Test status
Simulation time 94282115446 ps
CPU time 4299.63 seconds
Started May 16 02:32:01 PM PDT 24
Finished May 16 03:43:42 PM PDT 24
Peak memory 849680 kb
Host smart-1480c52b-47f7-4c97-860d-b3ace19d4be4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1043525218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.hmac_stress_all_with_rand_reset.1043525218
Directory /workspace/154.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.4204698761
Short name T7
Test name
Test status
Simulation time 13869211068 ps
CPU time 66.13 seconds
Started May 16 02:30:46 PM PDT 24
Finished May 16 02:31:55 PM PDT 24
Peak memory 249372 kb
Host smart-23035e04-d8b6-4292-aef3-02672115182f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4204698761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.4204698761
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.3307129509
Short name T2
Test name
Test status
Simulation time 895471831 ps
CPU time 1 seconds
Started May 16 02:28:30 PM PDT 24
Finished May 16 02:28:35 PM PDT 24
Peak memory 219916 kb
Host smart-ac646b24-db91-4ecb-89f1-6d460aeb85d1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307129509 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.3307129509
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.3568299363
Short name T15
Test name
Test status
Simulation time 27469732680 ps
CPU time 27.51 seconds
Started May 16 02:29:50 PM PDT 24
Finished May 16 02:30:20 PM PDT 24
Peak memory 200692 kb
Host smart-d371ca07-34aa-4081-8ea0-83129c206c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568299363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.3568299363
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.1134442660
Short name T50
Test name
Test status
Simulation time 396124747 ps
CPU time 1.85 seconds
Started May 16 02:27:32 PM PDT 24
Finished May 16 02:27:39 PM PDT 24
Peak memory 200036 kb
Host smart-f0b9942e-6963-4eb3-9492-3cbaad84df56
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134442660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.1134442660
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/177.hmac_stress_all_with_rand_reset.3662171667
Short name T10
Test name
Test status
Simulation time 42544444402 ps
CPU time 2457.98 seconds
Started May 16 02:32:14 PM PDT 24
Finished May 16 03:13:13 PM PDT 24
Peak memory 798856 kb
Host smart-f57ea375-de9f-4636-8bcb-bbc2ac6c05ab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3662171667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.hmac_stress_all_with_rand_reset.3662171667
Directory /workspace/177.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.3401197973
Short name T21
Test name
Test status
Simulation time 1866213804 ps
CPU time 46.59 seconds
Started May 16 02:30:19 PM PDT 24
Finished May 16 02:31:07 PM PDT 24
Peak memory 200664 kb
Host smart-1a886610-dbc7-45c6-938e-9c772fb9d602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401197973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.3401197973
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.1682528238
Short name T399
Test name
Test status
Simulation time 900167598 ps
CPU time 5.68 seconds
Started May 16 02:28:59 PM PDT 24
Finished May 16 02:29:10 PM PDT 24
Peak memory 200552 kb
Host smart-6fc37f11-b25d-4d20-9b21-d07e8bcb925b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682528238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.1682528238
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.2575759101
Short name T130
Test name
Test status
Simulation time 664739218 ps
CPU time 3.08 seconds
Started May 16 02:27:21 PM PDT 24
Finished May 16 02:27:26 PM PDT 24
Peak memory 200044 kb
Host smart-7648be77-8aca-4e76-8027-511534addfde
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575759101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.2575759101
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.1418927341
Short name T4
Test name
Test status
Simulation time 4354629225 ps
CPU time 494.18 seconds
Started May 16 02:30:21 PM PDT 24
Finished May 16 02:38:37 PM PDT 24
Peak memory 718092 kb
Host smart-f6b595f3-65b3-4098-acca-941068f7d525
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1418927341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.1418927341
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_alert_test.3226769630
Short name T24
Test name
Test status
Simulation time 16766707 ps
CPU time 0.65 seconds
Started May 16 02:31:07 PM PDT 24
Finished May 16 02:31:10 PM PDT 24
Peak memory 196372 kb
Host smart-da60f3fc-f61d-441a-be13-20e521b0b8ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226769630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.3226769630
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.91409704
Short name T71
Test name
Test status
Simulation time 1369648922 ps
CPU time 11.6 seconds
Started May 16 02:27:01 PM PDT 24
Finished May 16 02:27:16 PM PDT 24
Peak memory 199920 kb
Host smart-f9c442e2-3be3-43a8-80af-8067f74e9b70
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91409704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.91409704
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.1528601381
Short name T115
Test name
Test status
Simulation time 4565497381 ps
CPU time 60.89 seconds
Started May 16 02:30:35 PM PDT 24
Finished May 16 02:31:38 PM PDT 24
Peak memory 233492 kb
Host smart-728898a1-eb4a-4624-b498-6d5f45e4469b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1528601381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.1528601381
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.1765299442
Short name T135
Test name
Test status
Simulation time 1074703039 ps
CPU time 4.48 seconds
Started May 16 02:27:07 PM PDT 24
Finished May 16 02:27:15 PM PDT 24
Peak memory 200036 kb
Host smart-82e6f796-a926-433f-8c89-a3bd8e636fbb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765299442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.1765299442
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.4062940153
Short name T116
Test name
Test status
Simulation time 3494115686 ps
CPU time 870.97 seconds
Started May 16 02:28:56 PM PDT 24
Finished May 16 02:43:31 PM PDT 24
Peak memory 735324 kb
Host smart-03266d6e-b30b-4a91-83bf-2af10eacd00a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4062940153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.4062940153
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.1004631562
Short name T90
Test name
Test status
Simulation time 4605609568 ps
CPU time 1272.55 seconds
Started May 16 02:29:18 PM PDT 24
Finished May 16 02:50:34 PM PDT 24
Peak memory 787348 kb
Host smart-c5c6db16-e322-4258-90dc-da4b3f6c6dc1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1004631562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.1004631562
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.3624130452
Short name T54
Test name
Test status
Simulation time 885244172 ps
CPU time 3.84 seconds
Started May 16 02:27:33 PM PDT 24
Finished May 16 02:27:42 PM PDT 24
Peak memory 200000 kb
Host smart-2e28d0ad-030f-4ac8-ba0f-8149a542031f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624130452 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.3624130452
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.2911296815
Short name T478
Test name
Test status
Simulation time 28037856 ps
CPU time 0.61 seconds
Started May 16 02:27:22 PM PDT 24
Finished May 16 02:27:25 PM PDT 24
Peak memory 195036 kb
Host smart-66b30c48-273a-4ecb-ba33-7688fa79b031
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911296815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.2911296815
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.2252259471
Short name T128
Test name
Test status
Simulation time 761134435 ps
CPU time 3.13 seconds
Started May 16 02:27:32 PM PDT 24
Finished May 16 02:27:41 PM PDT 24
Peak memory 200036 kb
Host smart-748cc987-c657-4a66-b492-2b286dee2d0e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252259471 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.2252259471
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/14.hmac_long_msg.805833890
Short name T14
Test name
Test status
Simulation time 7015140279 ps
CPU time 136.42 seconds
Started May 16 02:29:00 PM PDT 24
Finished May 16 02:31:22 PM PDT 24
Peak memory 200692 kb
Host smart-b3592b33-ee66-4bc7-89d4-b1467eb37b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805833890 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.805833890
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.479762585
Short name T395
Test name
Test status
Simulation time 545135428 ps
CPU time 35.85 seconds
Started May 16 02:29:10 PM PDT 24
Finished May 16 02:29:49 PM PDT 24
Peak memory 231332 kb
Host smart-4474d8aa-d0e1-4900-a8c3-f1710ba8968f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=479762585 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.479762585
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_stress_all_with_rand_reset.1316105268
Short name T13
Test name
Test status
Simulation time 98457634485 ps
CPU time 395.51 seconds
Started May 16 02:29:36 PM PDT 24
Finished May 16 02:36:14 PM PDT 24
Peak memory 241848 kb
Host smart-03545f53-f7ec-465a-83db-c0c4b10f60f4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1316105268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all_with_rand_reset.1316105268
Directory /workspace/24.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.973782828
Short name T596
Test name
Test status
Simulation time 683411213 ps
CPU time 6.35 seconds
Started May 16 02:27:09 PM PDT 24
Finished May 16 02:27:19 PM PDT 24
Peak memory 200092 kb
Host smart-93825edd-ac3e-4f07-8132-f07d35dab5fb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973782828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.973782828
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.2457081968
Short name T573
Test name
Test status
Simulation time 81324235 ps
CPU time 1.01 seconds
Started May 16 02:27:04 PM PDT 24
Finished May 16 02:27:09 PM PDT 24
Peak memory 199724 kb
Host smart-a144f23c-8fc3-4456-bb74-6d0e8dbbe5bd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457081968 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.2457081968
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2799553551
Short name T568
Test name
Test status
Simulation time 40282304 ps
CPU time 1.35 seconds
Started May 16 02:27:03 PM PDT 24
Finished May 16 02:27:09 PM PDT 24
Peak memory 200072 kb
Host smart-19db5a92-59df-46a7-ab60-dba7f0babb26
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799553551 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.2799553551
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.3951774683
Short name T94
Test name
Test status
Simulation time 25168720 ps
CPU time 0.82 seconds
Started May 16 02:27:07 PM PDT 24
Finished May 16 02:27:12 PM PDT 24
Peak memory 199844 kb
Host smart-f1cf7afa-3faa-4c90-8b49-f93652556dca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951774683 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.3951774683
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.1865957122
Short name T513
Test name
Test status
Simulation time 25067732 ps
CPU time 0.59 seconds
Started May 16 02:27:01 PM PDT 24
Finished May 16 02:27:05 PM PDT 24
Peak memory 194956 kb
Host smart-260a350b-a83a-438b-a7d3-0d9e324e5a7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865957122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.1865957122
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.3122099593
Short name T536
Test name
Test status
Simulation time 25308283 ps
CPU time 1.13 seconds
Started May 16 02:27:02 PM PDT 24
Finished May 16 02:27:07 PM PDT 24
Peak memory 199372 kb
Host smart-1379bde2-c677-4a5d-b733-4e7e8be2428a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122099593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.3122099593
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.4121549329
Short name T58
Test name
Test status
Simulation time 825440978 ps
CPU time 4.53 seconds
Started May 16 02:27:01 PM PDT 24
Finished May 16 02:27:09 PM PDT 24
Peak memory 200112 kb
Host smart-9f936a26-4df5-4e77-92c2-673a89ffdbb2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121549329 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.4121549329
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.3529429465
Short name T580
Test name
Test status
Simulation time 349323858 ps
CPU time 5.95 seconds
Started May 16 02:27:01 PM PDT 24
Finished May 16 02:27:11 PM PDT 24
Peak memory 199984 kb
Host smart-c43a3e32-ecd5-4916-84ac-cc411cd47adf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529429465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.3529429465
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.924156209
Short name T102
Test name
Test status
Simulation time 3933265275 ps
CPU time 5.81 seconds
Started May 16 02:27:05 PM PDT 24
Finished May 16 02:27:14 PM PDT 24
Peak memory 200100 kb
Host smart-bbb924c3-0332-4e12-bb13-cae8df277826
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924156209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.924156209
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.3616628187
Short name T70
Test name
Test status
Simulation time 36926336 ps
CPU time 0.79 seconds
Started May 16 02:27:00 PM PDT 24
Finished May 16 02:27:04 PM PDT 24
Peak memory 197828 kb
Host smart-0763daa8-88d3-48c1-b8ba-1fcc1e263ef8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616628187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.3616628187
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2803734485
Short name T498
Test name
Test status
Simulation time 145511834 ps
CPU time 1.95 seconds
Started May 16 02:27:09 PM PDT 24
Finished May 16 02:27:14 PM PDT 24
Peak memory 200088 kb
Host smart-9a6f585a-19fc-4a93-96c1-e22c33e2608d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803734485 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.2803734485
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.1095617627
Short name T562
Test name
Test status
Simulation time 32352928 ps
CPU time 0.84 seconds
Started May 16 02:27:02 PM PDT 24
Finished May 16 02:27:08 PM PDT 24
Peak memory 199176 kb
Host smart-31a06ea1-4a0e-4393-a4aa-b52083800058
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095617627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.1095617627
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.2759379936
Short name T576
Test name
Test status
Simulation time 14605373 ps
CPU time 0.61 seconds
Started May 16 02:27:00 PM PDT 24
Finished May 16 02:27:04 PM PDT 24
Peak memory 194836 kb
Host smart-35ed0b46-6602-4e32-b703-d72077f33436
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759379936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.2759379936
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.165497907
Short name T512
Test name
Test status
Simulation time 121255651 ps
CPU time 1.51 seconds
Started May 16 02:27:04 PM PDT 24
Finished May 16 02:27:10 PM PDT 24
Peak memory 199332 kb
Host smart-3600eb6d-0570-4922-b3ec-8d104e47cdab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165497907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr_
outstanding.165497907
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.4226401014
Short name T567
Test name
Test status
Simulation time 31170747 ps
CPU time 1.52 seconds
Started May 16 02:27:10 PM PDT 24
Finished May 16 02:27:14 PM PDT 24
Peak memory 200072 kb
Host smart-d7e94214-b6fa-4c6e-a4e8-c00e329fa2e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226401014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.4226401014
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.4149040628
Short name T570
Test name
Test status
Simulation time 95725405 ps
CPU time 2.79 seconds
Started May 16 02:27:03 PM PDT 24
Finished May 16 02:27:10 PM PDT 24
Peak memory 200076 kb
Host smart-b635b887-f577-4b4e-ba40-7765c485d136
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149040628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.4149040628
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.2059280285
Short name T588
Test name
Test status
Simulation time 82643042686 ps
CPU time 807.91 seconds
Started May 16 02:27:24 PM PDT 24
Finished May 16 02:40:57 PM PDT 24
Peak memory 216580 kb
Host smart-7644e7d6-5d72-49ef-85cd-d6917275d29a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059280285 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.2059280285
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.2089232919
Short name T510
Test name
Test status
Simulation time 15498593 ps
CPU time 0.71 seconds
Started May 16 02:27:25 PM PDT 24
Finished May 16 02:27:31 PM PDT 24
Peak memory 197776 kb
Host smart-8d4cf586-70f7-4ca0-bdc1-0beb93b60505
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089232919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.2089232919
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.2977942844
Short name T586
Test name
Test status
Simulation time 21297023 ps
CPU time 0.62 seconds
Started May 16 02:27:23 PM PDT 24
Finished May 16 02:27:28 PM PDT 24
Peak memory 194836 kb
Host smart-2adf5777-70aa-441e-9591-b9a895ac6ffc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977942844 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.2977942844
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.1760103291
Short name T557
Test name
Test status
Simulation time 750313327 ps
CPU time 2.24 seconds
Started May 16 02:27:25 PM PDT 24
Finished May 16 02:27:32 PM PDT 24
Peak memory 200040 kb
Host smart-c201824f-bf80-41e8-9c23-737e9a437e03
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760103291 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.1760103291
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.1132446777
Short name T558
Test name
Test status
Simulation time 160347745 ps
CPU time 2.26 seconds
Started May 16 02:27:22 PM PDT 24
Finished May 16 02:27:27 PM PDT 24
Peak memory 200088 kb
Host smart-34509e45-0606-4fba-8700-ef3461a306a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132446777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.1132446777
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.307935357
Short name T597
Test name
Test status
Simulation time 1627113716 ps
CPU time 3.18 seconds
Started May 16 02:27:25 PM PDT 24
Finished May 16 02:27:32 PM PDT 24
Peak memory 200020 kb
Host smart-e09b3486-8e9a-44d7-87bb-bf42b52e7bf8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307935357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.307935357
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.711081008
Short name T518
Test name
Test status
Simulation time 76488527 ps
CPU time 2.4 seconds
Started May 16 02:27:25 PM PDT 24
Finished May 16 02:27:32 PM PDT 24
Peak memory 200048 kb
Host smart-ac6f980f-3f61-442a-845d-37395a718d31
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711081008 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.711081008
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.1256151569
Short name T584
Test name
Test status
Simulation time 24382466 ps
CPU time 0.83 seconds
Started May 16 02:27:24 PM PDT 24
Finished May 16 02:27:29 PM PDT 24
Peak memory 199404 kb
Host smart-3286fd83-b656-4245-80d7-acdbfa6e8083
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256151569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.1256151569
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.1358312110
Short name T530
Test name
Test status
Simulation time 17580570 ps
CPU time 0.59 seconds
Started May 16 02:27:26 PM PDT 24
Finished May 16 02:27:31 PM PDT 24
Peak memory 194936 kb
Host smart-96e86297-ed46-4c23-a1bc-d13e89a4790b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358312110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.1358312110
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.2489664823
Short name T538
Test name
Test status
Simulation time 170307099 ps
CPU time 2.12 seconds
Started May 16 02:27:22 PM PDT 24
Finished May 16 02:27:26 PM PDT 24
Peak memory 199492 kb
Host smart-932dae2d-a40d-4d55-9db8-6e2b9c93c9b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489664823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.2489664823
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.1006216292
Short name T547
Test name
Test status
Simulation time 59415639 ps
CPU time 3.15 seconds
Started May 16 02:27:22 PM PDT 24
Finished May 16 02:27:27 PM PDT 24
Peak memory 200076 kb
Host smart-8329ac11-ec8a-499a-a3c1-5f52e058adfe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006216292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.1006216292
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.1022560501
Short name T52
Test name
Test status
Simulation time 186254363 ps
CPU time 1.85 seconds
Started May 16 02:27:23 PM PDT 24
Finished May 16 02:27:30 PM PDT 24
Peak memory 199912 kb
Host smart-3b1a48f0-3836-4f2b-bccc-5807f24e6d8b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022560501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.1022560501
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.775973092
Short name T487
Test name
Test status
Simulation time 74622487 ps
CPU time 1.24 seconds
Started May 16 02:27:25 PM PDT 24
Finished May 16 02:27:32 PM PDT 24
Peak memory 199852 kb
Host smart-7c255d0d-e88d-4336-bdbf-266aaa4d1c8f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775973092 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.775973092
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.3580376826
Short name T578
Test name
Test status
Simulation time 35313921 ps
CPU time 0.72 seconds
Started May 16 02:27:25 PM PDT 24
Finished May 16 02:27:30 PM PDT 24
Peak memory 198048 kb
Host smart-18777ff6-127f-43aa-acde-bebe32bd5cac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580376826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.3580376826
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.2490494482
Short name T514
Test name
Test status
Simulation time 35145067 ps
CPU time 0.62 seconds
Started May 16 02:27:26 PM PDT 24
Finished May 16 02:27:31 PM PDT 24
Peak memory 194900 kb
Host smart-f753d9a6-75cc-4cd0-8edb-9c45bddd5743
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490494482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.2490494482
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.4236951171
Short name T480
Test name
Test status
Simulation time 111374693 ps
CPU time 1.54 seconds
Started May 16 02:27:26 PM PDT 24
Finished May 16 02:27:33 PM PDT 24
Peak memory 199988 kb
Host smart-4d5dde6c-9de4-4d13-84d0-16f1b647b63d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236951171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.4236951171
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.1974406976
Short name T553
Test name
Test status
Simulation time 221424673 ps
CPU time 1.64 seconds
Started May 16 02:27:25 PM PDT 24
Finished May 16 02:27:31 PM PDT 24
Peak memory 200040 kb
Host smart-49529996-781e-4ff6-b1f4-4f481f119d5d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974406976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.1974406976
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.2434121608
Short name T131
Test name
Test status
Simulation time 1298960786 ps
CPU time 2.87 seconds
Started May 16 02:27:24 PM PDT 24
Finished May 16 02:27:31 PM PDT 24
Peak memory 200008 kb
Host smart-0d22992b-3ae9-4ac0-b602-26d9494bfad4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434121608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.2434121608
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.4197238449
Short name T509
Test name
Test status
Simulation time 1135201090091 ps
CPU time 689.37 seconds
Started May 16 02:27:33 PM PDT 24
Finished May 16 02:39:08 PM PDT 24
Peak memory 224760 kb
Host smart-92343f83-fdf2-4f6d-80e2-92e7e7b591e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197238449 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.4197238449
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.783185615
Short name T101
Test name
Test status
Simulation time 24689322 ps
CPU time 0.8 seconds
Started May 16 02:27:26 PM PDT 24
Finished May 16 02:27:32 PM PDT 24
Peak memory 199516 kb
Host smart-714a7a75-18bf-407e-8a34-0aab08bf9fb9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783185615 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.783185615
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.123811699
Short name T535
Test name
Test status
Simulation time 195704456 ps
CPU time 1.1 seconds
Started May 16 02:27:31 PM PDT 24
Finished May 16 02:27:38 PM PDT 24
Peak memory 199748 kb
Host smart-d1a9fc74-026c-4fce-b7be-75be22f501bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123811699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_csr
_outstanding.123811699
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.2428875405
Short name T560
Test name
Test status
Simulation time 127544602 ps
CPU time 1.62 seconds
Started May 16 02:27:24 PM PDT 24
Finished May 16 02:27:30 PM PDT 24
Peak memory 200104 kb
Host smart-b4864c0a-f805-46d0-8be2-1766302cdbf1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428875405 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.2428875405
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.1941660903
Short name T539
Test name
Test status
Simulation time 516049348 ps
CPU time 1.87 seconds
Started May 16 02:27:25 PM PDT 24
Finished May 16 02:27:32 PM PDT 24
Peak memory 199960 kb
Host smart-f145ad79-2f93-4e7a-b1f4-5e1f77aa7f92
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941660903 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.1941660903
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.2258488555
Short name T55
Test name
Test status
Simulation time 493790227 ps
CPU time 1.87 seconds
Started May 16 02:27:35 PM PDT 24
Finished May 16 02:27:43 PM PDT 24
Peak memory 200116 kb
Host smart-ee37e877-045b-40a7-a5bc-19b6415712d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258488555 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.2258488555
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.3230217087
Short name T484
Test name
Test status
Simulation time 21169471 ps
CPU time 0.69 seconds
Started May 16 02:27:35 PM PDT 24
Finished May 16 02:27:41 PM PDT 24
Peak memory 197372 kb
Host smart-b8adfb8e-27e5-4800-9f6a-234bca402482
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230217087 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.3230217087
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.2881772803
Short name T583
Test name
Test status
Simulation time 22360818 ps
CPU time 0.55 seconds
Started May 16 02:27:31 PM PDT 24
Finished May 16 02:27:37 PM PDT 24
Peak memory 194864 kb
Host smart-051b08e4-bd3e-4564-ae77-2c0accc97d4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881772803 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.2881772803
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.1074266855
Short name T491
Test name
Test status
Simulation time 37967550 ps
CPU time 1.69 seconds
Started May 16 02:27:32 PM PDT 24
Finished May 16 02:27:39 PM PDT 24
Peak memory 200044 kb
Host smart-329d93a5-1c31-4183-abfe-c0a9c5b50e33
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074266855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.1074266855
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.672831089
Short name T527
Test name
Test status
Simulation time 40727343 ps
CPU time 2.13 seconds
Started May 16 02:27:32 PM PDT 24
Finished May 16 02:27:40 PM PDT 24
Peak memory 200036 kb
Host smart-3f548bf7-4ed6-4233-8ae0-971e14143c10
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672831089 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.672831089
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.3671331674
Short name T502
Test name
Test status
Simulation time 54953178 ps
CPU time 1.78 seconds
Started May 16 02:27:34 PM PDT 24
Finished May 16 02:27:41 PM PDT 24
Peak memory 200100 kb
Host smart-7e3d7c06-a119-46ec-ab45-4484d910ff73
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671331674 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.3671331674
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.4150782197
Short name T564
Test name
Test status
Simulation time 149318651 ps
CPU time 2.04 seconds
Started May 16 02:27:31 PM PDT 24
Finished May 16 02:27:39 PM PDT 24
Peak memory 200008 kb
Host smart-52642dd6-8943-4563-9620-d09d25f254a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150782197 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.4150782197
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.1523733481
Short name T492
Test name
Test status
Simulation time 33744822 ps
CPU time 0.72 seconds
Started May 16 02:27:33 PM PDT 24
Finished May 16 02:27:39 PM PDT 24
Peak memory 197832 kb
Host smart-719a3da5-b8af-4655-a78b-5a34f2ad5835
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523733481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.1523733481
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.3710999507
Short name T569
Test name
Test status
Simulation time 55358992 ps
CPU time 0.63 seconds
Started May 16 02:27:32 PM PDT 24
Finished May 16 02:27:38 PM PDT 24
Peak memory 194868 kb
Host smart-eb9580fe-8b70-469e-8b90-571175fde919
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710999507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.3710999507
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.2656439157
Short name T551
Test name
Test status
Simulation time 105853024 ps
CPU time 1.85 seconds
Started May 16 02:27:32 PM PDT 24
Finished May 16 02:27:39 PM PDT 24
Peak memory 200024 kb
Host smart-1fce5aaf-0914-419f-a553-cbe58bd0293c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656439157 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.2656439157
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.1138564648
Short name T82
Test name
Test status
Simulation time 26848466 ps
CPU time 1.45 seconds
Started May 16 02:27:36 PM PDT 24
Finished May 16 02:27:43 PM PDT 24
Peak memory 200120 kb
Host smart-40f83dc0-a8a2-463c-8556-26232c6e4f05
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138564648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.1138564648
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.4219653882
Short name T508
Test name
Test status
Simulation time 9676691864 ps
CPU time 95.1 seconds
Started May 16 02:27:33 PM PDT 24
Finished May 16 02:29:14 PM PDT 24
Peak memory 215956 kb
Host smart-43e5d1b7-10ab-4a55-8e8e-f1483bc2d558
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219653882 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.4219653882
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.828775939
Short name T582
Test name
Test status
Simulation time 35349213 ps
CPU time 0.99 seconds
Started May 16 02:27:33 PM PDT 24
Finished May 16 02:27:40 PM PDT 24
Peak memory 199536 kb
Host smart-d27a379e-e906-4075-b004-28f40bac724a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828775939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.828775939
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.2128684965
Short name T554
Test name
Test status
Simulation time 50742710 ps
CPU time 0.61 seconds
Started May 16 02:27:32 PM PDT 24
Finished May 16 02:27:38 PM PDT 24
Peak memory 194908 kb
Host smart-7690eb62-df88-4ac2-9e67-a3841145b0b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128684965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.2128684965
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.740309790
Short name T511
Test name
Test status
Simulation time 31503633 ps
CPU time 1.59 seconds
Started May 16 02:27:31 PM PDT 24
Finished May 16 02:27:38 PM PDT 24
Peak memory 199912 kb
Host smart-8e39dbb4-63ea-4b79-a2f9-a6bbf6c5cb69
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740309790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_csr
_outstanding.740309790
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.4174300276
Short name T537
Test name
Test status
Simulation time 33957361 ps
CPU time 2.04 seconds
Started May 16 02:27:33 PM PDT 24
Finished May 16 02:27:41 PM PDT 24
Peak memory 200052 kb
Host smart-fddfb126-dfe7-43e4-8cf0-f77f41408ce8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174300276 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.4174300276
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.1016446216
Short name T523
Test name
Test status
Simulation time 183754677 ps
CPU time 1.69 seconds
Started May 16 02:27:31 PM PDT 24
Finished May 16 02:27:39 PM PDT 24
Peak memory 200084 kb
Host smart-1ec11721-ce3f-491b-9444-73113b2ceed3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016446216 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.1016446216
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.1486277981
Short name T587
Test name
Test status
Simulation time 43925213 ps
CPU time 1.25 seconds
Started May 16 02:27:32 PM PDT 24
Finished May 16 02:27:39 PM PDT 24
Peak memory 199904 kb
Host smart-c80ed595-1f59-4075-8286-326e7212d530
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486277981 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.1486277981
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.608813203
Short name T105
Test name
Test status
Simulation time 56706538 ps
CPU time 0.91 seconds
Started May 16 02:27:32 PM PDT 24
Finished May 16 02:27:38 PM PDT 24
Peak memory 199492 kb
Host smart-06d26d1f-3394-4666-8c0b-2609bf6088e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608813203 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.608813203
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.1916918134
Short name T556
Test name
Test status
Simulation time 43564429 ps
CPU time 0.59 seconds
Started May 16 02:27:32 PM PDT 24
Finished May 16 02:27:38 PM PDT 24
Peak memory 194948 kb
Host smart-e5970e0e-a4f1-4a49-9887-51b98065a2ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916918134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.1916918134
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.503823077
Short name T565
Test name
Test status
Simulation time 199552659 ps
CPU time 2.27 seconds
Started May 16 02:27:35 PM PDT 24
Finished May 16 02:27:43 PM PDT 24
Peak memory 199904 kb
Host smart-a7d48016-2840-41d6-8015-4d66b3f2c3c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503823077 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_csr
_outstanding.503823077
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.1844044556
Short name T528
Test name
Test status
Simulation time 758820289 ps
CPU time 4.36 seconds
Started May 16 02:27:33 PM PDT 24
Finished May 16 02:27:43 PM PDT 24
Peak memory 200016 kb
Host smart-d4fab2ab-ce31-4d1e-8639-6f083058b607
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844044556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.1844044556
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.1438047857
Short name T548
Test name
Test status
Simulation time 77607791 ps
CPU time 1.98 seconds
Started May 16 02:27:31 PM PDT 24
Finished May 16 02:27:39 PM PDT 24
Peak memory 200092 kb
Host smart-9599df4c-149d-41d8-b345-97bfd5ef0db4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438047857 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.1438047857
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.340831336
Short name T106
Test name
Test status
Simulation time 53882440 ps
CPU time 0.82 seconds
Started May 16 02:27:30 PM PDT 24
Finished May 16 02:27:36 PM PDT 24
Peak memory 199160 kb
Host smart-d6668373-3914-4340-b650-06b9028777f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340831336 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.340831336
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.931122455
Short name T488
Test name
Test status
Simulation time 50897889 ps
CPU time 0.6 seconds
Started May 16 02:27:31 PM PDT 24
Finished May 16 02:27:38 PM PDT 24
Peak memory 194992 kb
Host smart-f9e1c863-17bc-472c-88a1-b23f3bc84d70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931122455 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.931122455
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.512591859
Short name T594
Test name
Test status
Simulation time 78739436 ps
CPU time 1.58 seconds
Started May 16 02:27:31 PM PDT 24
Finished May 16 02:27:39 PM PDT 24
Peak memory 199976 kb
Host smart-e04a7f49-9b05-49f0-88ad-7d248449e39c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512591859 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_csr
_outstanding.512591859
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.4191978529
Short name T601
Test name
Test status
Simulation time 40821286 ps
CPU time 2.02 seconds
Started May 16 02:27:30 PM PDT 24
Finished May 16 02:27:38 PM PDT 24
Peak memory 200096 kb
Host smart-35f36553-eca5-4e4d-bba7-8a4ad57917f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191978529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.4191978529
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.2713216632
Short name T602
Test name
Test status
Simulation time 198016451 ps
CPU time 1.73 seconds
Started May 16 02:27:45 PM PDT 24
Finished May 16 02:27:52 PM PDT 24
Peak memory 200088 kb
Host smart-99579c9e-1909-4339-8591-2f9157f9574d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713216632 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.2713216632
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.27989434
Short name T543
Test name
Test status
Simulation time 46790157 ps
CPU time 0.72 seconds
Started May 16 02:27:43 PM PDT 24
Finished May 16 02:27:50 PM PDT 24
Peak memory 197792 kb
Host smart-918860b2-3fdc-4e5f-837c-ec1b9c7d6775
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27989434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.27989434
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.2134227066
Short name T545
Test name
Test status
Simulation time 14125198 ps
CPU time 0.64 seconds
Started May 16 02:27:43 PM PDT 24
Finished May 16 02:27:50 PM PDT 24
Peak memory 194992 kb
Host smart-dcbabc54-ab12-4e2a-9976-21c6b6444c35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134227066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.2134227066
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.317093384
Short name T56
Test name
Test status
Simulation time 417082471 ps
CPU time 1.22 seconds
Started May 16 02:27:42 PM PDT 24
Finished May 16 02:27:49 PM PDT 24
Peak memory 198380 kb
Host smart-faf075d6-8859-4d04-abd7-bb3f1a8d6623
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317093384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_csr
_outstanding.317093384
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.3458767455
Short name T57
Test name
Test status
Simulation time 262649356 ps
CPU time 1.63 seconds
Started May 16 02:27:43 PM PDT 24
Finished May 16 02:27:51 PM PDT 24
Peak memory 200176 kb
Host smart-781663fe-e444-4582-b558-d1c6c4e6213d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458767455 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.3458767455
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.548429069
Short name T127
Test name
Test status
Simulation time 50731882 ps
CPU time 1.75 seconds
Started May 16 02:27:45 PM PDT 24
Finished May 16 02:27:53 PM PDT 24
Peak memory 200004 kb
Host smart-aa32967d-1ffe-4f4f-9728-514125756b0c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548429069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.548429069
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.2548415026
Short name T595
Test name
Test status
Simulation time 232356390 ps
CPU time 5.57 seconds
Started May 16 02:27:01 PM PDT 24
Finished May 16 02:27:11 PM PDT 24
Peak memory 200048 kb
Host smart-66b418c9-2265-4f94-ba63-f8008ca6203f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548415026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.2548415026
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.339996327
Short name T516
Test name
Test status
Simulation time 2338179309 ps
CPU time 16.54 seconds
Started May 16 02:27:02 PM PDT 24
Finished May 16 02:27:23 PM PDT 24
Peak memory 199416 kb
Host smart-33665615-bfa8-4de6-9861-86b8c55d5d8b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339996327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.339996327
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.3580212055
Short name T598
Test name
Test status
Simulation time 405642449 ps
CPU time 1.04 seconds
Started May 16 02:27:09 PM PDT 24
Finished May 16 02:27:13 PM PDT 24
Peak memory 199856 kb
Host smart-66d1d6cd-8e32-49f7-a708-321fd021d6af
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580212055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.3580212055
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.3055446213
Short name T490
Test name
Test status
Simulation time 112535081 ps
CPU time 1.38 seconds
Started May 16 02:27:03 PM PDT 24
Finished May 16 02:27:09 PM PDT 24
Peak memory 200052 kb
Host smart-0f449674-6779-4649-9c52-b9af2748e8d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055446213 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.3055446213
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.3655824856
Short name T98
Test name
Test status
Simulation time 28325896 ps
CPU time 0.93 seconds
Started May 16 02:27:09 PM PDT 24
Finished May 16 02:27:13 PM PDT 24
Peak memory 199604 kb
Host smart-1cb85f80-255a-4809-a1a2-32a433f1bca3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655824856 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.3655824856
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.3106596300
Short name T477
Test name
Test status
Simulation time 112305247 ps
CPU time 0.6 seconds
Started May 16 02:27:02 PM PDT 24
Finished May 16 02:27:07 PM PDT 24
Peak memory 194880 kb
Host smart-f60fdcf7-18ee-4a35-8383-2bd07fc166cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106596300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.3106596300
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.602279149
Short name T505
Test name
Test status
Simulation time 563630610 ps
CPU time 2.54 seconds
Started May 16 02:27:04 PM PDT 24
Finished May 16 02:27:10 PM PDT 24
Peak memory 199940 kb
Host smart-40f94905-9b58-4623-aa75-86e1d45bf418
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602279149 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr_
outstanding.602279149
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.205980716
Short name T483
Test name
Test status
Simulation time 73773706 ps
CPU time 3.63 seconds
Started May 16 02:27:07 PM PDT 24
Finished May 16 02:27:15 PM PDT 24
Peak memory 200084 kb
Host smart-0e80a0c6-e5ee-44d2-86bb-b2b066098102
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205980716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.205980716
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.1524928662
Short name T132
Test name
Test status
Simulation time 141803400 ps
CPU time 4.08 seconds
Started May 16 02:27:04 PM PDT 24
Finished May 16 02:27:12 PM PDT 24
Peak memory 200052 kb
Host smart-5fe892bc-d397-4ec7-9eb1-201fc0436e9c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524928662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.1524928662
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.2483327483
Short name T515
Test name
Test status
Simulation time 23086267 ps
CPU time 0.56 seconds
Started May 16 02:27:42 PM PDT 24
Finished May 16 02:27:48 PM PDT 24
Peak memory 194884 kb
Host smart-b53e643b-e598-4366-959b-71e8c25f0f77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483327483 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.2483327483
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.3607090893
Short name T521
Test name
Test status
Simulation time 19303888 ps
CPU time 0.63 seconds
Started May 16 02:27:42 PM PDT 24
Finished May 16 02:27:48 PM PDT 24
Peak memory 194992 kb
Host smart-7f17d9c9-cefd-4456-b437-2dd264dc2252
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607090893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.3607090893
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.2323247319
Short name T500
Test name
Test status
Simulation time 13742048 ps
CPU time 0.6 seconds
Started May 16 02:27:42 PM PDT 24
Finished May 16 02:27:48 PM PDT 24
Peak memory 194844 kb
Host smart-18e23a6a-30cb-4835-9a83-7db68c63d9eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323247319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.2323247319
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.375921262
Short name T559
Test name
Test status
Simulation time 36910378 ps
CPU time 0.62 seconds
Started May 16 02:27:41 PM PDT 24
Finished May 16 02:27:48 PM PDT 24
Peak memory 194868 kb
Host smart-748c28c7-35b2-44d2-a719-649fae08da57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375921262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.375921262
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.3682082024
Short name T532
Test name
Test status
Simulation time 127241267 ps
CPU time 0.63 seconds
Started May 16 02:27:45 PM PDT 24
Finished May 16 02:27:51 PM PDT 24
Peak memory 194972 kb
Host smart-9f350e48-e368-4e11-b909-ae4c8701db36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682082024 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.3682082024
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.2631997158
Short name T575
Test name
Test status
Simulation time 17585060 ps
CPU time 0.62 seconds
Started May 16 02:27:43 PM PDT 24
Finished May 16 02:27:49 PM PDT 24
Peak memory 194896 kb
Host smart-fb7626d5-a99f-4c18-beee-9fab7e75a658
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631997158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.2631997158
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.3647673119
Short name T592
Test name
Test status
Simulation time 27642251 ps
CPU time 0.62 seconds
Started May 16 02:27:43 PM PDT 24
Finished May 16 02:27:50 PM PDT 24
Peak memory 194880 kb
Host smart-c1db0245-90c2-4b34-8478-aa6cb9945e3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647673119 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.3647673119
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.4187944274
Short name T540
Test name
Test status
Simulation time 18553247 ps
CPU time 0.62 seconds
Started May 16 02:27:43 PM PDT 24
Finished May 16 02:27:50 PM PDT 24
Peak memory 194912 kb
Host smart-d91a3a1f-e1fa-48ae-bd49-f37924af7235
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187944274 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.4187944274
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.1719433386
Short name T501
Test name
Test status
Simulation time 18383017 ps
CPU time 0.64 seconds
Started May 16 02:27:45 PM PDT 24
Finished May 16 02:27:51 PM PDT 24
Peak memory 194964 kb
Host smart-d7e29975-0feb-4b0d-b831-5d81083d6cf3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719433386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.1719433386
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.2487735891
Short name T604
Test name
Test status
Simulation time 60534074 ps
CPU time 0.61 seconds
Started May 16 02:27:44 PM PDT 24
Finished May 16 02:27:50 PM PDT 24
Peak memory 194844 kb
Host smart-79ba0394-c585-47ed-951b-412dd4c4074f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487735891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.2487735891
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.3842682604
Short name T103
Test name
Test status
Simulation time 622477474 ps
CPU time 8.53 seconds
Started May 16 02:27:02 PM PDT 24
Finished May 16 02:27:15 PM PDT 24
Peak memory 199984 kb
Host smart-a209f4ae-ce8b-404d-910f-07f8b008d063
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842682604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.3842682604
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.317288852
Short name T100
Test name
Test status
Simulation time 797966466 ps
CPU time 9.89 seconds
Started May 16 02:27:07 PM PDT 24
Finished May 16 02:27:21 PM PDT 24
Peak memory 199996 kb
Host smart-388dac6f-8551-474e-9758-a6e326ccdf00
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317288852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.317288852
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.3654778063
Short name T96
Test name
Test status
Simulation time 47199774 ps
CPU time 0.76 seconds
Started May 16 02:27:02 PM PDT 24
Finished May 16 02:27:06 PM PDT 24
Peak memory 197788 kb
Host smart-c9901288-11d2-48c9-8276-61e8c6810d6e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654778063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.3654778063
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.2102856736
Short name T544
Test name
Test status
Simulation time 44061864 ps
CPU time 1.22 seconds
Started May 16 02:27:03 PM PDT 24
Finished May 16 02:27:08 PM PDT 24
Peak memory 199808 kb
Host smart-3373f142-d155-49c2-8a1a-97e6282d4474
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102856736 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.2102856736
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.1582347288
Short name T104
Test name
Test status
Simulation time 36888807 ps
CPU time 0.75 seconds
Started May 16 02:27:08 PM PDT 24
Finished May 16 02:27:12 PM PDT 24
Peak memory 198164 kb
Host smart-3f3ad833-f0c0-46b8-8005-7ab695b2e722
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582347288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.1582347288
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.62312872
Short name T522
Test name
Test status
Simulation time 43341650 ps
CPU time 0.62 seconds
Started May 16 02:27:05 PM PDT 24
Finished May 16 02:27:10 PM PDT 24
Peak memory 194888 kb
Host smart-82d8e3bc-5d54-441e-b0ad-f54268fca35f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62312872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.62312872
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.4218707621
Short name T526
Test name
Test status
Simulation time 22190758 ps
CPU time 1.02 seconds
Started May 16 02:27:04 PM PDT 24
Finished May 16 02:27:09 PM PDT 24
Peak memory 199748 kb
Host smart-4d0c0f33-ab50-4690-9462-14b1edda0caa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218707621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.4218707621
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.3083452539
Short name T589
Test name
Test status
Simulation time 338459820 ps
CPU time 3.37 seconds
Started May 16 02:27:04 PM PDT 24
Finished May 16 02:27:12 PM PDT 24
Peak memory 200044 kb
Host smart-1eacb29e-1be8-4e2c-847c-462773e7ccaf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083452539 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.3083452539
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.3294406969
Short name T550
Test name
Test status
Simulation time 211066592 ps
CPU time 2.02 seconds
Started May 16 02:27:05 PM PDT 24
Finished May 16 02:27:11 PM PDT 24
Peak memory 200032 kb
Host smart-b75aeab5-06fb-4a09-8720-ecf9b1674098
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294406969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.3294406969
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.2450698724
Short name T571
Test name
Test status
Simulation time 50230948 ps
CPU time 0.6 seconds
Started May 16 02:27:44 PM PDT 24
Finished May 16 02:27:51 PM PDT 24
Peak memory 194852 kb
Host smart-a8f7629e-47ba-4735-9fb3-e0695248e922
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450698724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.2450698724
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.2928948748
Short name T593
Test name
Test status
Simulation time 198028222 ps
CPU time 0.6 seconds
Started May 16 02:27:42 PM PDT 24
Finished May 16 02:27:48 PM PDT 24
Peak memory 194884 kb
Host smart-d2f01603-627e-450a-8913-babfca3e4710
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928948748 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.2928948748
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.550831224
Short name T507
Test name
Test status
Simulation time 45675598 ps
CPU time 0.63 seconds
Started May 16 02:27:42 PM PDT 24
Finished May 16 02:27:48 PM PDT 24
Peak memory 194908 kb
Host smart-fc1fc86f-6a5e-4261-bfb3-6ad0b3843eb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550831224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.550831224
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.3435401974
Short name T552
Test name
Test status
Simulation time 16440987 ps
CPU time 0.62 seconds
Started May 16 02:27:41 PM PDT 24
Finished May 16 02:27:47 PM PDT 24
Peak memory 194936 kb
Host smart-a65a21a9-fd17-4d2a-b44b-5385e70d221d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435401974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.3435401974
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.4007273894
Short name T482
Test name
Test status
Simulation time 21118529 ps
CPU time 0.63 seconds
Started May 16 02:27:46 PM PDT 24
Finished May 16 02:27:52 PM PDT 24
Peak memory 194932 kb
Host smart-2857229c-cffa-45ec-94d8-cf5eaeaa3f96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007273894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.4007273894
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.302128684
Short name T489
Test name
Test status
Simulation time 24219362 ps
CPU time 0.62 seconds
Started May 16 02:27:42 PM PDT 24
Finished May 16 02:27:48 PM PDT 24
Peak memory 194876 kb
Host smart-0ec1ad5c-f1dd-4e69-a940-4aa3b4f261ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302128684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.302128684
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.1759190396
Short name T481
Test name
Test status
Simulation time 46592557 ps
CPU time 0.64 seconds
Started May 16 02:27:44 PM PDT 24
Finished May 16 02:27:50 PM PDT 24
Peak memory 194900 kb
Host smart-006b6a39-e8ab-4f37-8d27-5d11ba5734b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759190396 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.1759190396
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.3008802776
Short name T495
Test name
Test status
Simulation time 45687546 ps
CPU time 0.57 seconds
Started May 16 02:27:43 PM PDT 24
Finished May 16 02:27:49 PM PDT 24
Peak memory 194868 kb
Host smart-30795adc-3208-4929-b908-ebb238c1d9c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008802776 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.3008802776
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.3392711662
Short name T555
Test name
Test status
Simulation time 191770646 ps
CPU time 0.62 seconds
Started May 16 02:27:42 PM PDT 24
Finished May 16 02:27:49 PM PDT 24
Peak memory 194912 kb
Host smart-c0af0bbc-fd45-4c5e-bb43-bed046b50867
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392711662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.3392711662
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.1266835932
Short name T69
Test name
Test status
Simulation time 43139058 ps
CPU time 0.6 seconds
Started May 16 02:27:44 PM PDT 24
Finished May 16 02:27:51 PM PDT 24
Peak memory 195004 kb
Host smart-5faef9ab-8b48-4b02-bf27-5bcbef7ea39d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266835932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.1266835932
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.1768860434
Short name T97
Test name
Test status
Simulation time 105767894 ps
CPU time 5.64 seconds
Started May 16 02:27:15 PM PDT 24
Finished May 16 02:27:25 PM PDT 24
Peak memory 199960 kb
Host smart-e7652489-8b15-42a0-997b-9f0fb10f9944
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768860434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.1768860434
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.2746266386
Short name T574
Test name
Test status
Simulation time 4375910730 ps
CPU time 16.41 seconds
Started May 16 02:27:13 PM PDT 24
Finished May 16 02:27:32 PM PDT 24
Peak memory 200048 kb
Host smart-68777c76-891f-45e0-b0ee-f1a816c7e6fa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746266386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.2746266386
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.3677638886
Short name T479
Test name
Test status
Simulation time 86537637 ps
CPU time 0.75 seconds
Started May 16 02:27:15 PM PDT 24
Finished May 16 02:27:19 PM PDT 24
Peak memory 197804 kb
Host smart-abc8f78f-e1f3-44f2-9d83-3e5e4db8a9a4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677638886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.3677638886
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.2204633761
Short name T600
Test name
Test status
Simulation time 42383177 ps
CPU time 2.75 seconds
Started May 16 02:27:14 PM PDT 24
Finished May 16 02:27:20 PM PDT 24
Peak memory 216484 kb
Host smart-70388568-6620-452e-92f4-2e145f3521d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204633761 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.2204633761
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.678851816
Short name T95
Test name
Test status
Simulation time 16941827 ps
CPU time 0.72 seconds
Started May 16 02:27:13 PM PDT 24
Finished May 16 02:27:17 PM PDT 24
Peak memory 197936 kb
Host smart-899d267d-a77f-431e-965f-92a7a46056da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678851816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.678851816
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.3774890996
Short name T485
Test name
Test status
Simulation time 135560679 ps
CPU time 0.59 seconds
Started May 16 02:27:13 PM PDT 24
Finished May 16 02:27:16 PM PDT 24
Peak memory 194968 kb
Host smart-4b4c5424-3945-4f5c-ba1d-1d71bcf827ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774890996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.3774890996
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.1522420377
Short name T585
Test name
Test status
Simulation time 49387520 ps
CPU time 1.16 seconds
Started May 16 02:27:13 PM PDT 24
Finished May 16 02:27:18 PM PDT 24
Peak memory 199776 kb
Host smart-094a0470-fa86-4610-a00c-f2b3be958c8a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522420377 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.1522420377
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.1882253073
Short name T525
Test name
Test status
Simulation time 3641490733 ps
CPU time 3.6 seconds
Started May 16 02:27:04 PM PDT 24
Finished May 16 02:27:12 PM PDT 24
Peak memory 200264 kb
Host smart-6ba4998a-757c-4645-859c-80dae7ca2062
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882253073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.1882253073
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.1206910608
Short name T136
Test name
Test status
Simulation time 170929464 ps
CPU time 4.01 seconds
Started May 16 02:27:15 PM PDT 24
Finished May 16 02:27:23 PM PDT 24
Peak memory 200032 kb
Host smart-d2d16a02-30c0-4d5b-8b16-06be526e31b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206910608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.1206910608
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.3501235698
Short name T591
Test name
Test status
Simulation time 13787214 ps
CPU time 0.64 seconds
Started May 16 02:27:47 PM PDT 24
Finished May 16 02:27:52 PM PDT 24
Peak memory 194932 kb
Host smart-ce9947f1-b4a7-434b-bdd2-ee79460a4228
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501235698 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.3501235698
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.470212122
Short name T577
Test name
Test status
Simulation time 14549551 ps
CPU time 0.59 seconds
Started May 16 02:27:44 PM PDT 24
Finished May 16 02:27:50 PM PDT 24
Peak memory 194852 kb
Host smart-bdc9fbbe-145f-4361-bdba-0c87c0afcbfc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470212122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.470212122
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.257323773
Short name T497
Test name
Test status
Simulation time 16196970 ps
CPU time 0.59 seconds
Started May 16 02:27:44 PM PDT 24
Finished May 16 02:27:50 PM PDT 24
Peak memory 194912 kb
Host smart-22240018-1a1b-4337-9ea2-dbd105fc4313
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257323773 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.257323773
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.2600677759
Short name T504
Test name
Test status
Simulation time 35338024 ps
CPU time 0.65 seconds
Started May 16 02:27:43 PM PDT 24
Finished May 16 02:27:50 PM PDT 24
Peak memory 195000 kb
Host smart-5cabc26c-53d9-4ab4-b8d6-be441ae74eb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600677759 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.2600677759
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.2927380803
Short name T581
Test name
Test status
Simulation time 24426322 ps
CPU time 0.63 seconds
Started May 16 02:27:42 PM PDT 24
Finished May 16 02:27:48 PM PDT 24
Peak memory 194928 kb
Host smart-bdc39ce9-2524-4fdb-8c8e-822bc0f04c38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927380803 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.2927380803
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.4123929647
Short name T529
Test name
Test status
Simulation time 48332609 ps
CPU time 0.68 seconds
Started May 16 02:27:42 PM PDT 24
Finished May 16 02:27:48 PM PDT 24
Peak memory 194940 kb
Host smart-46a16da8-064c-4371-acf0-5725f496ec8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123929647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.4123929647
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.3975723742
Short name T533
Test name
Test status
Simulation time 11583016 ps
CPU time 0.65 seconds
Started May 16 02:27:45 PM PDT 24
Finished May 16 02:27:51 PM PDT 24
Peak memory 194896 kb
Host smart-96f9d513-5266-4114-8b03-ad176764c562
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975723742 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.3975723742
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.3278336767
Short name T499
Test name
Test status
Simulation time 15276513 ps
CPU time 0.6 seconds
Started May 16 02:27:42 PM PDT 24
Finished May 16 02:27:48 PM PDT 24
Peak memory 194904 kb
Host smart-514169cf-3c30-462d-8e70-31f75a56a525
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278336767 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.3278336767
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.3975366436
Short name T546
Test name
Test status
Simulation time 21067510 ps
CPU time 0.67 seconds
Started May 16 02:27:44 PM PDT 24
Finished May 16 02:27:51 PM PDT 24
Peak memory 194956 kb
Host smart-1832aeff-7c41-44e0-815d-36696107a677
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975366436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.3975366436
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.3143134663
Short name T494
Test name
Test status
Simulation time 11666487 ps
CPU time 0.61 seconds
Started May 16 02:27:44 PM PDT 24
Finished May 16 02:27:50 PM PDT 24
Peak memory 194936 kb
Host smart-d229ffe5-85bc-4fe3-8a36-3eb13c884f30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143134663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.3143134663
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.4091476259
Short name T506
Test name
Test status
Simulation time 333744361203 ps
CPU time 681.17 seconds
Started May 16 02:27:15 PM PDT 24
Finished May 16 02:38:40 PM PDT 24
Peak memory 216424 kb
Host smart-170a9145-250c-42ff-8f7f-dbe410fd2740
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091476259 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.4091476259
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.544549854
Short name T599
Test name
Test status
Simulation time 153774577 ps
CPU time 0.8 seconds
Started May 16 02:27:13 PM PDT 24
Finished May 16 02:27:18 PM PDT 24
Peak memory 199128 kb
Host smart-7226212f-100b-40a0-abc5-7c87ca2fff18
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544549854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.544549854
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.593970537
Short name T534
Test name
Test status
Simulation time 133352780 ps
CPU time 0.63 seconds
Started May 16 02:27:12 PM PDT 24
Finished May 16 02:27:15 PM PDT 24
Peak memory 194872 kb
Host smart-13d9e147-4da9-4fa1-a787-e8559f2a93f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593970537 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.593970537
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.1135746463
Short name T520
Test name
Test status
Simulation time 36100314 ps
CPU time 1.69 seconds
Started May 16 02:27:13 PM PDT 24
Finished May 16 02:27:19 PM PDT 24
Peak memory 199776 kb
Host smart-b1577149-fe53-4d1a-9da7-acfbfe15390d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135746463 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.1135746463
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.3465361513
Short name T579
Test name
Test status
Simulation time 282251041 ps
CPU time 4.03 seconds
Started May 16 02:27:14 PM PDT 24
Finished May 16 02:27:22 PM PDT 24
Peak memory 200052 kb
Host smart-113b27b5-18e8-4c17-8be8-449ecd6b1a21
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465361513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.3465361513
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.2365988673
Short name T51
Test name
Test status
Simulation time 338490941 ps
CPU time 1.81 seconds
Started May 16 02:27:14 PM PDT 24
Finished May 16 02:27:19 PM PDT 24
Peak memory 200016 kb
Host smart-d4272b4f-5d00-41d7-be18-5459e0fa4097
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365988673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.2365988673
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.1282682558
Short name T486
Test name
Test status
Simulation time 99738605 ps
CPU time 2.36 seconds
Started May 16 02:27:15 PM PDT 24
Finished May 16 02:27:21 PM PDT 24
Peak memory 200092 kb
Host smart-611f0d02-4637-4168-bd71-0f833ead0101
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282682558 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.1282682558
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.3512133863
Short name T541
Test name
Test status
Simulation time 38533891 ps
CPU time 0.76 seconds
Started May 16 02:27:15 PM PDT 24
Finished May 16 02:27:19 PM PDT 24
Peak memory 197928 kb
Host smart-f1b08945-9ef4-4df6-9327-66a4ac3aac31
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512133863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.3512133863
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.371235673
Short name T561
Test name
Test status
Simulation time 13685098 ps
CPU time 0.6 seconds
Started May 16 02:27:13 PM PDT 24
Finished May 16 02:27:17 PM PDT 24
Peak memory 194924 kb
Host smart-4c6f7346-3e84-4c7e-8695-16a6c68a4483
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371235673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.371235673
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.1916395000
Short name T524
Test name
Test status
Simulation time 115535151 ps
CPU time 2.32 seconds
Started May 16 02:27:13 PM PDT 24
Finished May 16 02:27:18 PM PDT 24
Peak memory 199844 kb
Host smart-348c6bad-93c6-4b72-8ace-cd7e0e302b5f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916395000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.1916395000
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.267952361
Short name T531
Test name
Test status
Simulation time 102862932 ps
CPU time 1.65 seconds
Started May 16 02:27:13 PM PDT 24
Finished May 16 02:27:18 PM PDT 24
Peak memory 200100 kb
Host smart-7e736187-4c67-49aa-9e52-c1aa23eac057
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267952361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.267952361
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.3494715121
Short name T129
Test name
Test status
Simulation time 121367843 ps
CPU time 3.04 seconds
Started May 16 02:27:13 PM PDT 24
Finished May 16 02:27:20 PM PDT 24
Peak memory 199992 kb
Host smart-97122d0c-127a-4a8f-8a69-4c83ad6a7cf3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494715121 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.3494715121
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.1284552611
Short name T566
Test name
Test status
Simulation time 82508085 ps
CPU time 1.32 seconds
Started May 16 02:27:13 PM PDT 24
Finished May 16 02:27:18 PM PDT 24
Peak memory 199808 kb
Host smart-51bd6fb3-e693-4009-afb5-0f4ff31acf27
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284552611 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.1284552611
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.1582011257
Short name T603
Test name
Test status
Simulation time 54333670 ps
CPU time 0.7 seconds
Started May 16 02:27:14 PM PDT 24
Finished May 16 02:27:19 PM PDT 24
Peak memory 198264 kb
Host smart-4e594fd4-7739-49b1-b2c5-62de16e38f5b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582011257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.1582011257
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.2625950609
Short name T563
Test name
Test status
Simulation time 36676330 ps
CPU time 0.59 seconds
Started May 16 02:27:14 PM PDT 24
Finished May 16 02:27:18 PM PDT 24
Peak memory 194964 kb
Host smart-3db18e1f-6754-4fb6-a5f6-2e263e9b785e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625950609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.2625950609
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.2327870399
Short name T519
Test name
Test status
Simulation time 37407881 ps
CPU time 1.7 seconds
Started May 16 02:27:13 PM PDT 24
Finished May 16 02:27:18 PM PDT 24
Peak memory 199972 kb
Host smart-991b12cd-5341-487f-aab6-a318fa532d61
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327870399 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.2327870399
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.710343474
Short name T503
Test name
Test status
Simulation time 223016337 ps
CPU time 3.14 seconds
Started May 16 02:27:12 PM PDT 24
Finished May 16 02:27:18 PM PDT 24
Peak memory 200080 kb
Host smart-bd1b6e22-f491-4edb-beff-8ee559108125
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710343474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.710343474
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.526511493
Short name T134
Test name
Test status
Simulation time 62202852 ps
CPU time 1.87 seconds
Started May 16 02:27:14 PM PDT 24
Finished May 16 02:27:20 PM PDT 24
Peak memory 200012 kb
Host smart-5e972491-b6bb-486d-973a-4a8ba8af38fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526511493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.526511493
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.1838644055
Short name T59
Test name
Test status
Simulation time 98013438 ps
CPU time 1.52 seconds
Started May 16 02:27:21 PM PDT 24
Finished May 16 02:27:24 PM PDT 24
Peak memory 199944 kb
Host smart-95be2c6a-ff49-44b6-bbeb-5b27b478e15e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838644055 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.1838644055
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.145057791
Short name T99
Test name
Test status
Simulation time 63324156 ps
CPU time 0.89 seconds
Started May 16 02:27:25 PM PDT 24
Finished May 16 02:27:30 PM PDT 24
Peak memory 199076 kb
Host smart-d48f3d49-4413-48a2-bf62-d1321537998c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145057791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.145057791
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.4087432822
Short name T496
Test name
Test status
Simulation time 14580383 ps
CPU time 0.59 seconds
Started May 16 02:27:24 PM PDT 24
Finished May 16 02:27:29 PM PDT 24
Peak memory 194880 kb
Host smart-d61456c2-b594-4b95-9e3a-4d3612a6589b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087432822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.4087432822
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.586440897
Short name T542
Test name
Test status
Simulation time 183233219 ps
CPU time 1.11 seconds
Started May 16 02:27:23 PM PDT 24
Finished May 16 02:27:28 PM PDT 24
Peak memory 200088 kb
Host smart-45a9cbb5-47b9-49be-b797-bc1d522e5d33
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586440897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr_
outstanding.586440897
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.3517877510
Short name T493
Test name
Test status
Simulation time 171848277 ps
CPU time 1.71 seconds
Started May 16 02:27:12 PM PDT 24
Finished May 16 02:27:17 PM PDT 24
Peak memory 200120 kb
Host smart-76f6dc29-7f1d-487e-900d-9354cbccfc62
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517877510 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.3517877510
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.1474687924
Short name T549
Test name
Test status
Simulation time 47513265 ps
CPU time 1.52 seconds
Started May 16 02:27:24 PM PDT 24
Finished May 16 02:27:30 PM PDT 24
Peak memory 199916 kb
Host smart-3e3c05dc-b505-4294-bd7b-2f9340c6bb89
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474687924 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.1474687924
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.862380933
Short name T590
Test name
Test status
Simulation time 62197129 ps
CPU time 0.98 seconds
Started May 16 02:27:24 PM PDT 24
Finished May 16 02:27:30 PM PDT 24
Peak memory 199580 kb
Host smart-9af85b99-0307-49b6-9b64-c69c0dbe24df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862380933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.862380933
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.371697623
Short name T572
Test name
Test status
Simulation time 11532449 ps
CPU time 0.57 seconds
Started May 16 02:27:21 PM PDT 24
Finished May 16 02:27:24 PM PDT 24
Peak memory 194920 kb
Host smart-ed56529a-edf9-4ddb-b67d-9b2d1d89208d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371697623 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.371697623
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.3236146852
Short name T517
Test name
Test status
Simulation time 91558699 ps
CPU time 1.11 seconds
Started May 16 02:27:24 PM PDT 24
Finished May 16 02:27:29 PM PDT 24
Peak memory 200008 kb
Host smart-f2ddaf53-4992-4620-879a-bc062e4cbb24
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236146852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.3236146852
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.557383792
Short name T81
Test name
Test status
Simulation time 53319133 ps
CPU time 2.82 seconds
Started May 16 02:27:26 PM PDT 24
Finished May 16 02:27:34 PM PDT 24
Peak memory 200056 kb
Host smart-ff0fb462-cea9-4b3f-af85-f0aff40d8bb6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557383792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.557383792
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.2845406815
Short name T133
Test name
Test status
Simulation time 505006256 ps
CPU time 3.14 seconds
Started May 16 02:27:25 PM PDT 24
Finished May 16 02:27:32 PM PDT 24
Peak memory 200008 kb
Host smart-52194eb9-189a-441d-a0eb-6b39b44e439a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845406815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.2845406815
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.2542422100
Short name T417
Test name
Test status
Simulation time 82556799 ps
CPU time 0.63 seconds
Started May 16 02:28:28 PM PDT 24
Finished May 16 02:28:30 PM PDT 24
Peak memory 196092 kb
Host smart-ccb53b6b-5093-4324-8bd0-3b6259bae8e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542422100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.2542422100
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.2040927963
Short name T290
Test name
Test status
Simulation time 288574287 ps
CPU time 17.54 seconds
Started May 16 02:28:33 PM PDT 24
Finished May 16 02:28:54 PM PDT 24
Peak memory 223240 kb
Host smart-c2061da3-8ecc-4b6d-87d2-a5c3e9c097e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2040927963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.2040927963
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.2433041989
Short name T121
Test name
Test status
Simulation time 9256822217 ps
CPU time 46.57 seconds
Started May 16 02:28:30 PM PDT 24
Finished May 16 02:29:21 PM PDT 24
Peak memory 200768 kb
Host smart-ef415106-51b6-4c94-b2a6-a8175ab65b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433041989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.2433041989
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.902160632
Short name T418
Test name
Test status
Simulation time 11857877013 ps
CPU time 756.06 seconds
Started May 16 02:28:29 PM PDT 24
Finished May 16 02:41:07 PM PDT 24
Peak memory 727788 kb
Host smart-054b31c0-a332-4550-a74e-063f1eafb112
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=902160632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.902160632
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_long_msg.139981077
Short name T310
Test name
Test status
Simulation time 3485031649 ps
CPU time 23.88 seconds
Started May 16 02:28:33 PM PDT 24
Finished May 16 02:29:00 PM PDT 24
Peak memory 200652 kb
Host smart-12075cd1-2d4a-4dc3-8cc0-c7958e2d8e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139981077 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.139981077
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.3965153916
Short name T40
Test name
Test status
Simulation time 157377548 ps
CPU time 0.99 seconds
Started May 16 02:28:28 PM PDT 24
Finished May 16 02:28:31 PM PDT 24
Peak memory 219892 kb
Host smart-0008398d-571b-40d7-a944-707be2e6e2c4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965153916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.3965153916
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/0.hmac_smoke.1666231589
Short name T208
Test name
Test status
Simulation time 484150011 ps
CPU time 6.65 seconds
Started May 16 02:28:28 PM PDT 24
Finished May 16 02:28:37 PM PDT 24
Peak memory 200500 kb
Host smart-eb31b2a4-0868-447c-9ed1-984d27d59051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666231589 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.1666231589
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_test_hmac_vectors.2150965343
Short name T88
Test name
Test status
Simulation time 51203798 ps
CPU time 1.08 seconds
Started May 16 02:28:28 PM PDT 24
Finished May 16 02:28:31 PM PDT 24
Peak memory 199984 kb
Host smart-692b50d4-c676-4393-8c1d-a3f77227ceb6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150965343 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.hmac_test_hmac_vectors.2150965343
Directory /workspace/0.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha_vectors.4229195516
Short name T162
Test name
Test status
Simulation time 42628490594 ps
CPU time 539.59 seconds
Started May 16 02:28:28 PM PDT 24
Finished May 16 02:37:29 PM PDT 24
Peak memory 200720 kb
Host smart-4b5bc831-5ba3-44cf-aae4-2b35ede204ee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229195516 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha_vectors.4229195516
Directory /workspace/0.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/1.hmac_alert_test.2474509303
Short name T444
Test name
Test status
Simulation time 14206375 ps
CPU time 0.64 seconds
Started May 16 02:28:30 PM PDT 24
Finished May 16 02:28:35 PM PDT 24
Peak memory 197096 kb
Host smart-462cf323-16f5-4a77-9459-91590f85be91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474509303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.2474509303
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.38265063
Short name T334
Test name
Test status
Simulation time 6618819336 ps
CPU time 64.63 seconds
Started May 16 02:28:30 PM PDT 24
Finished May 16 02:29:39 PM PDT 24
Peak memory 248864 kb
Host smart-0b3a90e5-00a5-441c-b630-be56193ac50c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=38265063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.38265063
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.1248606613
Short name T120
Test name
Test status
Simulation time 3354998566 ps
CPU time 45.02 seconds
Started May 16 02:28:33 PM PDT 24
Finished May 16 02:29:22 PM PDT 24
Peak memory 200748 kb
Host smart-79943ae1-dc2c-4621-8034-675278c29685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248606613 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.1248606613
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.1950146604
Short name T277
Test name
Test status
Simulation time 176993925 ps
CPU time 31.58 seconds
Started May 16 02:28:30 PM PDT 24
Finished May 16 02:29:06 PM PDT 24
Peak memory 309320 kb
Host smart-5dc4cf47-621e-4a37-a1ca-a6a36a4f55f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1950146604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.1950146604
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_long_msg.1136929420
Short name T148
Test name
Test status
Simulation time 17558955391 ps
CPU time 85.63 seconds
Started May 16 02:28:31 PM PDT 24
Finished May 16 02:30:01 PM PDT 24
Peak memory 200756 kb
Host smart-0fcd61b5-59d7-4088-b55a-b28266eea680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136929420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.1136929420
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_smoke.1061420885
Short name T387
Test name
Test status
Simulation time 426037216 ps
CPU time 2.02 seconds
Started May 16 02:28:29 PM PDT 24
Finished May 16 02:28:34 PM PDT 24
Peak memory 200640 kb
Host smart-3628afb8-bb43-4b38-8bc6-d94ea5085f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061420885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.1061420885
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.937833788
Short name T53
Test name
Test status
Simulation time 79312671012 ps
CPU time 1046.05 seconds
Started May 16 02:28:31 PM PDT 24
Finished May 16 02:46:01 PM PDT 24
Peak memory 200688 kb
Host smart-c4f5f976-c473-4467-82e0-64b49f1ae21b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937833788 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.937833788
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_test_hmac_vectors.2627007827
Short name T149
Test name
Test status
Simulation time 39522028 ps
CPU time 1.06 seconds
Started May 16 02:28:30 PM PDT 24
Finished May 16 02:28:34 PM PDT 24
Peak memory 199348 kb
Host smart-3ee0d4e4-31d1-474a-beb4-2f11e607b65e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627007827 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.hmac_test_hmac_vectors.2627007827
Directory /workspace/1.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha_vectors.618183237
Short name T380
Test name
Test status
Simulation time 91934173096 ps
CPU time 485.2 seconds
Started May 16 02:28:33 PM PDT 24
Finished May 16 02:36:42 PM PDT 24
Peak memory 200688 kb
Host smart-90ff9060-6b68-43b6-8310-5833f9ddd9d5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618183237 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha_vectors.618183237
Directory /workspace/1.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/10.hmac_alert_test.3411929566
Short name T236
Test name
Test status
Simulation time 11674039 ps
CPU time 0.58 seconds
Started May 16 02:28:57 PM PDT 24
Finished May 16 02:29:03 PM PDT 24
Peak memory 196032 kb
Host smart-71f56224-9cc6-40f6-9337-949c53438d19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411929566 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.3411929566
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.4229422810
Short name T233
Test name
Test status
Simulation time 799901917 ps
CPU time 28.49 seconds
Started May 16 02:28:55 PM PDT 24
Finished May 16 02:29:26 PM PDT 24
Peak memory 233356 kb
Host smart-e6011b6c-7c2d-4627-83d1-aecc97f789cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4229422810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.4229422810
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.1384174016
Short name T230
Test name
Test status
Simulation time 496230598 ps
CPU time 9.88 seconds
Started May 16 02:28:57 PM PDT 24
Finished May 16 02:29:12 PM PDT 24
Peak memory 200592 kb
Host smart-e7804fad-2151-492a-adac-56bed5b83bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384174016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.1384174016
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.2186319552
Short name T441
Test name
Test status
Simulation time 56178835812 ps
CPU time 1340.66 seconds
Started May 16 02:28:55 PM PDT 24
Finished May 16 02:51:19 PM PDT 24
Peak memory 775308 kb
Host smart-b7b8a240-9423-4336-8e3c-27f3c09f8b9e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2186319552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.2186319552
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_long_msg.2173446020
Short name T295
Test name
Test status
Simulation time 1087335429 ps
CPU time 55.89 seconds
Started May 16 02:28:55 PM PDT 24
Finished May 16 02:29:54 PM PDT 24
Peak memory 200692 kb
Host smart-6b46cc88-0d3c-423d-845a-ba3971021bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173446020 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.2173446020
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.1445976474
Short name T392
Test name
Test status
Simulation time 1145095029 ps
CPU time 3.37 seconds
Started May 16 02:28:56 PM PDT 24
Finished May 16 02:29:04 PM PDT 24
Peak memory 200548 kb
Host smart-64b5f52c-9cfe-43af-8430-3db8e3c8e98d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445976474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.1445976474
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_test_hmac_vectors.1446072101
Short name T404
Test name
Test status
Simulation time 128537313 ps
CPU time 1.19 seconds
Started May 16 02:28:54 PM PDT 24
Finished May 16 02:28:59 PM PDT 24
Peak memory 200560 kb
Host smart-299dc2c6-e9ff-4a85-9e1f-e441fb6e3657
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446072101 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.hmac_test_hmac_vectors.1446072101
Directory /workspace/10.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha_vectors.3398351448
Short name T154
Test name
Test status
Simulation time 40627063690 ps
CPU time 532.17 seconds
Started May 16 02:28:59 PM PDT 24
Finished May 16 02:37:57 PM PDT 24
Peak memory 200656 kb
Host smart-b3e28bd5-93d7-469d-b200-d1019d4f7a7d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398351448 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_sha_vectors.3398351448
Directory /workspace/10.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/11.hmac_alert_test.2542574898
Short name T62
Test name
Test status
Simulation time 43643297 ps
CPU time 0.58 seconds
Started May 16 02:28:57 PM PDT 24
Finished May 16 02:29:03 PM PDT 24
Peak memory 196084 kb
Host smart-fcf7f7aa-9567-4100-9742-b6939c315a81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542574898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.2542574898
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.850459980
Short name T73
Test name
Test status
Simulation time 729236743 ps
CPU time 24.01 seconds
Started May 16 02:28:54 PM PDT 24
Finished May 16 02:29:21 PM PDT 24
Peak memory 223980 kb
Host smart-809d5062-6ed0-495a-93c5-e61d93304cbb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=850459980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.850459980
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.35346923
Short name T288
Test name
Test status
Simulation time 8041193337 ps
CPU time 34.08 seconds
Started May 16 02:28:56 PM PDT 24
Finished May 16 02:29:36 PM PDT 24
Peak memory 200688 kb
Host smart-be902ef0-05f3-4bba-b92d-968b50637dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35346923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.35346923
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.3114949244
Short name T158
Test name
Test status
Simulation time 27104091683 ps
CPU time 645.53 seconds
Started May 16 02:28:56 PM PDT 24
Finished May 16 02:39:46 PM PDT 24
Peak memory 463796 kb
Host smart-0c540418-5e33-4916-b586-fee4085ee5cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3114949244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.3114949244
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.3631672694
Short name T42
Test name
Test status
Simulation time 129599455 ps
CPU time 6.84 seconds
Started May 16 02:28:56 PM PDT 24
Finished May 16 02:29:07 PM PDT 24
Peak memory 200472 kb
Host smart-21aec3f4-b29b-4011-9ba3-2ef67e94a3f2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631672694 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.3631672694
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.3383348335
Short name T429
Test name
Test status
Simulation time 6770753710 ps
CPU time 88.68 seconds
Started May 16 02:28:59 PM PDT 24
Finished May 16 02:30:34 PM PDT 24
Peak memory 200732 kb
Host smart-e66fc0cf-5e0b-4f1d-a3df-a9bb9970aaea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383348335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.3383348335
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.2206994080
Short name T43
Test name
Test status
Simulation time 170166120 ps
CPU time 3.84 seconds
Started May 16 02:28:56 PM PDT 24
Finished May 16 02:29:04 PM PDT 24
Peak memory 200644 kb
Host smart-83e9fe87-1540-41c5-8b29-8bf08f2434a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206994080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.2206994080
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_test_hmac_vectors.2553573665
Short name T294
Test name
Test status
Simulation time 69488487 ps
CPU time 1.35 seconds
Started May 16 02:28:56 PM PDT 24
Finished May 16 02:29:01 PM PDT 24
Peak memory 200620 kb
Host smart-51e69468-3267-45bd-94d9-1a4a13ba6f56
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553573665 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.hmac_test_hmac_vectors.2553573665
Directory /workspace/11.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha_vectors.2678028048
Short name T360
Test name
Test status
Simulation time 221037381784 ps
CPU time 519.11 seconds
Started May 16 02:28:59 PM PDT 24
Finished May 16 02:37:45 PM PDT 24
Peak memory 200696 kb
Host smart-e27ab4fc-6d48-4f50-925b-6c40c557a6b5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678028048 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_sha_vectors.2678028048
Directory /workspace/11.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/12.hmac_alert_test.269286260
Short name T80
Test name
Test status
Simulation time 45919464 ps
CPU time 0.58 seconds
Started May 16 02:28:59 PM PDT 24
Finished May 16 02:29:05 PM PDT 24
Peak memory 196412 kb
Host smart-a444c652-610c-4c4f-a425-e9bb7dcb5f63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269286260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.269286260
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.1780934409
Short name T416
Test name
Test status
Simulation time 2012419536 ps
CPU time 53.86 seconds
Started May 16 02:28:59 PM PDT 24
Finished May 16 02:29:58 PM PDT 24
Peak memory 225212 kb
Host smart-676c822c-a7e8-4dcd-96de-ef4bc1b6cc11
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1780934409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.1780934409
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.3739393693
Short name T304
Test name
Test status
Simulation time 4431761977 ps
CPU time 62.19 seconds
Started May 16 02:28:53 PM PDT 24
Finished May 16 02:29:58 PM PDT 24
Peak memory 200624 kb
Host smart-2271b1f9-ab86-456d-a2af-c40e2227d281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739393693 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.3739393693
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.694653030
Short name T165
Test name
Test status
Simulation time 3134640186 ps
CPU time 237.9 seconds
Started May 16 02:28:59 PM PDT 24
Finished May 16 02:33:02 PM PDT 24
Peak memory 667184 kb
Host smart-a97d8515-8f51-4a0f-a4ca-5a8cc94acafa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=694653030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.694653030
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_long_msg.1194513860
Short name T268
Test name
Test status
Simulation time 5001900743 ps
CPU time 67.3 seconds
Started May 16 02:28:58 PM PDT 24
Finished May 16 02:30:11 PM PDT 24
Peak memory 200712 kb
Host smart-b2c1e0aa-9a49-4fa4-a6a4-23bfe2217db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194513860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.1194513860
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.2505561505
Short name T198
Test name
Test status
Simulation time 2134766534 ps
CPU time 4.67 seconds
Started May 16 02:28:57 PM PDT 24
Finished May 16 02:29:07 PM PDT 24
Peak memory 200612 kb
Host smart-43879ac0-0113-4d95-ac7a-6fb34873443a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505561505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.2505561505
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.1414359783
Short name T31
Test name
Test status
Simulation time 384566767 ps
CPU time 3.41 seconds
Started May 16 02:28:58 PM PDT 24
Finished May 16 02:29:06 PM PDT 24
Peak memory 200604 kb
Host smart-316b1628-d065-45e2-93eb-4bc2ca82c1c1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414359783 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.1414359783
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_test_hmac_vectors.3424269597
Short name T383
Test name
Test status
Simulation time 100725102 ps
CPU time 1.02 seconds
Started May 16 02:28:57 PM PDT 24
Finished May 16 02:29:04 PM PDT 24
Peak memory 199484 kb
Host smart-761890ed-db54-4403-a804-217bca944800
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424269597 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.hmac_test_hmac_vectors.3424269597
Directory /workspace/12.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha_vectors.1371237627
Short name T322
Test name
Test status
Simulation time 218572287177 ps
CPU time 502.37 seconds
Started May 16 02:28:59 PM PDT 24
Finished May 16 02:37:28 PM PDT 24
Peak memory 200740 kb
Host smart-9034c80f-4467-4405-987d-8c9f90dfcef4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371237627 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_sha_vectors.1371237627
Directory /workspace/12.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/13.hmac_alert_test.1328618154
Short name T163
Test name
Test status
Simulation time 10863972 ps
CPU time 0.59 seconds
Started May 16 02:28:59 PM PDT 24
Finished May 16 02:29:06 PM PDT 24
Peak memory 195252 kb
Host smart-1b371ddf-625b-49f4-8ebb-309925640b50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328618154 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.1328618154
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.139827733
Short name T292
Test name
Test status
Simulation time 420550305 ps
CPU time 25.45 seconds
Started May 16 02:28:59 PM PDT 24
Finished May 16 02:29:30 PM PDT 24
Peak memory 225632 kb
Host smart-bd7384cc-683e-49de-bcd6-5a245fc17795
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=139827733 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.139827733
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.2819006017
Short name T363
Test name
Test status
Simulation time 1764941029 ps
CPU time 47.6 seconds
Started May 16 02:28:59 PM PDT 24
Finished May 16 02:29:53 PM PDT 24
Peak memory 200636 kb
Host smart-b8511c5e-5f59-4fd2-9396-c57afd6bdf18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819006017 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.2819006017
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.1053943159
Short name T109
Test name
Test status
Simulation time 2120906278 ps
CPU time 511.1 seconds
Started May 16 02:28:59 PM PDT 24
Finished May 16 02:37:36 PM PDT 24
Peak memory 696708 kb
Host smart-a98c0b01-bb3d-4b02-b933-2400e852fcba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1053943159 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.1053943159
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_long_msg.602373798
Short name T325
Test name
Test status
Simulation time 935426250 ps
CPU time 53.19 seconds
Started May 16 02:28:59 PM PDT 24
Finished May 16 02:29:58 PM PDT 24
Peak memory 200620 kb
Host smart-836cafdf-98aa-4db4-a5f9-384b98bc599f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602373798 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.602373798
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.2428121948
Short name T413
Test name
Test status
Simulation time 1762104856 ps
CPU time 4.71 seconds
Started May 16 02:28:58 PM PDT 24
Finished May 16 02:29:08 PM PDT 24
Peak memory 200620 kb
Host smart-fd631fd2-2f9a-48b0-9acb-4b40278773a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428121948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.2428121948
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_test_hmac_vectors.197064131
Short name T216
Test name
Test status
Simulation time 108605624 ps
CPU time 1.07 seconds
Started May 16 02:29:00 PM PDT 24
Finished May 16 02:29:07 PM PDT 24
Peak memory 200168 kb
Host smart-e6562f46-a65d-45ab-9d18-8ef4c83405e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197064131 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.hmac_test_hmac_vectors.197064131
Directory /workspace/13.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha_vectors.585514003
Short name T299
Test name
Test status
Simulation time 163429577599 ps
CPU time 548.69 seconds
Started May 16 02:28:54 PM PDT 24
Finished May 16 02:38:05 PM PDT 24
Peak memory 200660 kb
Host smart-a8bb81f9-3784-4383-9fd2-1afb7b8ad22d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585514003 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_sha_vectors.585514003
Directory /workspace/13.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/14.hmac_alert_test.1124911311
Short name T207
Test name
Test status
Simulation time 54751887 ps
CPU time 0.62 seconds
Started May 16 02:29:08 PM PDT 24
Finished May 16 02:29:13 PM PDT 24
Peak memory 196368 kb
Host smart-4757800d-f135-47da-b948-2f103211b038
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124911311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.1124911311
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.1574957451
Short name T462
Test name
Test status
Simulation time 4123928044 ps
CPU time 26.02 seconds
Started May 16 02:29:00 PM PDT 24
Finished May 16 02:29:32 PM PDT 24
Peak memory 227388 kb
Host smart-fd46c5c6-3e61-4bb0-a9db-e0b9538e788d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1574957451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.1574957451
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.1498623423
Short name T114
Test name
Test status
Simulation time 15107912352 ps
CPU time 27.15 seconds
Started May 16 02:29:01 PM PDT 24
Finished May 16 02:29:33 PM PDT 24
Peak memory 200732 kb
Host smart-958d2c2d-06ef-4a0b-8873-197aa1b2732d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498623423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.1498623423
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_smoke.3758189863
Short name T289
Test name
Test status
Simulation time 1029777225 ps
CPU time 4.43 seconds
Started May 16 02:29:00 PM PDT 24
Finished May 16 02:29:10 PM PDT 24
Peak memory 200644 kb
Host smart-2c12bb0d-7f5b-403d-a741-0fac753db2cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758189863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.3758189863
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_test_hmac_vectors.3265640387
Short name T339
Test name
Test status
Simulation time 29512862 ps
CPU time 1.03 seconds
Started May 16 02:29:01 PM PDT 24
Finished May 16 02:29:07 PM PDT 24
Peak memory 200112 kb
Host smart-d513b63c-6921-434d-99e5-e7090ffd8154
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265640387 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.hmac_test_hmac_vectors.3265640387
Directory /workspace/14.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha_vectors.1401721483
Short name T316
Test name
Test status
Simulation time 704912078658 ps
CPU time 518.45 seconds
Started May 16 02:28:55 PM PDT 24
Finished May 16 02:37:36 PM PDT 24
Peak memory 200636 kb
Host smart-e04c4181-e340-4873-b050-d0e93cc0b8e1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401721483 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_sha_vectors.1401721483
Directory /workspace/14.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/15.hmac_alert_test.3713712816
Short name T265
Test name
Test status
Simulation time 20543503 ps
CPU time 0.59 seconds
Started May 16 02:29:05 PM PDT 24
Finished May 16 02:29:09 PM PDT 24
Peak memory 197112 kb
Host smart-161be97c-4574-4c2c-9f3f-12e83cfaa93e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713712816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.3713712816
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.1077934594
Short name T204
Test name
Test status
Simulation time 833224656 ps
CPU time 49.05 seconds
Started May 16 02:29:08 PM PDT 24
Finished May 16 02:30:01 PM PDT 24
Peak memory 232872 kb
Host smart-da157616-6b54-457f-b5c2-90bd6a73e95a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1077934594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.1077934594
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.2087820033
Short name T119
Test name
Test status
Simulation time 28082661159 ps
CPU time 43.88 seconds
Started May 16 02:29:05 PM PDT 24
Finished May 16 02:29:53 PM PDT 24
Peak memory 200844 kb
Host smart-ca8ca692-3602-48ed-90cc-bd7941261798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087820033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.2087820033
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.1105126966
Short name T303
Test name
Test status
Simulation time 4455528013 ps
CPU time 1361 seconds
Started May 16 02:29:07 PM PDT 24
Finished May 16 02:51:52 PM PDT 24
Peak memory 767260 kb
Host smart-63d9bf37-f8a2-4d2b-a7d4-50a10a92d49a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1105126966 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.1105126966
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_long_msg.821283991
Short name T247
Test name
Test status
Simulation time 3086362106 ps
CPU time 64.93 seconds
Started May 16 02:29:09 PM PDT 24
Finished May 16 02:30:18 PM PDT 24
Peak memory 200664 kb
Host smart-a2a4e769-d8ea-4ea7-b3b7-b9df393aeec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821283991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.821283991
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.372922011
Short name T238
Test name
Test status
Simulation time 51533438 ps
CPU time 0.69 seconds
Started May 16 02:29:07 PM PDT 24
Finished May 16 02:29:11 PM PDT 24
Peak memory 198020 kb
Host smart-a93d6baa-507c-44b9-82d0-b6dbec47f92f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372922011 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.372922011
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_test_hmac_vectors.764095678
Short name T153
Test name
Test status
Simulation time 32455740 ps
CPU time 1.23 seconds
Started May 16 02:29:05 PM PDT 24
Finished May 16 02:29:10 PM PDT 24
Peak memory 200560 kb
Host smart-282c20de-bf27-4ca5-b81a-208c658bfbb4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764095678 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 15.hmac_test_hmac_vectors.764095678
Directory /workspace/15.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha_vectors.70095729
Short name T411
Test name
Test status
Simulation time 56075030187 ps
CPU time 544.96 seconds
Started May 16 02:29:08 PM PDT 24
Finished May 16 02:38:17 PM PDT 24
Peak memory 200628 kb
Host smart-72b4a90a-3c9b-45bf-8b95-db4caafa3b5a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70095729 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_sha_vectors.70095729
Directory /workspace/15.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/16.hmac_alert_test.289637222
Short name T353
Test name
Test status
Simulation time 29482018 ps
CPU time 0.62 seconds
Started May 16 02:29:05 PM PDT 24
Finished May 16 02:29:09 PM PDT 24
Peak memory 196392 kb
Host smart-baea0e07-aa53-4e4b-8919-5f7c5b87c132
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289637222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.289637222
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.3461270397
Short name T345
Test name
Test status
Simulation time 3479834730 ps
CPU time 34.54 seconds
Started May 16 02:29:09 PM PDT 24
Finished May 16 02:29:48 PM PDT 24
Peak memory 200732 kb
Host smart-151a9042-a950-4803-8c56-1507e23cabc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461270397 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.3461270397
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.642488470
Short name T78
Test name
Test status
Simulation time 20027295179 ps
CPU time 1454.07 seconds
Started May 16 02:29:07 PM PDT 24
Finished May 16 02:53:25 PM PDT 24
Peak memory 741940 kb
Host smart-17df56dc-fc0a-46d1-87f9-436110f02f52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=642488470 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.642488470
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_long_msg.4125525466
Short name T66
Test name
Test status
Simulation time 408100557 ps
CPU time 25.54 seconds
Started May 16 02:29:06 PM PDT 24
Finished May 16 02:29:35 PM PDT 24
Peak memory 200632 kb
Host smart-5653f2d7-762a-45fc-b7a2-0cfcc2a6a839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125525466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.4125525466
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.3251833057
Short name T17
Test name
Test status
Simulation time 377342584 ps
CPU time 3.51 seconds
Started May 16 02:29:11 PM PDT 24
Finished May 16 02:29:18 PM PDT 24
Peak memory 200588 kb
Host smart-d8141b68-b48a-481a-a80b-972e9bfff86e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251833057 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.3251833057
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.1705636350
Short name T313
Test name
Test status
Simulation time 5470995956 ps
CPU time 58.28 seconds
Started May 16 02:29:07 PM PDT 24
Finished May 16 02:30:08 PM PDT 24
Peak memory 200716 kb
Host smart-7baaa6d1-4319-4736-808f-ec82a7985597
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705636350 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.1705636350
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_test_hmac_vectors.693208117
Short name T317
Test name
Test status
Simulation time 97594944 ps
CPU time 1.3 seconds
Started May 16 02:29:13 PM PDT 24
Finished May 16 02:29:18 PM PDT 24
Peak memory 200648 kb
Host smart-9a6ed8c9-f8c6-4b54-81d9-d49ca8cabff0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693208117 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 16.hmac_test_hmac_vectors.693208117
Directory /workspace/16.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha_vectors.820149127
Short name T6
Test name
Test status
Simulation time 14467937462 ps
CPU time 405.14 seconds
Started May 16 02:29:10 PM PDT 24
Finished May 16 02:35:59 PM PDT 24
Peak memory 200624 kb
Host smart-0a8c3722-7298-4737-a43d-59c21a7e4667
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820149127 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_sha_vectors.820149127
Directory /workspace/16.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/17.hmac_alert_test.1087738049
Short name T364
Test name
Test status
Simulation time 25523089 ps
CPU time 0.59 seconds
Started May 16 02:29:13 PM PDT 24
Finished May 16 02:29:17 PM PDT 24
Peak memory 197124 kb
Host smart-d960d61f-5f5f-46e7-91ee-a978d26e5a41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087738049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.1087738049
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.1454946588
Short name T393
Test name
Test status
Simulation time 615254581 ps
CPU time 31.9 seconds
Started May 16 02:29:05 PM PDT 24
Finished May 16 02:29:41 PM PDT 24
Peak memory 208856 kb
Host smart-b41bf3a9-6abf-47a9-a859-ceaf7ccd23f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1454946588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.1454946588
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.4101435775
Short name T475
Test name
Test status
Simulation time 902554647 ps
CPU time 8.61 seconds
Started May 16 02:29:14 PM PDT 24
Finished May 16 02:29:26 PM PDT 24
Peak memory 200676 kb
Host smart-510ae490-b000-4b43-b31c-1bd23efd321a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101435775 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.4101435775
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.1400735493
Short name T241
Test name
Test status
Simulation time 2660898205 ps
CPU time 800.68 seconds
Started May 16 02:29:06 PM PDT 24
Finished May 16 02:42:30 PM PDT 24
Peak memory 676272 kb
Host smart-aa55228a-1492-44df-93b6-74db614ab508
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1400735493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.1400735493
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_long_msg.2400942610
Short name T220
Test name
Test status
Simulation time 1367295573 ps
CPU time 85.68 seconds
Started May 16 02:29:08 PM PDT 24
Finished May 16 02:30:37 PM PDT 24
Peak memory 200644 kb
Host smart-4459abfc-4a2e-430c-a94d-e17c06fd0cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400942610 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.2400942610
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.3157580243
Short name T187
Test name
Test status
Simulation time 806046848 ps
CPU time 3.41 seconds
Started May 16 02:29:09 PM PDT 24
Finished May 16 02:29:17 PM PDT 24
Peak memory 200552 kb
Host smart-3303be3d-93a6-44da-92c8-e419fd912693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157580243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.3157580243
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_test_hmac_vectors.2362377446
Short name T83
Test name
Test status
Simulation time 93536774 ps
CPU time 1.06 seconds
Started May 16 02:29:10 PM PDT 24
Finished May 16 02:29:15 PM PDT 24
Peak memory 200164 kb
Host smart-87e73205-b775-403f-af03-89d4fe59cc6d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362377446 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.hmac_test_hmac_vectors.2362377446
Directory /workspace/17.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha_vectors.595211290
Short name T252
Test name
Test status
Simulation time 33955984884 ps
CPU time 498.01 seconds
Started May 16 02:29:05 PM PDT 24
Finished May 16 02:37:27 PM PDT 24
Peak memory 200724 kb
Host smart-91649311-6c96-44e8-a2b2-af29eb854858
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595211290 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_sha_vectors.595211290
Directory /workspace/17.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/18.hmac_alert_test.2457145161
Short name T245
Test name
Test status
Simulation time 29461080 ps
CPU time 0.64 seconds
Started May 16 02:29:10 PM PDT 24
Finished May 16 02:29:14 PM PDT 24
Peak memory 196380 kb
Host smart-ea981fdb-e517-4684-9a3a-155c45fcfbf8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457145161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.2457145161
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.1334932669
Short name T266
Test name
Test status
Simulation time 136820953 ps
CPU time 6.74 seconds
Started May 16 02:29:10 PM PDT 24
Finished May 16 02:29:20 PM PDT 24
Peak memory 200560 kb
Host smart-345aa9f6-1c85-43bc-bfca-91436645e9c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1334932669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.1334932669
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.2491940239
Short name T123
Test name
Test status
Simulation time 314940846 ps
CPU time 16.48 seconds
Started May 16 02:29:10 PM PDT 24
Finished May 16 02:29:30 PM PDT 24
Peak memory 200696 kb
Host smart-3f26a1c0-f6fd-4c77-90ef-6c9447ea7612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491940239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.2491940239
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.206333484
Short name T473
Test name
Test status
Simulation time 5968389060 ps
CPU time 314.5 seconds
Started May 16 02:29:15 PM PDT 24
Finished May 16 02:34:32 PM PDT 24
Peak memory 443180 kb
Host smart-c0abdd35-11e8-4574-879c-9622f21a72ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=206333484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.206333484
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_long_msg.1700003803
Short name T300
Test name
Test status
Simulation time 7895994333 ps
CPU time 76.86 seconds
Started May 16 02:29:06 PM PDT 24
Finished May 16 02:30:26 PM PDT 24
Peak memory 200768 kb
Host smart-bf3117af-dd40-4d3a-bfd1-8a36927032f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700003803 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.1700003803
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.2953670104
Short name T262
Test name
Test status
Simulation time 910710234 ps
CPU time 4.89 seconds
Started May 16 02:29:09 PM PDT 24
Finished May 16 02:29:18 PM PDT 24
Peak memory 200616 kb
Host smart-41b1d685-f0be-4745-a8e4-239fea2b0bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953670104 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.2953670104
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_test_hmac_vectors.4081733288
Short name T327
Test name
Test status
Simulation time 86041043 ps
CPU time 1 seconds
Started May 16 02:29:09 PM PDT 24
Finished May 16 02:29:14 PM PDT 24
Peak memory 199964 kb
Host smart-5437ca74-9722-4b60-8887-33727e2d5d49
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081733288 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.hmac_test_hmac_vectors.4081733288
Directory /workspace/18.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha_vectors.55667262
Short name T389
Test name
Test status
Simulation time 27919253494 ps
CPU time 499.67 seconds
Started May 16 02:29:14 PM PDT 24
Finished May 16 02:37:37 PM PDT 24
Peak memory 200656 kb
Host smart-1cc01ff6-86b3-4de8-af8c-8867639413b9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55667262 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_sha_vectors.55667262
Directory /workspace/18.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/19.hmac_alert_test.3138210012
Short name T391
Test name
Test status
Simulation time 18125613 ps
CPU time 0.59 seconds
Started May 16 02:29:18 PM PDT 24
Finished May 16 02:29:22 PM PDT 24
Peak memory 196388 kb
Host smart-46384228-e5a2-4ccf-bacd-263861fa9b94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138210012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.3138210012
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.1081778599
Short name T231
Test name
Test status
Simulation time 44474312 ps
CPU time 2.83 seconds
Started May 16 02:29:08 PM PDT 24
Finished May 16 02:29:14 PM PDT 24
Peak memory 200560 kb
Host smart-f0b38041-bc2b-4493-98a9-503925e30dcc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1081778599 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.1081778599
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.311238853
Short name T210
Test name
Test status
Simulation time 1129350915 ps
CPU time 15.04 seconds
Started May 16 02:29:17 PM PDT 24
Finished May 16 02:29:35 PM PDT 24
Peak memory 200632 kb
Host smart-9c788b73-b4e6-43d6-abea-db84d56b096d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311238853 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.311238853
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.1924873072
Short name T379
Test name
Test status
Simulation time 11549919318 ps
CPU time 209.25 seconds
Started May 16 02:29:06 PM PDT 24
Finished May 16 02:32:39 PM PDT 24
Peak memory 458040 kb
Host smart-b6686dee-a845-42b4-bc82-3107c0f02251
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1924873072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.1924873072
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_long_msg.3685129962
Short name T89
Test name
Test status
Simulation time 7302578500 ps
CPU time 99.11 seconds
Started May 16 02:29:10 PM PDT 24
Finished May 16 02:30:53 PM PDT 24
Peak memory 200724 kb
Host smart-c8d5b5fc-3a67-4f72-b578-2a126855a588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685129962 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.3685129962
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.2465740622
Short name T5
Test name
Test status
Simulation time 224559727 ps
CPU time 2.83 seconds
Started May 16 02:29:15 PM PDT 24
Finished May 16 02:29:21 PM PDT 24
Peak memory 200620 kb
Host smart-47a678eb-6754-448f-9c96-9cb4df25cf59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465740622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.2465740622
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_test_hmac_vectors.2772887864
Short name T439
Test name
Test status
Simulation time 237145282 ps
CPU time 1.06 seconds
Started May 16 02:29:16 PM PDT 24
Finished May 16 02:29:21 PM PDT 24
Peak memory 200164 kb
Host smart-88fad0b5-2a13-463b-b0ac-58c7597bed12
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772887864 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.hmac_test_hmac_vectors.2772887864
Directory /workspace/19.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha_vectors.537428551
Short name T286
Test name
Test status
Simulation time 30308961044 ps
CPU time 521.12 seconds
Started May 16 02:29:10 PM PDT 24
Finished May 16 02:37:55 PM PDT 24
Peak memory 200688 kb
Host smart-84a7213e-19e9-472a-9bb8-37f779336d83
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537428551 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_sha_vectors.537428551
Directory /workspace/19.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/2.hmac_alert_test.1459457096
Short name T160
Test name
Test status
Simulation time 13840514 ps
CPU time 0.6 seconds
Started May 16 02:28:30 PM PDT 24
Finished May 16 02:28:35 PM PDT 24
Peak memory 195984 kb
Host smart-42ae270f-e39a-4f8e-a89c-1f5c3ce5a42d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459457096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.1459457096
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.1004151222
Short name T446
Test name
Test status
Simulation time 245860138 ps
CPU time 13.44 seconds
Started May 16 02:28:29 PM PDT 24
Finished May 16 02:28:45 PM PDT 24
Peak memory 217036 kb
Host smart-067182ae-bddb-482a-bf29-a126767cd44e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1004151222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.1004151222
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.3416591142
Short name T273
Test name
Test status
Simulation time 347701728 ps
CPU time 6.65 seconds
Started May 16 02:28:30 PM PDT 24
Finished May 16 02:28:41 PM PDT 24
Peak memory 200572 kb
Host smart-d9de50f6-2ff6-4d06-a301-424b081bbbf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416591142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.3416591142
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.3431600707
Short name T459
Test name
Test status
Simulation time 14075079235 ps
CPU time 890.3 seconds
Started May 16 02:28:32 PM PDT 24
Finished May 16 02:43:26 PM PDT 24
Peak memory 724524 kb
Host smart-516a7781-95bd-4fd8-9da4-c0fd2bff0b8f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3431600707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.3431600707
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_long_msg.3649360383
Short name T240
Test name
Test status
Simulation time 5707931503 ps
CPU time 85.23 seconds
Started May 16 02:28:30 PM PDT 24
Finished May 16 02:29:59 PM PDT 24
Peak memory 200724 kb
Host smart-16103b40-6fae-4d64-8ae4-c4b7b53e382d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649360383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.3649360383
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.1372131839
Short name T38
Test name
Test status
Simulation time 58601394 ps
CPU time 0.93 seconds
Started May 16 02:28:29 PM PDT 24
Finished May 16 02:28:31 PM PDT 24
Peak memory 218860 kb
Host smart-f142a787-f8bb-4530-a395-68cd404854d9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372131839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.1372131839
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.3998624616
Short name T321
Test name
Test status
Simulation time 508567812 ps
CPU time 3.24 seconds
Started May 16 02:28:31 PM PDT 24
Finished May 16 02:28:38 PM PDT 24
Peak memory 200584 kb
Host smart-02b261a4-f0ec-43dd-a653-f4fc8cfb5980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998624616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.3998624616
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.412435316
Short name T445
Test name
Test status
Simulation time 2261815886 ps
CPU time 130.68 seconds
Started May 16 02:28:30 PM PDT 24
Finished May 16 02:30:44 PM PDT 24
Peak memory 231920 kb
Host smart-ef71bcc3-ab6e-4ebe-9136-69c72694aa0c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412435316 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.412435316
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_test_hmac_vectors.539442668
Short name T232
Test name
Test status
Simulation time 29552551 ps
CPU time 1.06 seconds
Started May 16 02:28:32 PM PDT 24
Finished May 16 02:28:36 PM PDT 24
Peak memory 200040 kb
Host smart-649fe9dc-6bd4-4c69-8d8a-2696dae32cbd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539442668 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.hmac_test_hmac_vectors.539442668
Directory /workspace/2.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha_vectors.2498500728
Short name T366
Test name
Test status
Simulation time 30414228173 ps
CPU time 441.08 seconds
Started May 16 02:28:33 PM PDT 24
Finished May 16 02:35:57 PM PDT 24
Peak memory 200660 kb
Host smart-62e4d5b4-fc13-4cb3-93c1-b2e28bc2e538
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498500728 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha_vectors.2498500728
Directory /workspace/2.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/20.hmac_alert_test.3048716054
Short name T25
Test name
Test status
Simulation time 40851960 ps
CPU time 0.59 seconds
Started May 16 02:29:18 PM PDT 24
Finished May 16 02:29:22 PM PDT 24
Peak memory 195364 kb
Host smart-426d1be8-a1d8-4432-89dc-ea0ff1d61ff2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048716054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.3048716054
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.1713282484
Short name T365
Test name
Test status
Simulation time 8533318974 ps
CPU time 35.51 seconds
Started May 16 02:29:18 PM PDT 24
Finished May 16 02:29:57 PM PDT 24
Peak memory 241760 kb
Host smart-f0548287-37e8-4800-8e1f-94ad65d7c16d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1713282484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.1713282484
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.1987691219
Short name T117
Test name
Test status
Simulation time 3382733157 ps
CPU time 30.96 seconds
Started May 16 02:29:13 PM PDT 24
Finished May 16 02:29:48 PM PDT 24
Peak memory 200744 kb
Host smart-79e7fc6d-54f2-4721-8199-30bd92107409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987691219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.1987691219
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_long_msg.1932393119
Short name T433
Test name
Test status
Simulation time 6459715354 ps
CPU time 93.14 seconds
Started May 16 02:29:17 PM PDT 24
Finished May 16 02:30:53 PM PDT 24
Peak memory 200756 kb
Host smart-30c5f6b4-7993-423e-8c9f-8c825e9f4a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932393119 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.1932393119
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.2251243007
Short name T188
Test name
Test status
Simulation time 396779905 ps
CPU time 6.18 seconds
Started May 16 02:29:11 PM PDT 24
Finished May 16 02:29:21 PM PDT 24
Peak memory 200696 kb
Host smart-6a7b215d-2db0-423e-8eb4-560756e61aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251243007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.2251243007
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_test_hmac_vectors.508451031
Short name T427
Test name
Test status
Simulation time 28278676 ps
CPU time 0.93 seconds
Started May 16 02:29:10 PM PDT 24
Finished May 16 02:29:15 PM PDT 24
Peak memory 199136 kb
Host smart-d1956e43-c597-499c-b2ea-0b0a2473f7cb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508451031 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 20.hmac_test_hmac_vectors.508451031
Directory /workspace/20.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha_vectors.1876188930
Short name T75
Test name
Test status
Simulation time 29314627882 ps
CPU time 486.63 seconds
Started May 16 02:29:09 PM PDT 24
Finished May 16 02:37:20 PM PDT 24
Peak memory 200672 kb
Host smart-606224b3-62e7-4848-bbfb-4b12188fbcec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876188930 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_sha_vectors.1876188930
Directory /workspace/20.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/21.hmac_alert_test.296201811
Short name T186
Test name
Test status
Simulation time 33610572 ps
CPU time 0.59 seconds
Started May 16 02:29:15 PM PDT 24
Finished May 16 02:29:19 PM PDT 24
Peak memory 197120 kb
Host smart-db3373bf-8420-43ad-9538-2715f2fa4b56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296201811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.296201811
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.3591619650
Short name T138
Test name
Test status
Simulation time 2834007340 ps
CPU time 39.31 seconds
Started May 16 02:29:14 PM PDT 24
Finished May 16 02:29:56 PM PDT 24
Peak memory 233488 kb
Host smart-be2aa040-7425-4f9d-b8fb-8c07099ded73
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3591619650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.3591619650
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.2392454502
Short name T122
Test name
Test status
Simulation time 9272639393 ps
CPU time 31.19 seconds
Started May 16 02:29:16 PM PDT 24
Finished May 16 02:29:50 PM PDT 24
Peak memory 200732 kb
Host smart-b345b550-3592-40f9-9859-98b965fdab06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392454502 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.2392454502
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.3426417015
Short name T332
Test name
Test status
Simulation time 21516195880 ps
CPU time 645.88 seconds
Started May 16 02:29:15 PM PDT 24
Finished May 16 02:40:05 PM PDT 24
Peak memory 737544 kb
Host smart-d70e42d0-9b1f-48ae-87b0-6e557e0318eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3426417015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.3426417015
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_long_msg.3958133195
Short name T361
Test name
Test status
Simulation time 43745718850 ps
CPU time 95.63 seconds
Started May 16 02:29:13 PM PDT 24
Finished May 16 02:30:52 PM PDT 24
Peak memory 200740 kb
Host smart-feb46378-c97d-466b-9333-f022f5e95768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958133195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.3958133195
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.357986542
Short name T63
Test name
Test status
Simulation time 67999004 ps
CPU time 2.3 seconds
Started May 16 02:29:13 PM PDT 24
Finished May 16 02:29:18 PM PDT 24
Peak memory 200600 kb
Host smart-a9545865-a243-40e3-8813-74df2096d29b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357986542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.357986542
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.3130753541
Short name T68
Test name
Test status
Simulation time 209092268413 ps
CPU time 3315.23 seconds
Started May 16 02:29:15 PM PDT 24
Finished May 16 03:24:34 PM PDT 24
Peak memory 772240 kb
Host smart-d9d4ac18-10cc-4c0a-b3f4-a4ca6884863c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130753541 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.3130753541
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_test_hmac_vectors.1155832263
Short name T243
Test name
Test status
Simulation time 112885441 ps
CPU time 0.96 seconds
Started May 16 02:29:15 PM PDT 24
Finished May 16 02:29:19 PM PDT 24
Peak memory 199692 kb
Host smart-5ba094ff-8b90-4be5-b964-ebff106d45c2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155832263 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.hmac_test_hmac_vectors.1155832263
Directory /workspace/21.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha_vectors.2946213411
Short name T372
Test name
Test status
Simulation time 7056021879 ps
CPU time 405.03 seconds
Started May 16 02:29:19 PM PDT 24
Finished May 16 02:36:07 PM PDT 24
Peak memory 200672 kb
Host smart-ca50d4e3-f3d1-44c4-89a7-c727b8aa50b2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946213411 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_sha_vectors.2946213411
Directory /workspace/21.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/22.hmac_alert_test.3304838474
Short name T438
Test name
Test status
Simulation time 37450754 ps
CPU time 0.6 seconds
Started May 16 02:29:22 PM PDT 24
Finished May 16 02:29:24 PM PDT 24
Peak memory 195340 kb
Host smart-3536195c-b3da-487b-a5d4-c8c12330ee1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304838474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.3304838474
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.2942949974
Short name T412
Test name
Test status
Simulation time 3495875863 ps
CPU time 42.43 seconds
Started May 16 02:29:12 PM PDT 24
Finished May 16 02:29:58 PM PDT 24
Peak memory 233504 kb
Host smart-93fcac9a-0249-4ec1-9083-5e580e9c3081
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2942949974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.2942949974
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.1310461115
Short name T254
Test name
Test status
Simulation time 603434803 ps
CPU time 16.8 seconds
Started May 16 02:29:14 PM PDT 24
Finished May 16 02:29:34 PM PDT 24
Peak memory 200608 kb
Host smart-5e0ebc3a-090e-4bd7-a86c-a3fac4d3955d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310461115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.1310461115
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.3137595958
Short name T350
Test name
Test status
Simulation time 43750484272 ps
CPU time 736.77 seconds
Started May 16 02:29:17 PM PDT 24
Finished May 16 02:41:37 PM PDT 24
Peak memory 617080 kb
Host smart-99636a01-5cbf-4f92-bc3f-3118d80468c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3137595958 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.3137595958
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_long_msg.3495193178
Short name T424
Test name
Test status
Simulation time 3787897365 ps
CPU time 12.35 seconds
Started May 16 02:29:11 PM PDT 24
Finished May 16 02:29:27 PM PDT 24
Peak memory 200776 kb
Host smart-9110b62c-aca0-4e65-8c01-d90084d89c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495193178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.3495193178
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.953091512
Short name T211
Test name
Test status
Simulation time 763384179 ps
CPU time 6.76 seconds
Started May 16 02:29:13 PM PDT 24
Finished May 16 02:29:23 PM PDT 24
Peak memory 200596 kb
Host smart-9b046614-ecca-48cb-ace2-df3480d0bf80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953091512 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.953091512
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.566872821
Short name T67
Test name
Test status
Simulation time 14642444535 ps
CPU time 636.02 seconds
Started May 16 02:29:23 PM PDT 24
Finished May 16 02:40:01 PM PDT 24
Peak memory 654600 kb
Host smart-2d06cf9c-e374-41df-a045-5ff0a03019e1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566872821 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.566872821
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_test_hmac_vectors.1147792443
Short name T275
Test name
Test status
Simulation time 30639200 ps
CPU time 1.14 seconds
Started May 16 02:29:15 PM PDT 24
Finished May 16 02:29:19 PM PDT 24
Peak memory 200640 kb
Host smart-fc6c568f-789b-44b5-8017-f45c37e13b06
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147792443 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.hmac_test_hmac_vectors.1147792443
Directory /workspace/22.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha_vectors.2727806381
Short name T359
Test name
Test status
Simulation time 7410911021 ps
CPU time 437.13 seconds
Started May 16 02:29:19 PM PDT 24
Finished May 16 02:36:39 PM PDT 24
Peak memory 200720 kb
Host smart-73cd81b4-dd0f-41ba-9820-67cff16e34d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727806381 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_sha_vectors.2727806381
Directory /workspace/22.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/23.hmac_alert_test.2289352190
Short name T405
Test name
Test status
Simulation time 12322355 ps
CPU time 0.59 seconds
Started May 16 02:29:34 PM PDT 24
Finished May 16 02:29:37 PM PDT 24
Peak memory 195348 kb
Host smart-cff13913-8f48-426b-95e4-77ebe3cfd0ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289352190 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.2289352190
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.248655430
Short name T267
Test name
Test status
Simulation time 11196750574 ps
CPU time 31.38 seconds
Started May 16 02:29:24 PM PDT 24
Finished May 16 02:29:57 PM PDT 24
Peak memory 208936 kb
Host smart-21fd7bd7-cbae-4866-8a98-421baa89a936
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=248655430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.248655430
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.3320584758
Short name T256
Test name
Test status
Simulation time 1257847226 ps
CPU time 16.61 seconds
Started May 16 02:29:22 PM PDT 24
Finished May 16 02:29:40 PM PDT 24
Peak memory 200668 kb
Host smart-112b948b-27bc-47fc-bc6f-7a7c8d3d7335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320584758 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.3320584758
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.3906495011
Short name T111
Test name
Test status
Simulation time 4574058374 ps
CPU time 619.55 seconds
Started May 16 02:29:25 PM PDT 24
Finished May 16 02:39:46 PM PDT 24
Peak memory 717940 kb
Host smart-681724df-e0eb-4d3c-893c-7ff1aa69f38f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3906495011 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.3906495011
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_long_msg.1132388909
Short name T281
Test name
Test status
Simulation time 1525762460 ps
CPU time 90.54 seconds
Started May 16 02:29:23 PM PDT 24
Finished May 16 02:30:56 PM PDT 24
Peak memory 200620 kb
Host smart-a987cf91-e89e-46fc-8131-de9de90b9d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132388909 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.1132388909
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.1251608876
Short name T206
Test name
Test status
Simulation time 831967992 ps
CPU time 3.37 seconds
Started May 16 02:29:22 PM PDT 24
Finished May 16 02:29:27 PM PDT 24
Peak memory 200624 kb
Host smart-37f810e3-7d57-4e11-b8a6-506146928eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251608876 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.1251608876
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.2300892378
Short name T448
Test name
Test status
Simulation time 15656743495 ps
CPU time 151.2 seconds
Started May 16 02:29:23 PM PDT 24
Finished May 16 02:31:56 PM PDT 24
Peak memory 225356 kb
Host smart-27a45a81-4f7d-49c1-be4d-fa68b091d323
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300892378 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.2300892378
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_test_hmac_vectors.383033326
Short name T197
Test name
Test status
Simulation time 29862540 ps
CPU time 1.01 seconds
Started May 16 02:29:23 PM PDT 24
Finished May 16 02:29:26 PM PDT 24
Peak memory 200324 kb
Host smart-6d8f222f-c65d-4cdc-9694-4c283c4b054d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383033326 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 23.hmac_test_hmac_vectors.383033326
Directory /workspace/23.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha_vectors.1579185539
Short name T328
Test name
Test status
Simulation time 36477959921 ps
CPU time 518.67 seconds
Started May 16 02:29:24 PM PDT 24
Finished May 16 02:38:04 PM PDT 24
Peak memory 200656 kb
Host smart-86a8c21e-ca71-444c-9c06-6d4f53596be3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579185539 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_sha_vectors.1579185539
Directory /workspace/23.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.3570762499
Short name T37
Test name
Test status
Simulation time 1207032725 ps
CPU time 5.53 seconds
Started May 16 02:29:25 PM PDT 24
Finished May 16 02:29:32 PM PDT 24
Peak memory 200472 kb
Host smart-39e45012-617c-4e80-a14c-be4bb091c8a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570762499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.3570762499
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.3219044
Short name T466
Test name
Test status
Simulation time 19869898 ps
CPU time 0.58 seconds
Started May 16 02:29:36 PM PDT 24
Finished May 16 02:29:39 PM PDT 24
Peak memory 195320 kb
Host smart-83e2af18-7df0-4c09-bde0-52482a714129
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219044 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.3219044
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.173912926
Short name T263
Test name
Test status
Simulation time 655893904 ps
CPU time 32.94 seconds
Started May 16 02:29:34 PM PDT 24
Finished May 16 02:30:09 PM PDT 24
Peak memory 208848 kb
Host smart-8be16db9-0387-4cbc-adeb-21e9ae862529
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=173912926 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.173912926
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.1853872941
Short name T415
Test name
Test status
Simulation time 1096517767 ps
CPU time 60.43 seconds
Started May 16 02:29:34 PM PDT 24
Finished May 16 02:30:37 PM PDT 24
Peak memory 200640 kb
Host smart-8f92da20-30cc-42d0-b407-99dba93879a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853872941 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.1853872941
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.3109398958
Short name T434
Test name
Test status
Simulation time 8753240022 ps
CPU time 499.06 seconds
Started May 16 02:29:36 PM PDT 24
Finished May 16 02:37:58 PM PDT 24
Peak memory 622700 kb
Host smart-c5d91af1-95d6-477b-86ab-a4c16da8f54b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3109398958 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.3109398958
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.458692368
Short name T421
Test name
Test status
Simulation time 33310471287 ps
CPU time 104.54 seconds
Started May 16 02:29:33 PM PDT 24
Finished May 16 02:31:20 PM PDT 24
Peak memory 200864 kb
Host smart-b1e68d47-4b2a-4e80-acbd-40b90b959e32
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458692368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.458692368
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.1600660062
Short name T239
Test name
Test status
Simulation time 1493758688 ps
CPU time 90.94 seconds
Started May 16 02:29:35 PM PDT 24
Finished May 16 02:31:09 PM PDT 24
Peak memory 200564 kb
Host smart-e6188ba6-a062-44b5-b0ae-9778ccddcfcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600660062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.1600660062
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.3943718845
Short name T274
Test name
Test status
Simulation time 414660891 ps
CPU time 6.76 seconds
Started May 16 02:29:35 PM PDT 24
Finished May 16 02:29:44 PM PDT 24
Peak memory 200652 kb
Host smart-735fa281-59c4-41bb-b071-7c17c052a348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943718845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.3943718845
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_test_hmac_vectors.1677833564
Short name T437
Test name
Test status
Simulation time 50567599 ps
CPU time 1.05 seconds
Started May 16 02:29:34 PM PDT 24
Finished May 16 02:29:38 PM PDT 24
Peak memory 199156 kb
Host smart-04fc7905-0797-4986-a5c1-868dcdb24847
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677833564 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.hmac_test_hmac_vectors.1677833564
Directory /workspace/24.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha_vectors.1632371703
Short name T196
Test name
Test status
Simulation time 29177946301 ps
CPU time 398.11 seconds
Started May 16 02:29:35 PM PDT 24
Finished May 16 02:36:16 PM PDT 24
Peak memory 200664 kb
Host smart-18abd85e-7da1-410e-b949-d3f52b7ac56f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632371703 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_sha_vectors.1632371703
Directory /workspace/24.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/25.hmac_alert_test.1734659825
Short name T464
Test name
Test status
Simulation time 54669016 ps
CPU time 0.59 seconds
Started May 16 02:29:34 PM PDT 24
Finished May 16 02:29:37 PM PDT 24
Peak memory 196372 kb
Host smart-792d205e-dd71-4434-8b33-f6474c49a57c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734659825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.1734659825
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.1859782108
Short name T221
Test name
Test status
Simulation time 3112225855 ps
CPU time 64.75 seconds
Started May 16 02:29:33 PM PDT 24
Finished May 16 02:30:40 PM PDT 24
Peak memory 233160 kb
Host smart-a31e2828-c5a4-4a56-b3d0-293bb594097d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1859782108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.1859782108
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.2118275849
Short name T369
Test name
Test status
Simulation time 4073151222 ps
CPU time 56.04 seconds
Started May 16 02:29:35 PM PDT 24
Finished May 16 02:30:33 PM PDT 24
Peak memory 200768 kb
Host smart-9253f1d0-2e63-4c98-8914-39f5f002c467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118275849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.2118275849
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_error.1600365711
Short name T474
Test name
Test status
Simulation time 448325981 ps
CPU time 24.47 seconds
Started May 16 02:29:33 PM PDT 24
Finished May 16 02:30:00 PM PDT 24
Peak memory 200580 kb
Host smart-4690dd54-50f0-4388-b2ef-5adf44272c1e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600365711 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.1600365711
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.3713990062
Short name T84
Test name
Test status
Simulation time 4948722633 ps
CPU time 72.34 seconds
Started May 16 02:29:37 PM PDT 24
Finished May 16 02:30:52 PM PDT 24
Peak memory 200732 kb
Host smart-ff840545-7377-4beb-91ba-4d2b019c3a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713990062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.3713990062
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.949507108
Short name T179
Test name
Test status
Simulation time 693003154 ps
CPU time 7.86 seconds
Started May 16 02:29:33 PM PDT 24
Finished May 16 02:29:43 PM PDT 24
Peak memory 200568 kb
Host smart-d3db77d8-0dbb-457b-99f2-f860220823c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949507108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.949507108
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_test_hmac_vectors.1370510274
Short name T287
Test name
Test status
Simulation time 79243102 ps
CPU time 1.13 seconds
Started May 16 02:29:35 PM PDT 24
Finished May 16 02:29:39 PM PDT 24
Peak memory 200424 kb
Host smart-c464286f-b800-4a27-bc69-15c85ee12211
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370510274 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.hmac_test_hmac_vectors.1370510274
Directory /workspace/25.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha_vectors.3007463976
Short name T319
Test name
Test status
Simulation time 50711289332 ps
CPU time 548.55 seconds
Started May 16 02:29:34 PM PDT 24
Finished May 16 02:38:46 PM PDT 24
Peak memory 200648 kb
Host smart-536260aa-d91b-4131-9edc-1add815fae2e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007463976 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_sha_vectors.3007463976
Directory /workspace/25.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.1076127549
Short name T419
Test name
Test status
Simulation time 300891753 ps
CPU time 4.83 seconds
Started May 16 02:29:35 PM PDT 24
Finished May 16 02:29:43 PM PDT 24
Peak memory 200588 kb
Host smart-2b39535e-c2a2-40f0-a50c-3041d77950e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076127549 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.1076127549
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.289946433
Short name T331
Test name
Test status
Simulation time 12199465 ps
CPU time 0.58 seconds
Started May 16 02:29:44 PM PDT 24
Finished May 16 02:29:47 PM PDT 24
Peak memory 195364 kb
Host smart-cd855cba-2028-4354-9d90-5b98461a9acc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289946433 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.289946433
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.439739978
Short name T461
Test name
Test status
Simulation time 365760821 ps
CPU time 5.47 seconds
Started May 16 02:29:37 PM PDT 24
Finished May 16 02:29:45 PM PDT 24
Peak memory 200564 kb
Host smart-4b4e4601-c8f5-445c-be63-c2bde54f730b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=439739978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.439739978
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.481419608
Short name T456
Test name
Test status
Simulation time 9795861247 ps
CPU time 18.33 seconds
Started May 16 02:29:35 PM PDT 24
Finished May 16 02:29:56 PM PDT 24
Peak memory 200732 kb
Host smart-99a719b9-498a-4797-adf6-13895ac11311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481419608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.481419608
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.488194326
Short name T340
Test name
Test status
Simulation time 10493218782 ps
CPU time 664.15 seconds
Started May 16 02:29:33 PM PDT 24
Finished May 16 02:40:39 PM PDT 24
Peak memory 671268 kb
Host smart-e7b801ac-e816-40cd-aebc-ce8cb509fc70
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=488194326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.488194326
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_long_msg.692591818
Short name T341
Test name
Test status
Simulation time 4188734565 ps
CPU time 60.44 seconds
Started May 16 02:29:36 PM PDT 24
Finished May 16 02:30:39 PM PDT 24
Peak memory 200740 kb
Host smart-e8a2c3a4-7b8c-4f7a-9ea4-01030601a6a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692591818 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.692591818
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.391211486
Short name T225
Test name
Test status
Simulation time 544668131 ps
CPU time 5.19 seconds
Started May 16 02:29:33 PM PDT 24
Finished May 16 02:29:40 PM PDT 24
Peak memory 200676 kb
Host smart-2d954ec4-bc38-43cc-b69e-b9080da66a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391211486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.391211486
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.3160788564
Short name T137
Test name
Test status
Simulation time 9096451936 ps
CPU time 505.21 seconds
Started May 16 02:29:48 PM PDT 24
Finished May 16 02:38:16 PM PDT 24
Peak memory 200764 kb
Host smart-84193b30-d19e-4612-98db-5fa5caede83c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160788564 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.3160788564
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_test_hmac_vectors.852099582
Short name T174
Test name
Test status
Simulation time 56044491 ps
CPU time 1.35 seconds
Started May 16 02:29:48 PM PDT 24
Finished May 16 02:29:52 PM PDT 24
Peak memory 200460 kb
Host smart-a75b5b36-d16f-4a21-ad85-f78c391b35e7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852099582 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 26.hmac_test_hmac_vectors.852099582
Directory /workspace/26.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha_vectors.1502246460
Short name T311
Test name
Test status
Simulation time 87315663018 ps
CPU time 565.87 seconds
Started May 16 02:29:52 PM PDT 24
Finished May 16 02:39:21 PM PDT 24
Peak memory 200724 kb
Host smart-90c5732a-0c9a-448d-82b0-359306ccff40
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502246460 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_sha_vectors.1502246460
Directory /workspace/26.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/27.hmac_alert_test.3235569471
Short name T430
Test name
Test status
Simulation time 38413928 ps
CPU time 0.58 seconds
Started May 16 02:29:52 PM PDT 24
Finished May 16 02:29:56 PM PDT 24
Peak memory 195348 kb
Host smart-8fb42310-2e88-4415-bc35-1c1db3ea2682
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235569471 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.3235569471
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.1317304861
Short name T48
Test name
Test status
Simulation time 1546724333 ps
CPU time 17.32 seconds
Started May 16 02:29:50 PM PDT 24
Finished May 16 02:30:10 PM PDT 24
Peak memory 213064 kb
Host smart-09a235fc-35dc-4bd9-a5f3-d14e1b242cf0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1317304861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.1317304861
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.432477987
Short name T471
Test name
Test status
Simulation time 1360237508 ps
CPU time 271.16 seconds
Started May 16 02:29:48 PM PDT 24
Finished May 16 02:34:22 PM PDT 24
Peak memory 452256 kb
Host smart-bcb2138d-4156-45cf-bd7d-2b53e17db718
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=432477987 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.432477987
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_long_msg.480536827
Short name T371
Test name
Test status
Simulation time 1828698673 ps
CPU time 40.2 seconds
Started May 16 02:29:51 PM PDT 24
Finished May 16 02:30:34 PM PDT 24
Peak memory 200644 kb
Host smart-582d1412-2473-4fef-a3ee-405ad1af3a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480536827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.480536827
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.263640819
Short name T451
Test name
Test status
Simulation time 2246701607 ps
CPU time 6.84 seconds
Started May 16 02:29:49 PM PDT 24
Finished May 16 02:29:58 PM PDT 24
Peak memory 200684 kb
Host smart-5120734d-17fa-4529-ae06-f9e237cfdb8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263640819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.263640819
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_test_hmac_vectors.248572845
Short name T249
Test name
Test status
Simulation time 49153403 ps
CPU time 1.27 seconds
Started May 16 02:29:49 PM PDT 24
Finished May 16 02:29:53 PM PDT 24
Peak memory 200368 kb
Host smart-4124517b-5e64-4392-812b-5f2e9442aace
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248572845 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 27.hmac_test_hmac_vectors.248572845
Directory /workspace/27.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha_vectors.1637775725
Short name T202
Test name
Test status
Simulation time 23836495859 ps
CPU time 479.54 seconds
Started May 16 02:29:42 PM PDT 24
Finished May 16 02:37:43 PM PDT 24
Peak memory 200632 kb
Host smart-66e7ddce-9730-4989-81c2-346cbed7cc67
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637775725 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_sha_vectors.1637775725
Directory /workspace/27.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/28.hmac_alert_test.3682747162
Short name T385
Test name
Test status
Simulation time 23270002 ps
CPU time 0.56 seconds
Started May 16 02:29:44 PM PDT 24
Finished May 16 02:29:46 PM PDT 24
Peak memory 195364 kb
Host smart-20fb4291-72bc-4602-bb13-9d3563c4df2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682747162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.3682747162
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.2958742005
Short name T458
Test name
Test status
Simulation time 866726930 ps
CPU time 46.67 seconds
Started May 16 02:29:45 PM PDT 24
Finished May 16 02:30:34 PM PDT 24
Peak memory 241548 kb
Host smart-b355c792-8114-46a4-b613-5b9f31b93e46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2958742005 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.2958742005
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.1538225093
Short name T336
Test name
Test status
Simulation time 3198508106 ps
CPU time 47.81 seconds
Started May 16 02:29:44 PM PDT 24
Finished May 16 02:30:34 PM PDT 24
Peak memory 200704 kb
Host smart-5893d8b0-4513-4d9e-a0a2-34a50ef9d5df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538225093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.1538225093
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.3180823470
Short name T175
Test name
Test status
Simulation time 3531309372 ps
CPU time 513.23 seconds
Started May 16 02:29:42 PM PDT 24
Finished May 16 02:38:17 PM PDT 24
Peak memory 690376 kb
Host smart-25d553ca-0333-497c-b1a4-88527a89bcfa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3180823470 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.3180823470
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_long_msg.1006300867
Short name T180
Test name
Test status
Simulation time 552065259 ps
CPU time 32.14 seconds
Started May 16 02:29:49 PM PDT 24
Finished May 16 02:30:24 PM PDT 24
Peak memory 200588 kb
Host smart-098f2214-9a3d-4a80-99f0-93db220cf4ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006300867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.1006300867
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.2637965280
Short name T351
Test name
Test status
Simulation time 655101487 ps
CPU time 6.05 seconds
Started May 16 02:29:43 PM PDT 24
Finished May 16 02:29:50 PM PDT 24
Peak memory 200620 kb
Host smart-7dc7c248-e96a-42d3-8c2f-9dc279fa95a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637965280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.2637965280
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_test_hmac_vectors.2514771391
Short name T465
Test name
Test status
Simulation time 50751224 ps
CPU time 1.05 seconds
Started May 16 02:29:49 PM PDT 24
Finished May 16 02:29:53 PM PDT 24
Peak memory 199904 kb
Host smart-b8056a5d-da80-4fd9-a72e-f28f90e30941
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514771391 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.hmac_test_hmac_vectors.2514771391
Directory /workspace/28.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha_vectors.2357820474
Short name T49
Test name
Test status
Simulation time 82620730430 ps
CPU time 503.92 seconds
Started May 16 02:29:50 PM PDT 24
Finished May 16 02:38:17 PM PDT 24
Peak memory 200676 kb
Host smart-8ce39275-096a-47fa-b637-cc923efb3244
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357820474 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_sha_vectors.2357820474
Directory /workspace/28.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/29.hmac_alert_test.2633493510
Short name T159
Test name
Test status
Simulation time 43609367 ps
CPU time 0.61 seconds
Started May 16 02:29:53 PM PDT 24
Finished May 16 02:29:57 PM PDT 24
Peak memory 196396 kb
Host smart-1d0bf056-3b41-480f-b039-ef53030e6ee5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633493510 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.2633493510
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.2585172473
Short name T143
Test name
Test status
Simulation time 276529428 ps
CPU time 15.01 seconds
Started May 16 02:29:45 PM PDT 24
Finished May 16 02:30:02 PM PDT 24
Peak memory 208832 kb
Host smart-efb6bfc3-68ff-41cb-8e5e-8f85b400eeb1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2585172473 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.2585172473
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.3384016786
Short name T124
Test name
Test status
Simulation time 666331346 ps
CPU time 34.38 seconds
Started May 16 02:29:52 PM PDT 24
Finished May 16 02:30:30 PM PDT 24
Peak memory 200696 kb
Host smart-7a1a3644-b0a6-4ab5-9646-b26afc7b42ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384016786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.3384016786
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.4006037970
Short name T246
Test name
Test status
Simulation time 4987560006 ps
CPU time 372.35 seconds
Started May 16 02:29:50 PM PDT 24
Finished May 16 02:36:05 PM PDT 24
Peak memory 649868 kb
Host smart-52da731a-6ee9-4d3b-8385-1c9ea1b51ca1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4006037970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.4006037970
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_long_msg.2921819554
Short name T410
Test name
Test status
Simulation time 10067156710 ps
CPU time 54.39 seconds
Started May 16 02:29:48 PM PDT 24
Finished May 16 02:30:44 PM PDT 24
Peak memory 200716 kb
Host smart-7141115c-1197-4636-beb4-306dee607daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921819554 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.2921819554
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.1164663135
Short name T237
Test name
Test status
Simulation time 4005683832 ps
CPU time 3.87 seconds
Started May 16 02:29:46 PM PDT 24
Finished May 16 02:29:51 PM PDT 24
Peak memory 200744 kb
Host smart-b5d7ee62-9a7a-4cf0-a00c-c1e66c3de954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164663135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.1164663135
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.3711328858
Short name T36
Test name
Test status
Simulation time 30679522540 ps
CPU time 474.26 seconds
Started May 16 02:29:51 PM PDT 24
Finished May 16 02:37:49 PM PDT 24
Peak memory 217204 kb
Host smart-a942989c-fac4-44b5-95be-4ae1fa2f319e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711328858 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.3711328858
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_test_hmac_vectors.1831244282
Short name T435
Test name
Test status
Simulation time 29861337 ps
CPU time 1.2 seconds
Started May 16 02:29:53 PM PDT 24
Finished May 16 02:29:57 PM PDT 24
Peak memory 200540 kb
Host smart-4fbc4f33-4e32-4e70-9e21-3743037a22da
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831244282 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.hmac_test_hmac_vectors.1831244282
Directory /workspace/29.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha_vectors.1384424674
Short name T219
Test name
Test status
Simulation time 30761282684 ps
CPU time 422.15 seconds
Started May 16 02:29:52 PM PDT 24
Finished May 16 02:36:58 PM PDT 24
Peak memory 200712 kb
Host smart-d6febeab-30b8-4422-b95d-09878cd53ea2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384424674 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_sha_vectors.1384424674
Directory /workspace/29.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/3.hmac_alert_test.3668515866
Short name T367
Test name
Test status
Simulation time 17942262 ps
CPU time 0.64 seconds
Started May 16 02:28:49 PM PDT 24
Finished May 16 02:28:53 PM PDT 24
Peak memory 196388 kb
Host smart-081cc097-3645-49ab-b1b4-1d5aed12f1f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668515866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.3668515866
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.2538866750
Short name T45
Test name
Test status
Simulation time 5566916236 ps
CPU time 72.28 seconds
Started May 16 02:28:49 PM PDT 24
Finished May 16 02:30:04 PM PDT 24
Peak memory 233088 kb
Host smart-5835cfc9-d39d-40c2-91ac-38339d99495c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2538866750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.2538866750
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.46424871
Short name T34
Test name
Test status
Simulation time 469729441 ps
CPU time 7.16 seconds
Started May 16 02:28:50 PM PDT 24
Finished May 16 02:29:00 PM PDT 24
Peak memory 200600 kb
Host smart-e3ccf98b-858c-4650-92a0-db35719a3d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46424871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.46424871
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.1904651740
Short name T454
Test name
Test status
Simulation time 75196314112 ps
CPU time 1488.41 seconds
Started May 16 02:28:44 PM PDT 24
Finished May 16 02:53:35 PM PDT 24
Peak memory 797468 kb
Host smart-acba04d1-e1cd-4aba-9888-3ec411aa8d6d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1904651740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.1904651740
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_long_msg.2026002346
Short name T161
Test name
Test status
Simulation time 5243557492 ps
CPU time 19.51 seconds
Started May 16 02:28:43 PM PDT 24
Finished May 16 02:29:05 PM PDT 24
Peak memory 200760 kb
Host smart-b72a1a65-44e1-43ee-a98d-f40aca6dfb30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026002346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.2026002346
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.3728218632
Short name T39
Test name
Test status
Simulation time 61946342 ps
CPU time 0.94 seconds
Started May 16 02:28:49 PM PDT 24
Finished May 16 02:28:53 PM PDT 24
Peak memory 218932 kb
Host smart-d1814f6c-c176-458b-9212-e9f30cadf465
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728218632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.3728218632
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.360443568
Short name T323
Test name
Test status
Simulation time 152407228 ps
CPU time 4.99 seconds
Started May 16 02:28:48 PM PDT 24
Finished May 16 02:28:56 PM PDT 24
Peak memory 200600 kb
Host smart-bfeac961-b14f-401b-9afe-7aaac3d20497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360443568 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.360443568
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.410299450
Short name T166
Test name
Test status
Simulation time 455505320 ps
CPU time 2.21 seconds
Started May 16 02:28:42 PM PDT 24
Finished May 16 02:28:46 PM PDT 24
Peak memory 200628 kb
Host smart-29c7e06f-04f9-4a85-a8a5-396b7319a471
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410299450 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.410299450
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_test_hmac_vectors.3244034221
Short name T77
Test name
Test status
Simulation time 78667686 ps
CPU time 1.12 seconds
Started May 16 02:28:46 PM PDT 24
Finished May 16 02:28:50 PM PDT 24
Peak memory 200124 kb
Host smart-8e1d72c2-8514-4665-a020-1fd348c2a9b0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244034221 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.hmac_test_hmac_vectors.3244034221
Directory /workspace/3.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha_vectors.3272843103
Short name T467
Test name
Test status
Simulation time 8257560588 ps
CPU time 494.55 seconds
Started May 16 02:28:42 PM PDT 24
Finished May 16 02:36:58 PM PDT 24
Peak memory 200548 kb
Host smart-713ab634-151e-42ba-952b-34144d47f42a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272843103 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha_vectors.3272843103
Directory /workspace/3.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/30.hmac_alert_test.1144211664
Short name T271
Test name
Test status
Simulation time 43996833 ps
CPU time 0.59 seconds
Started May 16 02:29:57 PM PDT 24
Finished May 16 02:29:59 PM PDT 24
Peak memory 196080 kb
Host smart-6c32ddd2-414c-43cf-9eda-f71dfd1999fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144211664 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.1144211664
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.2268425799
Short name T22
Test name
Test status
Simulation time 3395984051 ps
CPU time 44.16 seconds
Started May 16 02:29:53 PM PDT 24
Finished May 16 02:30:40 PM PDT 24
Peak memory 233476 kb
Host smart-0e3bd3bb-e59d-47aa-8dc7-75d3f0f193ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2268425799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.2268425799
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.3014190772
Short name T384
Test name
Test status
Simulation time 1986389961 ps
CPU time 54.63 seconds
Started May 16 02:29:51 PM PDT 24
Finished May 16 02:30:49 PM PDT 24
Peak memory 200624 kb
Host smart-1b52ae4b-7e60-476b-89f8-d49d808d4d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014190772 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.3014190772
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.1855185781
Short name T291
Test name
Test status
Simulation time 3853462110 ps
CPU time 272.25 seconds
Started May 16 02:29:52 PM PDT 24
Finished May 16 02:34:28 PM PDT 24
Peak memory 492468 kb
Host smart-bcdabc7d-7579-48ca-9bff-77f950b6bf46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1855185781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.1855185781
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_long_msg.528253114
Short name T324
Test name
Test status
Simulation time 964528120 ps
CPU time 19.72 seconds
Started May 16 02:29:51 PM PDT 24
Finished May 16 02:30:14 PM PDT 24
Peak memory 200636 kb
Host smart-2b11b115-e1ec-48a7-bc9d-6b99d7628b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528253114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.528253114
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.139999727
Short name T258
Test name
Test status
Simulation time 525834144 ps
CPU time 6.01 seconds
Started May 16 02:29:53 PM PDT 24
Finished May 16 02:30:02 PM PDT 24
Peak memory 200596 kb
Host smart-76308cec-06d7-481e-ac63-96bc949ba85e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139999727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.139999727
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_test_hmac_vectors.4037516127
Short name T343
Test name
Test status
Simulation time 138002576 ps
CPU time 1.07 seconds
Started May 16 02:29:52 PM PDT 24
Finished May 16 02:29:57 PM PDT 24
Peak memory 200248 kb
Host smart-35cd0d8c-90f7-4f04-9c4b-e95c1230b5e4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037516127 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.hmac_test_hmac_vectors.4037516127
Directory /workspace/30.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha_vectors.2849793710
Short name T307
Test name
Test status
Simulation time 33311083446 ps
CPU time 421.86 seconds
Started May 16 02:29:52 PM PDT 24
Finished May 16 02:36:58 PM PDT 24
Peak memory 200696 kb
Host smart-0cc35fd3-b246-4650-bd79-88e949c8bba0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849793710 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_sha_vectors.2849793710
Directory /workspace/30.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/31.hmac_alert_test.1966776940
Short name T168
Test name
Test status
Simulation time 25635711 ps
CPU time 0.59 seconds
Started May 16 02:29:57 PM PDT 24
Finished May 16 02:29:59 PM PDT 24
Peak memory 195356 kb
Host smart-a48f8a83-6f6d-4c17-9d5d-5b1656785b4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966776940 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.1966776940
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.4056908481
Short name T47
Test name
Test status
Simulation time 3926333218 ps
CPU time 56.62 seconds
Started May 16 02:29:52 PM PDT 24
Finished May 16 02:30:52 PM PDT 24
Peak memory 233400 kb
Host smart-e34faee2-3e60-4170-b659-9a016b6068de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4056908481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.4056908481
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.566500347
Short name T141
Test name
Test status
Simulation time 10132637479 ps
CPU time 37.12 seconds
Started May 16 02:29:54 PM PDT 24
Finished May 16 02:30:34 PM PDT 24
Peak memory 200780 kb
Host smart-5453e379-fe05-42cd-8123-2fa3ec7dc068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566500347 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.566500347
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.1802940674
Short name T408
Test name
Test status
Simulation time 1415217419 ps
CPU time 471.87 seconds
Started May 16 02:29:55 PM PDT 24
Finished May 16 02:37:50 PM PDT 24
Peak memory 710708 kb
Host smart-16a4c363-e141-4c48-bf92-64a79e3d9e10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1802940674 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.1802940674
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_long_msg.1686757421
Short name T272
Test name
Test status
Simulation time 28713818793 ps
CPU time 95.1 seconds
Started May 16 02:29:55 PM PDT 24
Finished May 16 02:31:33 PM PDT 24
Peak memory 200760 kb
Host smart-fe0149a3-e06e-412c-88b3-6d310f3fdded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686757421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.1686757421
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.884529653
Short name T32
Test name
Test status
Simulation time 327304121 ps
CPU time 1.5 seconds
Started May 16 02:29:52 PM PDT 24
Finished May 16 02:29:57 PM PDT 24
Peak memory 200696 kb
Host smart-b05f6eae-fc75-4059-a810-5ccdad7bbd01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884529653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.884529653
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.1716486403
Short name T126
Test name
Test status
Simulation time 69617614 ps
CPU time 1.79 seconds
Started May 16 02:29:53 PM PDT 24
Finished May 16 02:29:58 PM PDT 24
Peak memory 200624 kb
Host smart-0051494c-d839-4b59-8899-033951e84080
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716486403 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.1716486403
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_test_hmac_vectors.489777917
Short name T357
Test name
Test status
Simulation time 220540263 ps
CPU time 1.23 seconds
Started May 16 02:29:54 PM PDT 24
Finished May 16 02:29:58 PM PDT 24
Peak memory 200560 kb
Host smart-05d2295b-c720-48c8-866b-a6b8d6645f9c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489777917 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 31.hmac_test_hmac_vectors.489777917
Directory /workspace/31.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha_vectors.1066741511
Short name T193
Test name
Test status
Simulation time 22469568751 ps
CPU time 408.06 seconds
Started May 16 02:29:54 PM PDT 24
Finished May 16 02:36:45 PM PDT 24
Peak memory 200672 kb
Host smart-927722a0-7f5d-41e2-9e11-56621ad52493
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066741511 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_sha_vectors.1066741511
Directory /workspace/31.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/32.hmac_alert_test.1798426093
Short name T447
Test name
Test status
Simulation time 14216824 ps
CPU time 0.59 seconds
Started May 16 02:30:06 PM PDT 24
Finished May 16 02:30:09 PM PDT 24
Peak memory 195388 kb
Host smart-e58fe0ee-724d-4dc4-8d94-b1e50c3e290e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798426093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.1798426093
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.1779606657
Short name T72
Test name
Test status
Simulation time 216338344 ps
CPU time 12.63 seconds
Started May 16 02:30:06 PM PDT 24
Finished May 16 02:30:20 PM PDT 24
Peak memory 200576 kb
Host smart-a422c9b2-c0da-405e-b153-2e48f531ccbf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1779606657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.1779606657
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.1724305762
Short name T255
Test name
Test status
Simulation time 1858596539 ps
CPU time 6.6 seconds
Started May 16 02:30:06 PM PDT 24
Finished May 16 02:30:15 PM PDT 24
Peak memory 200636 kb
Host smart-9c474475-2f9e-4b98-9a3c-5a5eb43a6b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724305762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.1724305762
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.2467711815
Short name T352
Test name
Test status
Simulation time 19972063560 ps
CPU time 811.3 seconds
Started May 16 02:30:05 PM PDT 24
Finished May 16 02:43:38 PM PDT 24
Peak memory 743964 kb
Host smart-c0653a84-2537-4dec-ba9a-bf2ca50fb982
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2467711815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.2467711815
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_long_msg.3899469355
Short name T194
Test name
Test status
Simulation time 5425998453 ps
CPU time 106.92 seconds
Started May 16 02:30:06 PM PDT 24
Finished May 16 02:31:56 PM PDT 24
Peak memory 200768 kb
Host smart-29158bc3-0c55-4c2d-b3eb-ba22f854b4c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899469355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.3899469355
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.1135552074
Short name T199
Test name
Test status
Simulation time 612850502 ps
CPU time 4.19 seconds
Started May 16 02:30:07 PM PDT 24
Finished May 16 02:30:13 PM PDT 24
Peak memory 200600 kb
Host smart-ae8feaac-b203-418b-a030-d5c71d9d01f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135552074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.1135552074
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_test_hmac_vectors.3614481010
Short name T1
Test name
Test status
Simulation time 210800906 ps
CPU time 1.12 seconds
Started May 16 02:30:05 PM PDT 24
Finished May 16 02:30:07 PM PDT 24
Peak memory 200240 kb
Host smart-6e12a393-b823-4b30-b0dd-a9cc2e519d3e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614481010 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.hmac_test_hmac_vectors.3614481010
Directory /workspace/32.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha_vectors.2058247124
Short name T226
Test name
Test status
Simulation time 97111590715 ps
CPU time 492.99 seconds
Started May 16 02:30:04 PM PDT 24
Finished May 16 02:38:17 PM PDT 24
Peak memory 200700 kb
Host smart-0788a480-8160-403b-856a-98b86ecf2c44
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058247124 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_sha_vectors.2058247124
Directory /workspace/32.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.2982493551
Short name T298
Test name
Test status
Simulation time 717516009 ps
CPU time 18.21 seconds
Started May 16 02:30:05 PM PDT 24
Finished May 16 02:30:24 PM PDT 24
Peak memory 200652 kb
Host smart-d1921d0c-2cda-4444-8c7c-2b4702e2094a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982493551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.2982493551
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.1591804562
Short name T61
Test name
Test status
Simulation time 34319623 ps
CPU time 0.6 seconds
Started May 16 02:30:06 PM PDT 24
Finished May 16 02:30:08 PM PDT 24
Peak memory 195356 kb
Host smart-c812aed3-6454-451f-828d-e74cedd0b3d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591804562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.1591804562
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.4209233151
Short name T46
Test name
Test status
Simulation time 1624509797 ps
CPU time 44.1 seconds
Started May 16 02:30:06 PM PDT 24
Finished May 16 02:30:52 PM PDT 24
Peak memory 224308 kb
Host smart-aea8bbb3-3d1a-469b-bd80-3b961d013304
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4209233151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.4209233151
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.1563492844
Short name T338
Test name
Test status
Simulation time 15943616255 ps
CPU time 43.76 seconds
Started May 16 02:30:07 PM PDT 24
Finished May 16 02:30:53 PM PDT 24
Peak memory 200820 kb
Host smart-cd3bec76-5bd6-46e3-9154-36804a2e11d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563492844 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.1563492844
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.3367915991
Short name T167
Test name
Test status
Simulation time 3299194100 ps
CPU time 916.93 seconds
Started May 16 02:30:05 PM PDT 24
Finished May 16 02:45:24 PM PDT 24
Peak memory 738060 kb
Host smart-f7794f85-ecac-4843-bff5-641a8959189b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3367915991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.3367915991
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.4066875465
Short name T18
Test name
Test status
Simulation time 1506615074 ps
CPU time 47.89 seconds
Started May 16 02:30:04 PM PDT 24
Finished May 16 02:30:53 PM PDT 24
Peak memory 200632 kb
Host smart-4e1db701-0d8c-4a39-943e-938735c0b71a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066875465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.4066875465
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.2219992641
Short name T169
Test name
Test status
Simulation time 3698945250 ps
CPU time 69.91 seconds
Started May 16 02:30:06 PM PDT 24
Finished May 16 02:31:18 PM PDT 24
Peak memory 200724 kb
Host smart-c4e8ce5e-346f-432a-b66a-91be29cb6cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219992641 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.2219992641
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.3979921439
Short name T284
Test name
Test status
Simulation time 2149407675 ps
CPU time 7.52 seconds
Started May 16 02:30:06 PM PDT 24
Finished May 16 02:30:16 PM PDT 24
Peak memory 200668 kb
Host smart-72cb4e55-3344-4b3c-bde2-e634fbc04128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979921439 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.3979921439
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_test_hmac_vectors.3491023355
Short name T85
Test name
Test status
Simulation time 32450792 ps
CPU time 1.26 seconds
Started May 16 02:30:11 PM PDT 24
Finished May 16 02:30:14 PM PDT 24
Peak memory 200552 kb
Host smart-5c70e8f5-51c3-4324-95f4-5d102930104c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491023355 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.hmac_test_hmac_vectors.3491023355
Directory /workspace/33.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha_vectors.1782607906
Short name T86
Test name
Test status
Simulation time 31509486158 ps
CPU time 435.9 seconds
Started May 16 02:30:09 PM PDT 24
Finished May 16 02:37:26 PM PDT 24
Peak memory 200644 kb
Host smart-1ccbb63b-131d-47aa-8753-575f3ef3506e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782607906 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_sha_vectors.1782607906
Directory /workspace/33.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/34.hmac_alert_test.1465143
Short name T178
Test name
Test status
Simulation time 45442477 ps
CPU time 0.59 seconds
Started May 16 02:30:09 PM PDT 24
Finished May 16 02:30:10 PM PDT 24
Peak memory 195968 kb
Host smart-308c933c-4d0b-439b-8034-d3bcb0537424
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.1465143
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.3444083168
Short name T139
Test name
Test status
Simulation time 245998500 ps
CPU time 16.29 seconds
Started May 16 02:30:06 PM PDT 24
Finished May 16 02:30:24 PM PDT 24
Peak memory 213400 kb
Host smart-2384b816-c63d-4826-a933-85593b8951e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3444083168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.3444083168
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.917765869
Short name T118
Test name
Test status
Simulation time 10364824736 ps
CPU time 50.95 seconds
Started May 16 02:30:04 PM PDT 24
Finished May 16 02:30:56 PM PDT 24
Peak memory 200740 kb
Host smart-c166d046-2a2d-4bdd-bbaf-16fbc45c95f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917765869 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.917765869
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.3119369334
Short name T146
Test name
Test status
Simulation time 6766834753 ps
CPU time 978.67 seconds
Started May 16 02:30:05 PM PDT 24
Finished May 16 02:46:25 PM PDT 24
Peak memory 751848 kb
Host smart-500ffab3-3f59-4e5c-9b75-a65ee79e3613
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3119369334 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.3119369334
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_long_msg.3673130713
Short name T301
Test name
Test status
Simulation time 1125725842 ps
CPU time 21.56 seconds
Started May 16 02:30:07 PM PDT 24
Finished May 16 02:30:30 PM PDT 24
Peak memory 200584 kb
Host smart-b2013f20-1678-480e-a4fc-881a4aae8fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673130713 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.3673130713
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.596296887
Short name T235
Test name
Test status
Simulation time 2410736150 ps
CPU time 6.68 seconds
Started May 16 02:30:07 PM PDT 24
Finished May 16 02:30:16 PM PDT 24
Peak memory 200756 kb
Host smart-e4e5b1f5-46f0-471d-80e9-8e90b1b37078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596296887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.596296887
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.503824451
Short name T192
Test name
Test status
Simulation time 42302083498 ps
CPU time 561.54 seconds
Started May 16 02:30:12 PM PDT 24
Finished May 16 02:39:35 PM PDT 24
Peak memory 221208 kb
Host smart-231d0fad-7a6a-4a95-9ada-d8bd3a487629
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503824451 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.503824451
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_test_hmac_vectors.2466016705
Short name T190
Test name
Test status
Simulation time 39897819 ps
CPU time 1.03 seconds
Started May 16 02:30:13 PM PDT 24
Finished May 16 02:30:15 PM PDT 24
Peak memory 200116 kb
Host smart-04a4deab-39d2-48ea-8cbf-79f392508f06
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466016705 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.hmac_test_hmac_vectors.2466016705
Directory /workspace/34.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha_vectors.1991513344
Short name T223
Test name
Test status
Simulation time 9038991632 ps
CPU time 532.6 seconds
Started May 16 02:30:09 PM PDT 24
Finished May 16 02:39:02 PM PDT 24
Peak memory 200692 kb
Host smart-35b3116e-3dba-43f9-992c-0cedfa4c7744
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991513344 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_sha_vectors.1991513344
Directory /workspace/34.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/35.hmac_alert_test.1369021148
Short name T164
Test name
Test status
Simulation time 31361558 ps
CPU time 0.61 seconds
Started May 16 02:30:19 PM PDT 24
Finished May 16 02:30:21 PM PDT 24
Peak memory 197140 kb
Host smart-6976379c-271d-497c-b4f1-8ddd3ad3d008
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369021148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.1369021148
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.3788356237
Short name T234
Test name
Test status
Simulation time 771115969 ps
CPU time 14.14 seconds
Started May 16 02:30:07 PM PDT 24
Finished May 16 02:30:23 PM PDT 24
Peak memory 208760 kb
Host smart-0ba28fe3-40f4-4563-aa61-4ec90eac9751
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3788356237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.3788356237
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.3394427180
Short name T93
Test name
Test status
Simulation time 6928176522 ps
CPU time 25.47 seconds
Started May 16 02:30:21 PM PDT 24
Finished May 16 02:30:48 PM PDT 24
Peak memory 200760 kb
Host smart-e8b83855-362e-4177-92e4-effc33282b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394427180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.3394427180
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.2316858563
Short name T214
Test name
Test status
Simulation time 4933906389 ps
CPU time 738.51 seconds
Started May 16 02:30:18 PM PDT 24
Finished May 16 02:42:38 PM PDT 24
Peak memory 727500 kb
Host smart-b1d44398-bd12-4def-814d-01e1de556fa3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2316858563 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.2316858563
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_long_msg.2425171153
Short name T74
Test name
Test status
Simulation time 3800163127 ps
CPU time 84.22 seconds
Started May 16 02:30:06 PM PDT 24
Finished May 16 02:31:33 PM PDT 24
Peak memory 200664 kb
Host smart-784f1fc1-1a50-44d1-a25c-f89edadb605c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425171153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.2425171153
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.1688061947
Short name T250
Test name
Test status
Simulation time 359913226 ps
CPU time 1.9 seconds
Started May 16 02:30:05 PM PDT 24
Finished May 16 02:30:08 PM PDT 24
Peak memory 200616 kb
Host smart-ef3f434f-9fd2-4c65-a24a-2a3a0753f230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688061947 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.1688061947
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.2816785391
Short name T41
Test name
Test status
Simulation time 28130703473 ps
CPU time 416.67 seconds
Started May 16 02:30:23 PM PDT 24
Finished May 16 02:37:21 PM PDT 24
Peak memory 200688 kb
Host smart-9351cb0b-9702-4b21-8548-06aa79c1920d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816785391 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.2816785391
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_test_hmac_vectors.2500313108
Short name T442
Test name
Test status
Simulation time 209386112 ps
CPU time 1.38 seconds
Started May 16 02:30:20 PM PDT 24
Finished May 16 02:30:22 PM PDT 24
Peak memory 199620 kb
Host smart-7676113a-2e6a-4ae1-8ce3-de910b11a78c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500313108 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.hmac_test_hmac_vectors.2500313108
Directory /workspace/35.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha_vectors.567011168
Short name T279
Test name
Test status
Simulation time 37224536629 ps
CPU time 513.11 seconds
Started May 16 02:30:19 PM PDT 24
Finished May 16 02:38:53 PM PDT 24
Peak memory 200656 kb
Host smart-8a7ef0ad-b706-4338-9147-9e19c6681ebf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567011168 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_sha_vectors.567011168
Directory /workspace/35.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/36.hmac_alert_test.1083893813
Short name T259
Test name
Test status
Simulation time 42589189 ps
CPU time 0.59 seconds
Started May 16 02:30:21 PM PDT 24
Finished May 16 02:30:24 PM PDT 24
Peak memory 195972 kb
Host smart-ba06dd81-8b7f-4d6b-ad8c-29a32dd35440
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083893813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.1083893813
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.1064500989
Short name T157
Test name
Test status
Simulation time 933677668 ps
CPU time 3.63 seconds
Started May 16 02:30:18 PM PDT 24
Finished May 16 02:30:23 PM PDT 24
Peak memory 200468 kb
Host smart-a9f97967-0171-46f3-a209-43f240aa998b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1064500989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.1064500989
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.960887420
Short name T370
Test name
Test status
Simulation time 233737047 ps
CPU time 11.98 seconds
Started May 16 02:30:21 PM PDT 24
Finished May 16 02:30:35 PM PDT 24
Peak memory 200596 kb
Host smart-932420c2-ac38-43ff-9b2f-538e216c3ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960887420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.960887420
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_long_msg.2081693827
Short name T28
Test name
Test status
Simulation time 3212473209 ps
CPU time 50.03 seconds
Started May 16 02:30:18 PM PDT 24
Finished May 16 02:31:09 PM PDT 24
Peak memory 200660 kb
Host smart-9367ee51-c803-49e5-929c-b459cf832803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081693827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.2081693827
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.2887238544
Short name T314
Test name
Test status
Simulation time 880373267 ps
CPU time 3.88 seconds
Started May 16 02:30:18 PM PDT 24
Finished May 16 02:30:23 PM PDT 24
Peak memory 200648 kb
Host smart-cf513ceb-0398-4e38-b38c-08ed634fcc34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887238544 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.2887238544
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_test_hmac_vectors.3205786208
Short name T248
Test name
Test status
Simulation time 124003920 ps
CPU time 1.26 seconds
Started May 16 02:30:22 PM PDT 24
Finished May 16 02:30:25 PM PDT 24
Peak memory 200552 kb
Host smart-67ea6ef5-f1e4-4530-985f-524eb821ecec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205786208 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.hmac_test_hmac_vectors.3205786208
Directory /workspace/36.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha_vectors.54488400
Short name T375
Test name
Test status
Simulation time 15048822036 ps
CPU time 448.38 seconds
Started May 16 02:30:21 PM PDT 24
Finished May 16 02:37:52 PM PDT 24
Peak memory 200736 kb
Host smart-30257bad-96c6-4914-80d1-42a4d8cbe768
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54488400 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_sha_vectors.54488400
Directory /workspace/36.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/37.hmac_alert_test.4158356270
Short name T150
Test name
Test status
Simulation time 14604181 ps
CPU time 0.62 seconds
Started May 16 02:30:36 PM PDT 24
Finished May 16 02:30:39 PM PDT 24
Peak memory 196356 kb
Host smart-bdf17380-16df-466a-876e-c4a005833141
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158356270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.4158356270
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.2370259579
Short name T349
Test name
Test status
Simulation time 587548771 ps
CPU time 18.11 seconds
Started May 16 02:30:19 PM PDT 24
Finished May 16 02:30:39 PM PDT 24
Peak memory 215396 kb
Host smart-db898546-8078-4221-9e2a-90ba0937e3a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2370259579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.2370259579
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.1268094115
Short name T112
Test name
Test status
Simulation time 2988708048 ps
CPU time 825.76 seconds
Started May 16 02:30:19 PM PDT 24
Finished May 16 02:44:06 PM PDT 24
Peak memory 728636 kb
Host smart-4d3d5c55-8189-4dd6-b906-fb966d5efd8a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1268094115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.1268094115
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_long_msg.1682883474
Short name T110
Test name
Test status
Simulation time 1244352950 ps
CPU time 28.42 seconds
Started May 16 02:30:20 PM PDT 24
Finished May 16 02:30:50 PM PDT 24
Peak memory 200636 kb
Host smart-16b91bbe-2487-45e7-a55d-32d621ea5ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682883474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.1682883474
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.300863675
Short name T156
Test name
Test status
Simulation time 491564537 ps
CPU time 6.66 seconds
Started May 16 02:30:20 PM PDT 24
Finished May 16 02:30:28 PM PDT 24
Peak memory 200596 kb
Host smart-0d981586-b93e-4fb3-a999-d1542f1c4087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300863675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.300863675
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_test_hmac_vectors.575485560
Short name T183
Test name
Test status
Simulation time 26910656 ps
CPU time 1.02 seconds
Started May 16 02:30:20 PM PDT 24
Finished May 16 02:30:23 PM PDT 24
Peak memory 199048 kb
Host smart-959a3ae1-e054-4a86-94d9-7a2e3dd5b878
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575485560 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 37.hmac_test_hmac_vectors.575485560
Directory /workspace/37.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha_vectors.1662287396
Short name T293
Test name
Test status
Simulation time 7655730409 ps
CPU time 453.6 seconds
Started May 16 02:30:21 PM PDT 24
Finished May 16 02:37:56 PM PDT 24
Peak memory 200696 kb
Host smart-92564243-c75e-4890-96bb-bab5e5b29963
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662287396 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_sha_vectors.1662287396
Directory /workspace/37.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/38.hmac_alert_test.3237591235
Short name T455
Test name
Test status
Simulation time 56580375 ps
CPU time 0.59 seconds
Started May 16 02:30:36 PM PDT 24
Finished May 16 02:30:39 PM PDT 24
Peak memory 195320 kb
Host smart-0850999a-c422-453b-bf5e-f521d6570f3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237591235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.3237591235
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.4055586336
Short name T140
Test name
Test status
Simulation time 2202113922 ps
CPU time 22.07 seconds
Started May 16 02:30:38 PM PDT 24
Finished May 16 02:31:02 PM PDT 24
Peak memory 224624 kb
Host smart-25876192-757c-4d66-9750-ddb59eb8dd6d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4055586336 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.4055586336
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.1623203229
Short name T422
Test name
Test status
Simulation time 201586585 ps
CPU time 3.19 seconds
Started May 16 02:30:36 PM PDT 24
Finished May 16 02:30:41 PM PDT 24
Peak memory 200384 kb
Host smart-2996b242-d2c5-429d-9e6c-35a383b4531d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623203229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.1623203229
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.3306547374
Short name T450
Test name
Test status
Simulation time 3738467536 ps
CPU time 1049.6 seconds
Started May 16 02:30:41 PM PDT 24
Finished May 16 02:48:12 PM PDT 24
Peak memory 717304 kb
Host smart-81ace531-f7c9-478b-9258-5fe6c57b95ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3306547374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.3306547374
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_long_msg.3496281996
Short name T396
Test name
Test status
Simulation time 8787262343 ps
CPU time 39.62 seconds
Started May 16 02:30:33 PM PDT 24
Finished May 16 02:31:15 PM PDT 24
Peak memory 200716 kb
Host smart-84ee17ed-fd53-4606-886f-b2799e1cb1ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496281996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.3496281996
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.3518756983
Short name T443
Test name
Test status
Simulation time 328673544 ps
CPU time 2.48 seconds
Started May 16 02:30:37 PM PDT 24
Finished May 16 02:30:42 PM PDT 24
Peak memory 200572 kb
Host smart-798ff169-97d7-479c-b5c0-5c126a165a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518756983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.3518756983
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_test_hmac_vectors.2905716195
Short name T386
Test name
Test status
Simulation time 134849291 ps
CPU time 1.04 seconds
Started May 16 02:30:33 PM PDT 24
Finished May 16 02:30:36 PM PDT 24
Peak memory 200244 kb
Host smart-74f9ddd8-a0ce-41d5-8fb2-0e67abbeacbe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905716195 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.hmac_test_hmac_vectors.2905716195
Directory /workspace/38.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha_vectors.293931052
Short name T29
Test name
Test status
Simulation time 28416911298 ps
CPU time 538.18 seconds
Started May 16 02:30:37 PM PDT 24
Finished May 16 02:39:37 PM PDT 24
Peak memory 200664 kb
Host smart-ae6d1638-1b9e-4b13-9e7a-1325bbad4be2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293931052 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_sha_vectors.293931052
Directory /workspace/38.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/39.hmac_alert_test.3135319417
Short name T449
Test name
Test status
Simulation time 59426057 ps
CPU time 0.63 seconds
Started May 16 02:30:34 PM PDT 24
Finished May 16 02:30:36 PM PDT 24
Peak memory 196428 kb
Host smart-335c803b-31f8-472f-8c99-5bd11978594c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135319417 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.3135319417
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.3909715004
Short name T423
Test name
Test status
Simulation time 5013119834 ps
CPU time 34.46 seconds
Started May 16 02:30:41 PM PDT 24
Finished May 16 02:31:16 PM PDT 24
Peak memory 200756 kb
Host smart-9bb3d4df-dd66-4776-b0d0-368aa7265d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909715004 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.3909715004
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.2682161508
Short name T305
Test name
Test status
Simulation time 41989057327 ps
CPU time 825.14 seconds
Started May 16 02:30:33 PM PDT 24
Finished May 16 02:44:20 PM PDT 24
Peak memory 720692 kb
Host smart-09141354-8537-44c4-ac20-bd5dc51f9ca2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2682161508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.2682161508
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_long_msg.1010771921
Short name T222
Test name
Test status
Simulation time 19702343459 ps
CPU time 67.83 seconds
Started May 16 02:30:32 PM PDT 24
Finished May 16 02:31:41 PM PDT 24
Peak memory 200728 kb
Host smart-36d1d2c5-32aa-4801-b93d-5940e80e2c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010771921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.1010771921
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.2637474168
Short name T257
Test name
Test status
Simulation time 1510976115 ps
CPU time 4.97 seconds
Started May 16 02:30:35 PM PDT 24
Finished May 16 02:30:42 PM PDT 24
Peak memory 200664 kb
Host smart-2368ede1-02cc-4e9b-8b1b-114c86986423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637474168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.2637474168
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_test_hmac_vectors.4221932831
Short name T453
Test name
Test status
Simulation time 81363292 ps
CPU time 1.43 seconds
Started May 16 02:30:36 PM PDT 24
Finished May 16 02:30:40 PM PDT 24
Peak memory 200548 kb
Host smart-b307ae70-1d8e-47b5-a7bb-dd6f7035e5e7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221932831 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.hmac_test_hmac_vectors.4221932831
Directory /workspace/39.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha_vectors.2484071710
Short name T402
Test name
Test status
Simulation time 53479580723 ps
CPU time 479.56 seconds
Started May 16 02:30:32 PM PDT 24
Finished May 16 02:38:33 PM PDT 24
Peak memory 200648 kb
Host smart-c5d652f0-2373-4148-b8db-c0b01ab083c3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484071710 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_sha_vectors.2484071710
Directory /workspace/39.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/4.hmac_alert_test.3568048915
Short name T282
Test name
Test status
Simulation time 31749837 ps
CPU time 0.58 seconds
Started May 16 02:28:50 PM PDT 24
Finished May 16 02:28:53 PM PDT 24
Peak memory 195292 kb
Host smart-04ffa584-70b8-4fd1-a76d-d636c1bdec05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568048915 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.3568048915
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.3683123805
Short name T285
Test name
Test status
Simulation time 1598442817 ps
CPU time 46.64 seconds
Started May 16 02:28:48 PM PDT 24
Finished May 16 02:29:37 PM PDT 24
Peak memory 225180 kb
Host smart-37236ded-76b4-48b4-8d15-03b2cd130430
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3683123805 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.3683123805
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.4210352265
Short name T426
Test name
Test status
Simulation time 4038639137 ps
CPU time 38.45 seconds
Started May 16 02:28:56 PM PDT 24
Finished May 16 02:29:38 PM PDT 24
Peak memory 200752 kb
Host smart-af4988ff-db64-4800-88fc-7442bb59b25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210352265 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.4210352265
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.469854301
Short name T64
Test name
Test status
Simulation time 351640685 ps
CPU time 54.11 seconds
Started May 16 02:28:46 PM PDT 24
Finished May 16 02:29:43 PM PDT 24
Peak memory 342072 kb
Host smart-441affc9-f975-4ed3-8483-18ce4c619936
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=469854301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.469854301
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_long_msg.1924109409
Short name T377
Test name
Test status
Simulation time 5827641766 ps
CPU time 10.95 seconds
Started May 16 02:28:49 PM PDT 24
Finished May 16 02:29:03 PM PDT 24
Peak memory 200708 kb
Host smart-db5f393d-1fba-4af6-af59-d4dde7c936c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924109409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.1924109409
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.2188316724
Short name T30
Test name
Test status
Simulation time 1334690971 ps
CPU time 0.98 seconds
Started May 16 02:28:55 PM PDT 24
Finished May 16 02:28:58 PM PDT 24
Peak memory 218956 kb
Host smart-a270b84b-d250-41b1-a628-f8dcdd7eff8f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188316724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.2188316724
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.3650288133
Short name T373
Test name
Test status
Simulation time 1856232980 ps
CPU time 5.78 seconds
Started May 16 02:28:48 PM PDT 24
Finished May 16 02:28:56 PM PDT 24
Peak memory 200696 kb
Host smart-5582327b-03d5-46f9-864a-8b46fa5e74a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650288133 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.3650288133
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_test_hmac_vectors.3084744568
Short name T191
Test name
Test status
Simulation time 28768695 ps
CPU time 1.02 seconds
Started May 16 02:28:49 PM PDT 24
Finished May 16 02:28:53 PM PDT 24
Peak memory 199436 kb
Host smart-9cb5f79c-9c0b-4a4b-8513-38133b78a84f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084744568 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.hmac_test_hmac_vectors.3084744568
Directory /workspace/4.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha_vectors.2337145775
Short name T302
Test name
Test status
Simulation time 7766690847 ps
CPU time 443.04 seconds
Started May 16 02:28:42 PM PDT 24
Finished May 16 02:36:07 PM PDT 24
Peak memory 200616 kb
Host smart-06d474cd-5190-4d41-8cdc-4c7851ce151b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337145775 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha_vectors.2337145775
Directory /workspace/4.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/40.hmac_alert_test.4160275724
Short name T227
Test name
Test status
Simulation time 14494686 ps
CPU time 0.62 seconds
Started May 16 02:30:33 PM PDT 24
Finished May 16 02:30:36 PM PDT 24
Peak memory 196028 kb
Host smart-96bec142-2cf5-406f-aa73-1bc6c2324f72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160275724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.4160275724
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.1497250458
Short name T468
Test name
Test status
Simulation time 7286017354 ps
CPU time 41.79 seconds
Started May 16 02:30:33 PM PDT 24
Finished May 16 02:31:16 PM PDT 24
Peak memory 217180 kb
Host smart-db5dcf75-4eb0-436e-8291-8d6178e1a597
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1497250458 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.1497250458
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.1083990661
Short name T176
Test name
Test status
Simulation time 59284641 ps
CPU time 3.01 seconds
Started May 16 02:30:36 PM PDT 24
Finished May 16 02:30:41 PM PDT 24
Peak memory 200548 kb
Host smart-04f20136-7f95-4461-8538-baa934b95f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083990661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.1083990661
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.3973705666
Short name T147
Test name
Test status
Simulation time 15980770689 ps
CPU time 1151.36 seconds
Started May 16 02:30:41 PM PDT 24
Finished May 16 02:49:53 PM PDT 24
Peak memory 739712 kb
Host smart-f8082917-00e6-470b-b4a1-fe44f45ccdba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3973705666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.3973705666
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_long_msg.3705157012
Short name T320
Test name
Test status
Simulation time 627058727 ps
CPU time 22.06 seconds
Started May 16 02:30:39 PM PDT 24
Finished May 16 02:31:02 PM PDT 24
Peak memory 200612 kb
Host smart-d4b06e52-e81d-44f2-866a-e277de4535ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705157012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.3705157012
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.2915498978
Short name T16
Test name
Test status
Simulation time 163307206 ps
CPU time 2.38 seconds
Started May 16 02:30:35 PM PDT 24
Finished May 16 02:30:40 PM PDT 24
Peak memory 200636 kb
Host smart-82eba111-c410-4eb6-8dca-8055c13c593a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915498978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.2915498978
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_test_hmac_vectors.940064871
Short name T171
Test name
Test status
Simulation time 56114552 ps
CPU time 1.12 seconds
Started May 16 02:30:33 PM PDT 24
Finished May 16 02:30:35 PM PDT 24
Peak memory 200328 kb
Host smart-bcfa4f6e-150b-45c4-b0ec-ac53b915ddc5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940064871 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 40.hmac_test_hmac_vectors.940064871
Directory /workspace/40.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha_vectors.1853324177
Short name T337
Test name
Test status
Simulation time 8003809004 ps
CPU time 456.47 seconds
Started May 16 02:30:36 PM PDT 24
Finished May 16 02:38:15 PM PDT 24
Peak memory 200740 kb
Host smart-5b311882-47db-45c9-be51-c9c26f1dca6d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853324177 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_sha_vectors.1853324177
Directory /workspace/40.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/41.hmac_alert_test.1805780225
Short name T26
Test name
Test status
Simulation time 13841584 ps
CPU time 0.59 seconds
Started May 16 02:30:45 PM PDT 24
Finished May 16 02:30:48 PM PDT 24
Peak memory 196372 kb
Host smart-018ac222-4cb2-49f9-862a-cde7d76dd718
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805780225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.1805780225
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.1695303549
Short name T308
Test name
Test status
Simulation time 11330205512 ps
CPU time 47.93 seconds
Started May 16 02:30:43 PM PDT 24
Finished May 16 02:31:33 PM PDT 24
Peak memory 200768 kb
Host smart-40fb3131-b087-461a-9a20-9caecfa79a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695303549 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.1695303549
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.1607481325
Short name T8
Test name
Test status
Simulation time 2063025956 ps
CPU time 377.6 seconds
Started May 16 02:30:46 PM PDT 24
Finished May 16 02:37:06 PM PDT 24
Peak memory 615184 kb
Host smart-c93e1162-e694-4c16-b977-2ebdbcac78bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1607481325 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.1607481325
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.3473367404
Short name T189
Test name
Test status
Simulation time 12051183459 ps
CPU time 38.21 seconds
Started May 16 02:30:43 PM PDT 24
Finished May 16 02:31:23 PM PDT 24
Peak memory 200544 kb
Host smart-037a9ecc-4a19-4461-a1dc-900ad1a2f8ba
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473367404 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.3473367404
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.3037983093
Short name T213
Test name
Test status
Simulation time 1291362083 ps
CPU time 18.22 seconds
Started May 16 02:30:43 PM PDT 24
Finished May 16 02:31:03 PM PDT 24
Peak memory 200604 kb
Host smart-58a140be-d692-42ef-8acd-34d7e137d8c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037983093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.3037983093
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.3725769921
Short name T362
Test name
Test status
Simulation time 197641754 ps
CPU time 3.26 seconds
Started May 16 02:30:43 PM PDT 24
Finished May 16 02:30:48 PM PDT 24
Peak memory 200596 kb
Host smart-b864d375-4dec-4938-8560-c54caed49e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725769921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.3725769921
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_test_hmac_vectors.502772045
Short name T278
Test name
Test status
Simulation time 50811729 ps
CPU time 1 seconds
Started May 16 02:30:50 PM PDT 24
Finished May 16 02:30:53 PM PDT 24
Peak memory 199352 kb
Host smart-bc2e008e-f24a-4f1e-9951-f9a016d83bee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502772045 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 41.hmac_test_hmac_vectors.502772045
Directory /workspace/41.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha_vectors.3441260585
Short name T358
Test name
Test status
Simulation time 33196320200 ps
CPU time 497.81 seconds
Started May 16 02:30:43 PM PDT 24
Finished May 16 02:39:02 PM PDT 24
Peak memory 200692 kb
Host smart-1e4bc44f-d334-4e0b-a2d3-34683afcc1ba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441260585 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_sha_vectors.3441260585
Directory /workspace/41.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.317143062
Short name T409
Test name
Test status
Simulation time 1155200923 ps
CPU time 5.2 seconds
Started May 16 02:30:41 PM PDT 24
Finished May 16 02:30:48 PM PDT 24
Peak memory 200556 kb
Host smart-3657dfc9-8022-4dff-92f7-3cb86c6a9b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317143062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.317143062
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.1148853388
Short name T296
Test name
Test status
Simulation time 17407014 ps
CPU time 0.61 seconds
Started May 16 02:30:46 PM PDT 24
Finished May 16 02:30:50 PM PDT 24
Peak memory 196380 kb
Host smart-22afc76a-ee32-41ba-8fa5-1edd9bc20df5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148853388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.1148853388
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.1683600772
Short name T23
Test name
Test status
Simulation time 388277004 ps
CPU time 8.07 seconds
Started May 16 02:30:43 PM PDT 24
Finished May 16 02:30:53 PM PDT 24
Peak memory 200580 kb
Host smart-7a1ca315-fa6d-486c-9a47-6e73844b9f3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1683600772 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.1683600772
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.2795655644
Short name T142
Test name
Test status
Simulation time 1180308987 ps
CPU time 33.8 seconds
Started May 16 02:30:44 PM PDT 24
Finished May 16 02:31:20 PM PDT 24
Peak memory 200652 kb
Host smart-186ce0ef-8acc-466e-8e75-54be9b293911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795655644 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.2795655644
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.2638711524
Short name T344
Test name
Test status
Simulation time 27936092 ps
CPU time 0.74 seconds
Started May 16 02:30:50 PM PDT 24
Finished May 16 02:30:53 PM PDT 24
Peak memory 198060 kb
Host smart-05c78f17-10d0-44cc-9450-f1e7fc78db98
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2638711524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.2638711524
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.4160122080
Short name T27
Test name
Test status
Simulation time 1021296086 ps
CPU time 11.12 seconds
Started May 16 02:30:44 PM PDT 24
Finished May 16 02:30:57 PM PDT 24
Peak memory 200416 kb
Host smart-d48ce4d5-0952-4e58-ada9-e62ab4c13f7b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160122080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.4160122080
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.1192869678
Short name T297
Test name
Test status
Simulation time 1083636816 ps
CPU time 60.01 seconds
Started May 16 02:30:42 PM PDT 24
Finished May 16 02:31:43 PM PDT 24
Peak memory 200608 kb
Host smart-57b1aa5e-da9e-4537-b7ad-41b4b92bac01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192869678 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.1192869678
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.3674981575
Short name T329
Test name
Test status
Simulation time 97291820 ps
CPU time 0.9 seconds
Started May 16 02:30:44 PM PDT 24
Finished May 16 02:30:47 PM PDT 24
Peak memory 199684 kb
Host smart-b9233b39-2182-4a89-a93a-6fde45543584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674981575 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.3674981575
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_test_hmac_vectors.1943593292
Short name T394
Test name
Test status
Simulation time 28093396 ps
CPU time 1.07 seconds
Started May 16 02:30:50 PM PDT 24
Finished May 16 02:30:54 PM PDT 24
Peak memory 200148 kb
Host smart-1b43a4ef-1088-4104-afa0-275df2a7e2d2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943593292 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.hmac_test_hmac_vectors.1943593292
Directory /workspace/42.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha_vectors.845333539
Short name T195
Test name
Test status
Simulation time 107888501632 ps
CPU time 497.01 seconds
Started May 16 02:30:48 PM PDT 24
Finished May 16 02:39:08 PM PDT 24
Peak memory 200656 kb
Host smart-8f2682a7-926d-4794-a3de-04a95b5149bb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845333539 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_sha_vectors.845333539
Directory /workspace/42.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.1595787103
Short name T35
Test name
Test status
Simulation time 346352151 ps
CPU time 16.12 seconds
Started May 16 02:30:42 PM PDT 24
Finished May 16 02:30:59 PM PDT 24
Peak memory 200576 kb
Host smart-a482bde9-16ca-4edb-9b3b-2099e0ca2967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595787103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.1595787103
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.4236285386
Short name T407
Test name
Test status
Simulation time 38893215 ps
CPU time 0.59 seconds
Started May 16 02:30:44 PM PDT 24
Finished May 16 02:30:47 PM PDT 24
Peak memory 195344 kb
Host smart-e5af5afd-495e-42c9-be5e-385c7f38b9d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236285386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.4236285386
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.735054703
Short name T215
Test name
Test status
Simulation time 984966937 ps
CPU time 54.33 seconds
Started May 16 02:30:47 PM PDT 24
Finished May 16 02:31:44 PM PDT 24
Peak memory 227016 kb
Host smart-19d8d52a-380b-4a68-8cf6-03e7ce0b7d14
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=735054703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.735054703
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.3164761254
Short name T388
Test name
Test status
Simulation time 5950502961 ps
CPU time 32.19 seconds
Started May 16 02:30:43 PM PDT 24
Finished May 16 02:31:18 PM PDT 24
Peak memory 200756 kb
Host smart-1c95fab7-7a15-4700-b6ea-c2a59fb7c71a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164761254 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.3164761254
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.2248627969
Short name T381
Test name
Test status
Simulation time 2771835639 ps
CPU time 157.14 seconds
Started May 16 02:30:46 PM PDT 24
Finished May 16 02:33:26 PM PDT 24
Peak memory 586212 kb
Host smart-59b3e958-856c-43f8-8001-cde1010504ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2248627969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.2248627969
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_long_msg.4161435412
Short name T276
Test name
Test status
Simulation time 81718701671 ps
CPU time 112.31 seconds
Started May 16 02:30:46 PM PDT 24
Finished May 16 02:32:41 PM PDT 24
Peak memory 200732 kb
Host smart-05bdc02d-c726-4a17-a1d5-f7b45d29b7ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161435412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.4161435412
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.3042824673
Short name T144
Test name
Test status
Simulation time 272390971 ps
CPU time 4.63 seconds
Started May 16 02:30:50 PM PDT 24
Finished May 16 02:30:57 PM PDT 24
Peak memory 200628 kb
Host smart-3065c617-4294-482e-bd98-12da37c8c991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042824673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.3042824673
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_test_hmac_vectors.3309702609
Short name T333
Test name
Test status
Simulation time 121270916 ps
CPU time 1.24 seconds
Started May 16 02:30:48 PM PDT 24
Finished May 16 02:30:51 PM PDT 24
Peak memory 200568 kb
Host smart-431f413b-ea7a-446e-9807-ec52c30da55c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309702609 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.hmac_test_hmac_vectors.3309702609
Directory /workspace/43.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha_vectors.2475041123
Short name T107
Test name
Test status
Simulation time 249509709937 ps
CPU time 576.6 seconds
Started May 16 02:30:44 PM PDT 24
Finished May 16 02:40:23 PM PDT 24
Peak memory 200748 kb
Host smart-67a63391-fd7b-4680-b78c-0960283c7a47
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475041123 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_sha_vectors.2475041123
Directory /workspace/43.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/44.hmac_alert_test.743549242
Short name T432
Test name
Test status
Simulation time 44632951 ps
CPU time 0.61 seconds
Started May 16 02:30:56 PM PDT 24
Finished May 16 02:30:59 PM PDT 24
Peak memory 196008 kb
Host smart-2c140eae-1eb9-43f4-8d22-914433ff0263
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743549242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.743549242
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.2790639396
Short name T92
Test name
Test status
Simulation time 1016737074 ps
CPU time 11.93 seconds
Started May 16 02:30:44 PM PDT 24
Finished May 16 02:30:58 PM PDT 24
Peak memory 214972 kb
Host smart-985a3e2d-e5a3-4f29-bdf8-1ba75a8fa764
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2790639396 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.2790639396
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.751524965
Short name T414
Test name
Test status
Simulation time 3254044836 ps
CPU time 29.89 seconds
Started May 16 02:30:45 PM PDT 24
Finished May 16 02:31:17 PM PDT 24
Peak memory 200740 kb
Host smart-74a21333-3d12-4191-884e-c11701eb6cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751524965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.751524965
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.3910079961
Short name T155
Test name
Test status
Simulation time 1051522462 ps
CPU time 224.4 seconds
Started May 16 02:30:48 PM PDT 24
Finished May 16 02:34:35 PM PDT 24
Peak memory 460836 kb
Host smart-ba5e43ad-197b-4182-bcf3-21ee0e4e4d4a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3910079961 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.3910079961
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_long_msg.1963371055
Short name T457
Test name
Test status
Simulation time 2438922355 ps
CPU time 36.9 seconds
Started May 16 02:30:43 PM PDT 24
Finished May 16 02:31:22 PM PDT 24
Peak memory 200772 kb
Host smart-706ed2d4-c873-4a10-92e6-9ccf20eba24f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963371055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.1963371055
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.2507069603
Short name T342
Test name
Test status
Simulation time 212055630 ps
CPU time 6.45 seconds
Started May 16 02:30:46 PM PDT 24
Finished May 16 02:30:55 PM PDT 24
Peak memory 200596 kb
Host smart-46b2d9cb-45e5-42d7-8eea-a6ad7fea8640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507069603 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.2507069603
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_test_hmac_vectors.3887328415
Short name T406
Test name
Test status
Simulation time 210668127 ps
CPU time 1.16 seconds
Started May 16 02:30:45 PM PDT 24
Finished May 16 02:30:48 PM PDT 24
Peak memory 200624 kb
Host smart-cea7132e-5d83-414e-be44-c684481b06b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887328415 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.hmac_test_hmac_vectors.3887328415
Directory /workspace/44.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha_vectors.3287253932
Short name T335
Test name
Test status
Simulation time 62088441670 ps
CPU time 417.53 seconds
Started May 16 02:30:45 PM PDT 24
Finished May 16 02:37:45 PM PDT 24
Peak memory 200676 kb
Host smart-ed351de3-1edc-4b65-be78-3147243138a9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287253932 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_sha_vectors.3287253932
Directory /workspace/44.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/45.hmac_alert_test.3260416908
Short name T253
Test name
Test status
Simulation time 10746841 ps
CPU time 0.59 seconds
Started May 16 02:30:55 PM PDT 24
Finished May 16 02:30:59 PM PDT 24
Peak memory 195348 kb
Host smart-34a14652-8175-404b-8d3a-da43e15cdcdf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260416908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.3260416908
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.1462927118
Short name T428
Test name
Test status
Simulation time 939587057 ps
CPU time 44.69 seconds
Started May 16 02:30:55 PM PDT 24
Finished May 16 02:31:43 PM PDT 24
Peak memory 216360 kb
Host smart-fe590bb2-12dd-4d41-86e0-20c8b5617f6e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1462927118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.1462927118
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.2310250564
Short name T113
Test name
Test status
Simulation time 6022150956 ps
CPU time 44.77 seconds
Started May 16 02:30:56 PM PDT 24
Finished May 16 02:31:43 PM PDT 24
Peak memory 200684 kb
Host smart-2eb8ac97-bb39-46a9-b50b-7b678d0afabd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310250564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.2310250564
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.1402157148
Short name T398
Test name
Test status
Simulation time 2409382101 ps
CPU time 740.32 seconds
Started May 16 02:30:56 PM PDT 24
Finished May 16 02:43:19 PM PDT 24
Peak memory 754888 kb
Host smart-6899a7d0-4384-49d1-a1b7-c9349f9b197c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1402157148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.1402157148
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_long_msg.3552078860
Short name T440
Test name
Test status
Simulation time 389615432 ps
CPU time 6.24 seconds
Started May 16 02:30:56 PM PDT 24
Finished May 16 02:31:05 PM PDT 24
Peak memory 200620 kb
Host smart-5efccdf8-6b4d-478a-99fd-1dce4f3cef1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552078860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.3552078860
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.1841638036
Short name T403
Test name
Test status
Simulation time 302396997 ps
CPU time 2.37 seconds
Started May 16 02:30:56 PM PDT 24
Finished May 16 02:31:01 PM PDT 24
Peak memory 200640 kb
Host smart-f866ed03-125f-457c-b1e0-f85c060571c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841638036 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.1841638036
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_test_hmac_vectors.677815418
Short name T280
Test name
Test status
Simulation time 395445093 ps
CPU time 1.54 seconds
Started May 16 02:30:55 PM PDT 24
Finished May 16 02:30:59 PM PDT 24
Peak memory 200484 kb
Host smart-c807e2af-a3aa-4cc7-901b-92b36a91d036
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677815418 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 45.hmac_test_hmac_vectors.677815418
Directory /workspace/45.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha_vectors.1518130363
Short name T200
Test name
Test status
Simulation time 27600924737 ps
CPU time 512.81 seconds
Started May 16 02:30:56 PM PDT 24
Finished May 16 02:39:32 PM PDT 24
Peak memory 200652 kb
Host smart-cb6b816e-1cb2-400d-85b5-b7c7cf465b65
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518130363 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_sha_vectors.1518130363
Directory /workspace/45.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.3153990660
Short name T378
Test name
Test status
Simulation time 1076888534 ps
CPU time 33.28 seconds
Started May 16 02:31:07 PM PDT 24
Finished May 16 02:31:43 PM PDT 24
Peak memory 225188 kb
Host smart-2af13af3-bd78-4d37-93e2-4414d4cfe5bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3153990660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.3153990660
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.1407286024
Short name T368
Test name
Test status
Simulation time 6214559474 ps
CPU time 59.4 seconds
Started May 16 02:31:06 PM PDT 24
Finished May 16 02:32:07 PM PDT 24
Peak memory 200764 kb
Host smart-b7652818-4289-4c56-a629-aea4b933707e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407286024 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.1407286024
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.3460889354
Short name T326
Test name
Test status
Simulation time 3788530947 ps
CPU time 1032.16 seconds
Started May 16 02:31:08 PM PDT 24
Finished May 16 02:48:22 PM PDT 24
Peak memory 749888 kb
Host smart-3193e6b0-c01b-4ddd-849e-ac4acd529ddc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3460889354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.3460889354
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_long_msg.1589773669
Short name T397
Test name
Test status
Simulation time 4348533192 ps
CPU time 48.26 seconds
Started May 16 02:30:57 PM PDT 24
Finished May 16 02:31:48 PM PDT 24
Peak memory 200736 kb
Host smart-d4426c05-10e7-48e1-8a7e-2f5150eba20e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589773669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.1589773669
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.3936973499
Short name T318
Test name
Test status
Simulation time 328501217 ps
CPU time 5.14 seconds
Started May 16 02:30:58 PM PDT 24
Finished May 16 02:31:05 PM PDT 24
Peak memory 200616 kb
Host smart-c431bd2a-f76a-4481-b72c-95c7ba7a24c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936973499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.3936973499
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.3217634194
Short name T261
Test name
Test status
Simulation time 16252852835 ps
CPU time 79.07 seconds
Started May 16 02:31:06 PM PDT 24
Finished May 16 02:32:27 PM PDT 24
Peak memory 200768 kb
Host smart-561ede40-26ab-4879-8748-07a8dda4964c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217634194 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.3217634194
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_test_hmac_vectors.257221852
Short name T382
Test name
Test status
Simulation time 48753919 ps
CPU time 1.07 seconds
Started May 16 02:31:06 PM PDT 24
Finished May 16 02:31:09 PM PDT 24
Peak memory 200392 kb
Host smart-218846bf-cc93-4f19-a70e-ae277e4bd143
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257221852 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 46.hmac_test_hmac_vectors.257221852
Directory /workspace/46.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha_vectors.3320671293
Short name T400
Test name
Test status
Simulation time 8619210654 ps
CPU time 451.21 seconds
Started May 16 02:31:09 PM PDT 24
Finished May 16 02:38:42 PM PDT 24
Peak memory 200664 kb
Host smart-7d802619-f84e-4e81-b93f-9383688e2087
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320671293 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_sha_vectors.3320671293
Directory /workspace/46.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/47.hmac_alert_test.188084071
Short name T436
Test name
Test status
Simulation time 39497864 ps
CPU time 0.59 seconds
Started May 16 02:31:09 PM PDT 24
Finished May 16 02:31:12 PM PDT 24
Peak memory 196024 kb
Host smart-ee1fbeda-115f-4925-bc2b-9d842f3d042e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188084071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.188084071
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.1408295959
Short name T306
Test name
Test status
Simulation time 1583019226 ps
CPU time 38.57 seconds
Started May 16 02:31:09 PM PDT 24
Finished May 16 02:31:50 PM PDT 24
Peak memory 212052 kb
Host smart-2924f2f9-33a2-4503-954c-0acba688f907
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1408295959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.1408295959
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.2220927916
Short name T228
Test name
Test status
Simulation time 10465302067 ps
CPU time 22.83 seconds
Started May 16 02:31:07 PM PDT 24
Finished May 16 02:31:31 PM PDT 24
Peak memory 200768 kb
Host smart-e37d41c4-4242-48bd-863d-4f54f4f8f618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220927916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.2220927916
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.1655079162
Short name T60
Test name
Test status
Simulation time 61382600 ps
CPU time 3.23 seconds
Started May 16 02:31:08 PM PDT 24
Finished May 16 02:31:13 PM PDT 24
Peak memory 208864 kb
Host smart-7d30d330-0fc3-47e1-84fd-a4d15205a182
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1655079162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.1655079162
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_long_msg.156981412
Short name T65
Test name
Test status
Simulation time 312014565 ps
CPU time 18.38 seconds
Started May 16 02:31:22 PM PDT 24
Finished May 16 02:31:44 PM PDT 24
Peak memory 200616 kb
Host smart-27c9df32-c591-459e-89c5-90d98bafbd58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156981412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.156981412
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.2784417721
Short name T420
Test name
Test status
Simulation time 1650118537 ps
CPU time 5.89 seconds
Started May 16 02:31:07 PM PDT 24
Finished May 16 02:31:15 PM PDT 24
Peak memory 200628 kb
Host smart-ed642bda-5e24-48fd-a288-1723d1bd058b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784417721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.2784417721
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.2265175724
Short name T19
Test name
Test status
Simulation time 8043443432 ps
CPU time 938.54 seconds
Started May 16 02:31:07 PM PDT 24
Finished May 16 02:46:48 PM PDT 24
Peak memory 732352 kb
Host smart-1e672a23-9b55-4b87-81a3-5a13369d726f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265175724 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.2265175724
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_test_hmac_vectors.523827950
Short name T469
Test name
Test status
Simulation time 44516633 ps
CPU time 1.07 seconds
Started May 16 02:31:07 PM PDT 24
Finished May 16 02:31:10 PM PDT 24
Peak memory 200092 kb
Host smart-d8c7c3a8-651c-4cba-a772-44a28b069daf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523827950 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 47.hmac_test_hmac_vectors.523827950
Directory /workspace/47.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha_vectors.2058457098
Short name T182
Test name
Test status
Simulation time 127809249621 ps
CPU time 477.53 seconds
Started May 16 02:31:07 PM PDT 24
Finished May 16 02:39:06 PM PDT 24
Peak memory 200648 kb
Host smart-cfa2f310-bafc-4d35-ac07-bd2fd4fa1c61
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058457098 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_sha_vectors.2058457098
Directory /workspace/47.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/48.hmac_alert_test.1381237830
Short name T201
Test name
Test status
Simulation time 15348431 ps
CPU time 0.61 seconds
Started May 16 02:31:20 PM PDT 24
Finished May 16 02:31:24 PM PDT 24
Peak memory 197080 kb
Host smart-5c190d26-8c3a-4ecb-9612-1c1167a6bd07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381237830 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.1381237830
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.2385326596
Short name T312
Test name
Test status
Simulation time 98862945 ps
CPU time 6.73 seconds
Started May 16 02:31:07 PM PDT 24
Finished May 16 02:31:16 PM PDT 24
Peak memory 216840 kb
Host smart-c234bb1c-1b62-4c51-b1a3-4a9ba855f5fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2385326596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.2385326596
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.1940845214
Short name T87
Test name
Test status
Simulation time 530858804 ps
CPU time 5.08 seconds
Started May 16 02:31:09 PM PDT 24
Finished May 16 02:31:16 PM PDT 24
Peak memory 200616 kb
Host smart-f646855c-b827-4362-9860-19caa3d673de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940845214 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.1940845214
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.3811750964
Short name T76
Test name
Test status
Simulation time 971959681 ps
CPU time 193.41 seconds
Started May 16 02:31:08 PM PDT 24
Finished May 16 02:34:24 PM PDT 24
Peak memory 442284 kb
Host smart-72e7692f-c28d-49c9-b8c3-38b280c69b44
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3811750964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.3811750964
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_long_msg.572777777
Short name T108
Test name
Test status
Simulation time 1711645111 ps
CPU time 100.39 seconds
Started May 16 02:31:09 PM PDT 24
Finished May 16 02:32:51 PM PDT 24
Peak memory 200640 kb
Host smart-d4df0721-4c12-449e-a4bf-3bd3784918bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572777777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.572777777
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.1675499473
Short name T170
Test name
Test status
Simulation time 2322524898 ps
CPU time 6.1 seconds
Started May 16 02:31:09 PM PDT 24
Finished May 16 02:31:17 PM PDT 24
Peak memory 200716 kb
Host smart-bdb483f1-986b-4bc2-ad3b-1b6474fc9eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675499473 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.1675499473
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_test_hmac_vectors.2549670786
Short name T460
Test name
Test status
Simulation time 371558069 ps
CPU time 0.98 seconds
Started May 16 02:31:19 PM PDT 24
Finished May 16 02:31:22 PM PDT 24
Peak memory 199560 kb
Host smart-4453acfb-bcce-4d88-b6da-63dddd46994e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549670786 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.hmac_test_hmac_vectors.2549670786
Directory /workspace/48.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha_vectors.1591510525
Short name T217
Test name
Test status
Simulation time 8074831504 ps
CPU time 467.38 seconds
Started May 16 02:31:17 PM PDT 24
Finished May 16 02:39:07 PM PDT 24
Peak memory 200700 kb
Host smart-ab3fb6cf-9585-4bb2-880f-b57f3291117b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591510525 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_sha_vectors.1591510525
Directory /workspace/48.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/49.hmac_alert_test.3690288136
Short name T251
Test name
Test status
Simulation time 19094242 ps
CPU time 0.6 seconds
Started May 16 02:31:19 PM PDT 24
Finished May 16 02:31:21 PM PDT 24
Peak memory 195292 kb
Host smart-d45840a3-aa74-479e-bd22-6cd5e0a7351f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690288136 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.3690288136
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.1763649204
Short name T355
Test name
Test status
Simulation time 2363956730 ps
CPU time 43.49 seconds
Started May 16 02:31:20 PM PDT 24
Finished May 16 02:32:07 PM PDT 24
Peak memory 216836 kb
Host smart-ce4ca616-c2e1-4f8b-b20a-f0eda0099d44
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1763649204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.1763649204
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.2119900049
Short name T91
Test name
Test status
Simulation time 4619909138 ps
CPU time 62.99 seconds
Started May 16 02:31:18 PM PDT 24
Finished May 16 02:32:23 PM PDT 24
Peak memory 200824 kb
Host smart-ff4a538e-df58-41ef-823e-dfb9a64fdd85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119900049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.2119900049
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.2385922884
Short name T472
Test name
Test status
Simulation time 12246430336 ps
CPU time 567.68 seconds
Started May 16 02:31:19 PM PDT 24
Finished May 16 02:40:49 PM PDT 24
Peak memory 732464 kb
Host smart-e42c5a18-954d-4c33-a855-5b67829693d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2385922884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.2385922884
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_long_msg.2077192335
Short name T212
Test name
Test status
Simulation time 9516922903 ps
CPU time 18.97 seconds
Started May 16 02:31:21 PM PDT 24
Finished May 16 02:31:44 PM PDT 24
Peak memory 200716 kb
Host smart-491f543a-31b0-4320-86d3-84ef6a8d528b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077192335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.2077192335
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.3332570761
Short name T346
Test name
Test status
Simulation time 880364651 ps
CPU time 5.41 seconds
Started May 16 02:31:40 PM PDT 24
Finished May 16 02:31:46 PM PDT 24
Peak memory 200688 kb
Host smart-35369f00-084e-4e97-91eb-05f1632a5911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332570761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.3332570761
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_test_hmac_vectors.1364159290
Short name T79
Test name
Test status
Simulation time 27575625 ps
CPU time 1.06 seconds
Started May 16 02:31:20 PM PDT 24
Finished May 16 02:31:24 PM PDT 24
Peak memory 200212 kb
Host smart-7c3f7062-8ce2-4b76-977b-9f8b869923c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364159290 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.hmac_test_hmac_vectors.1364159290
Directory /workspace/49.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha_vectors.1689546253
Short name T374
Test name
Test status
Simulation time 9190594078 ps
CPU time 521.7 seconds
Started May 16 02:31:20 PM PDT 24
Finished May 16 02:40:04 PM PDT 24
Peak memory 200708 kb
Host smart-d0849ded-dbc3-4875-bc62-2026ea3402bc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689546253 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_sha_vectors.1689546253
Directory /workspace/49.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/5.hmac_alert_test.3076950671
Short name T244
Test name
Test status
Simulation time 12863439 ps
CPU time 0.61 seconds
Started May 16 02:28:52 PM PDT 24
Finished May 16 02:28:55 PM PDT 24
Peak memory 196364 kb
Host smart-df74d116-2ee4-46c6-a421-c4aec93a3af3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076950671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.3076950671
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.905109878
Short name T348
Test name
Test status
Simulation time 2146881565 ps
CPU time 26.32 seconds
Started May 16 02:28:43 PM PDT 24
Finished May 16 02:29:12 PM PDT 24
Peak memory 222148 kb
Host smart-a320a540-51f6-424b-8763-4028eeca9ee3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=905109878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.905109878
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.1035394396
Short name T431
Test name
Test status
Simulation time 1298332909 ps
CPU time 55.35 seconds
Started May 16 02:28:44 PM PDT 24
Finished May 16 02:29:41 PM PDT 24
Peak memory 200692 kb
Host smart-8d9db17f-6f27-4566-aa45-692d623b6ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035394396 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.1035394396
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.1524744276
Short name T185
Test name
Test status
Simulation time 2646717742 ps
CPU time 721.78 seconds
Started May 16 02:28:49 PM PDT 24
Finished May 16 02:40:53 PM PDT 24
Peak memory 717024 kb
Host smart-d36e717e-f68b-4f13-a8c3-ad7cb6610f10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1524744276 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.1524744276
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_long_msg.4251359363
Short name T151
Test name
Test status
Simulation time 851087721 ps
CPU time 25.52 seconds
Started May 16 02:28:43 PM PDT 24
Finished May 16 02:29:11 PM PDT 24
Peak memory 200548 kb
Host smart-c693f641-9321-4566-b986-d4355d8281b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251359363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.4251359363
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.2937079676
Short name T224
Test name
Test status
Simulation time 1762000357 ps
CPU time 6.14 seconds
Started May 16 02:28:51 PM PDT 24
Finished May 16 02:29:00 PM PDT 24
Peak memory 200588 kb
Host smart-b19d4c39-f2df-4520-866f-091beef59c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937079676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.2937079676
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_test_hmac_vectors.4079189554
Short name T309
Test name
Test status
Simulation time 40141033 ps
CPU time 1.21 seconds
Started May 16 02:28:49 PM PDT 24
Finished May 16 02:28:53 PM PDT 24
Peak memory 200316 kb
Host smart-fbfc1936-7291-4128-8f92-d2687d630f58
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079189554 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.hmac_test_hmac_vectors.4079189554
Directory /workspace/5.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha_vectors.374647000
Short name T181
Test name
Test status
Simulation time 35975021276 ps
CPU time 482.98 seconds
Started May 16 02:28:49 PM PDT 24
Finished May 16 02:36:54 PM PDT 24
Peak memory 200636 kb
Host smart-3bd767ee-6009-4e3b-b53f-67619f391d75
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374647000 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_sha_vectors.374647000
Directory /workspace/5.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/6.hmac_alert_test.3218433068
Short name T452
Test name
Test status
Simulation time 34678368 ps
CPU time 0.61 seconds
Started May 16 02:28:51 PM PDT 24
Finished May 16 02:28:54 PM PDT 24
Peak memory 196344 kb
Host smart-d0679aac-887f-4114-b14d-89768385c6bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218433068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.3218433068
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.3801962128
Short name T283
Test name
Test status
Simulation time 9028378531 ps
CPU time 54.87 seconds
Started May 16 02:28:47 PM PDT 24
Finished May 16 02:29:45 PM PDT 24
Peak memory 233600 kb
Host smart-639c979c-38ed-4352-bb85-6a60329e042b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3801962128 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.3801962128
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.3274866313
Short name T33
Test name
Test status
Simulation time 1771920525 ps
CPU time 25.48 seconds
Started May 16 02:28:52 PM PDT 24
Finished May 16 02:29:20 PM PDT 24
Peak memory 200492 kb
Host smart-14e9dbc7-a4db-492a-acce-b707ffad8b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274866313 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.3274866313
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.3233198094
Short name T229
Test name
Test status
Simulation time 11596559488 ps
CPU time 908.72 seconds
Started May 16 02:28:50 PM PDT 24
Finished May 16 02:44:01 PM PDT 24
Peak memory 736004 kb
Host smart-eb092026-0b52-4c49-830f-9f761107a12e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3233198094 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.3233198094
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.1593482169
Short name T20
Test name
Test status
Simulation time 1778226855 ps
CPU time 99.5 seconds
Started May 16 02:28:49 PM PDT 24
Finished May 16 02:30:32 PM PDT 24
Peak memory 200676 kb
Host smart-b02c182c-da13-4d08-ab84-d896d603e3a4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593482169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.1593482169
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.803576138
Short name T218
Test name
Test status
Simulation time 14776226299 ps
CPU time 46.24 seconds
Started May 16 02:28:51 PM PDT 24
Finished May 16 02:29:40 PM PDT 24
Peak memory 200612 kb
Host smart-222d22c0-c98a-462a-9bde-8dccd1c5018e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803576138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.803576138
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.1058550467
Short name T463
Test name
Test status
Simulation time 124738911 ps
CPU time 4.67 seconds
Started May 16 02:28:43 PM PDT 24
Finished May 16 02:28:50 PM PDT 24
Peak memory 200592 kb
Host smart-df8cd99e-bb5a-4bef-8454-a77f483b5a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058550467 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.1058550467
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_test_hmac_vectors.2233663957
Short name T354
Test name
Test status
Simulation time 161700610 ps
CPU time 1.18 seconds
Started May 16 02:28:44 PM PDT 24
Finished May 16 02:28:48 PM PDT 24
Peak memory 200280 kb
Host smart-2abb91f6-2715-4291-89b3-417e110bfdc3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233663957 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.hmac_test_hmac_vectors.2233663957
Directory /workspace/6.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha_vectors.2652417674
Short name T356
Test name
Test status
Simulation time 177244123408 ps
CPU time 524.46 seconds
Started May 16 02:28:51 PM PDT 24
Finished May 16 02:37:38 PM PDT 24
Peak memory 200556 kb
Host smart-1d99c751-6065-4f2c-98ce-401e9be08287
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652417674 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_sha_vectors.2652417674
Directory /workspace/6.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/7.hmac_alert_test.551047676
Short name T476
Test name
Test status
Simulation time 36919478 ps
CPU time 0.56 seconds
Started May 16 02:29:00 PM PDT 24
Finished May 16 02:29:07 PM PDT 24
Peak memory 195344 kb
Host smart-8e1e18d7-0038-4b3e-812a-30cde4be5495
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551047676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.551047676
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.3385124727
Short name T264
Test name
Test status
Simulation time 641716443 ps
CPU time 9.29 seconds
Started May 16 02:28:52 PM PDT 24
Finished May 16 02:29:04 PM PDT 24
Peak memory 208736 kb
Host smart-2fac65cb-5d2e-4cf9-9c5e-4179a999b0ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3385124727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.3385124727
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.684328695
Short name T172
Test name
Test status
Simulation time 88764332 ps
CPU time 2.36 seconds
Started May 16 02:28:49 PM PDT 24
Finished May 16 02:28:54 PM PDT 24
Peak memory 200584 kb
Host smart-75fab42b-b6e0-491c-964a-273ab226cc55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684328695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.684328695
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.503338692
Short name T184
Test name
Test status
Simulation time 964203252 ps
CPU time 312.35 seconds
Started May 16 02:28:51 PM PDT 24
Finished May 16 02:34:06 PM PDT 24
Peak memory 653532 kb
Host smart-59071274-49c0-4b47-907e-5031550b7c5f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=503338692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.503338692
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_long_msg.1014129808
Short name T209
Test name
Test status
Simulation time 4088619704 ps
CPU time 70.31 seconds
Started May 16 02:28:42 PM PDT 24
Finished May 16 02:29:53 PM PDT 24
Peak memory 200768 kb
Host smart-20b1fbc0-19a0-47e0-9b08-792a944b8799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014129808 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.1014129808
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.3747893636
Short name T152
Test name
Test status
Simulation time 991688251 ps
CPU time 5.8 seconds
Started May 16 02:28:43 PM PDT 24
Finished May 16 02:28:51 PM PDT 24
Peak memory 200592 kb
Host smart-0ff89cae-ed8c-4e68-ba91-b41a54294aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747893636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.3747893636
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.2575981913
Short name T125
Test name
Test status
Simulation time 9601204270 ps
CPU time 116.87 seconds
Started May 16 02:28:57 PM PDT 24
Finished May 16 02:31:00 PM PDT 24
Peak memory 200720 kb
Host smart-7eb3716e-65f4-4e79-888d-f31f5e0ecff7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575981913 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.2575981913
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_test_hmac_vectors.1027923716
Short name T205
Test name
Test status
Simulation time 134836017 ps
CPU time 1.02 seconds
Started May 16 02:28:49 PM PDT 24
Finished May 16 02:28:53 PM PDT 24
Peak memory 199236 kb
Host smart-94a5c872-5d75-4b5a-b549-36c0ca273a9d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027923716 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.hmac_test_hmac_vectors.1027923716
Directory /workspace/7.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha_vectors.2508164824
Short name T9
Test name
Test status
Simulation time 65547476901 ps
CPU time 572.04 seconds
Started May 16 02:28:52 PM PDT 24
Finished May 16 02:38:26 PM PDT 24
Peak memory 200676 kb
Host smart-240d703d-c3e1-4b25-8bac-6fa6a68acc08
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508164824 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_sha_vectors.2508164824
Directory /workspace/7.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/8.hmac_alert_test.2621280600
Short name T203
Test name
Test status
Simulation time 23363409 ps
CPU time 0.57 seconds
Started May 16 02:28:55 PM PDT 24
Finished May 16 02:28:59 PM PDT 24
Peak memory 195368 kb
Host smart-02aed2f0-6ccc-4b8f-b72d-db408b1ce886
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621280600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.2621280600
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.4105983325
Short name T270
Test name
Test status
Simulation time 87638693 ps
CPU time 4.61 seconds
Started May 16 02:28:56 PM PDT 24
Finished May 16 02:29:06 PM PDT 24
Peak memory 200584 kb
Host smart-41d545b1-a0b8-462c-8168-5daab8c98dab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4105983325 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.4105983325
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.2472618068
Short name T470
Test name
Test status
Simulation time 5615183937 ps
CPU time 28.76 seconds
Started May 16 02:28:59 PM PDT 24
Finished May 16 02:29:34 PM PDT 24
Peak memory 200692 kb
Host smart-bfecd452-76b0-4221-8882-be3fd1742553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472618068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.2472618068
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.3247823343
Short name T260
Test name
Test status
Simulation time 11621557962 ps
CPU time 1036.82 seconds
Started May 16 02:28:54 PM PDT 24
Finished May 16 02:46:13 PM PDT 24
Peak memory 761572 kb
Host smart-b499f75e-a622-4cea-8fac-67d1e1172eae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3247823343 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.3247823343
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_long_msg.536252517
Short name T269
Test name
Test status
Simulation time 3885811153 ps
CPU time 116.74 seconds
Started May 16 02:28:55 PM PDT 24
Finished May 16 02:30:55 PM PDT 24
Peak memory 200788 kb
Host smart-facfb24b-9562-4447-a2c6-3e6a4ecb061d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536252517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.536252517
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.1466685172
Short name T425
Test name
Test status
Simulation time 171753130 ps
CPU time 1.04 seconds
Started May 16 02:28:55 PM PDT 24
Finished May 16 02:29:00 PM PDT 24
Peak memory 199664 kb
Host smart-c95a34a2-7006-4bfe-9866-7fdfb5b51f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466685172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.1466685172
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_test_hmac_vectors.840152421
Short name T242
Test name
Test status
Simulation time 37482314 ps
CPU time 1.02 seconds
Started May 16 02:28:58 PM PDT 24
Finished May 16 02:29:04 PM PDT 24
Peak memory 198952 kb
Host smart-4a07fd3f-c7e9-494a-b8bd-73643bde6ba2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840152421 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 8.hmac_test_hmac_vectors.840152421
Directory /workspace/8.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha_vectors.2221558065
Short name T376
Test name
Test status
Simulation time 535542312484 ps
CPU time 593.53 seconds
Started May 16 02:28:57 PM PDT 24
Finished May 16 02:38:55 PM PDT 24
Peak memory 200628 kb
Host smart-a9d933af-d335-44bb-8ea7-01a831dab507
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221558065 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_sha_vectors.2221558065
Directory /workspace/8.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.2268524661
Short name T390
Test name
Test status
Simulation time 47881458 ps
CPU time 2.96 seconds
Started May 16 02:28:56 PM PDT 24
Finished May 16 02:29:04 PM PDT 24
Peak memory 200384 kb
Host smart-27a174ef-1763-4531-90b0-5ac9d31aaec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268524661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.2268524661
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.763835632
Short name T315
Test name
Test status
Simulation time 23838472 ps
CPU time 0.6 seconds
Started May 16 02:28:59 PM PDT 24
Finished May 16 02:29:06 PM PDT 24
Peak memory 197104 kb
Host smart-4b72bd72-f191-42c9-bdfd-4ca4e182361d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763835632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.763835632
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.1505228602
Short name T44
Test name
Test status
Simulation time 235322266 ps
CPU time 19.84 seconds
Started May 16 02:28:53 PM PDT 24
Finished May 16 02:29:15 PM PDT 24
Peak memory 233376 kb
Host smart-4a59d8a9-f867-4951-b55a-8d5c5dd01029
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1505228602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.1505228602
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.1073754730
Short name T401
Test name
Test status
Simulation time 7487750625 ps
CPU time 52.36 seconds
Started May 16 02:28:53 PM PDT 24
Finished May 16 02:29:48 PM PDT 24
Peak memory 200696 kb
Host smart-6d6b62ea-c59a-44ca-8b56-f8d49049b87a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073754730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.1073754730
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.1436184566
Short name T177
Test name
Test status
Simulation time 12549150601 ps
CPU time 813.63 seconds
Started May 16 02:28:59 PM PDT 24
Finished May 16 02:42:39 PM PDT 24
Peak memory 621120 kb
Host smart-9b6d7711-e9f8-4044-8746-fdaf2d1b4e17
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1436184566 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.1436184566
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_long_msg.2375638708
Short name T145
Test name
Test status
Simulation time 2542031212 ps
CPU time 78.15 seconds
Started May 16 02:28:58 PM PDT 24
Finished May 16 02:30:22 PM PDT 24
Peak memory 200784 kb
Host smart-27cb1fc4-cbb2-4a2a-b245-a02b8e809170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375638708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.2375638708
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.3749533711
Short name T330
Test name
Test status
Simulation time 217022020 ps
CPU time 6.47 seconds
Started May 16 02:28:54 PM PDT 24
Finished May 16 02:29:03 PM PDT 24
Peak memory 200516 kb
Host smart-2e39e678-5fa2-4fea-8045-b6e645d9d4e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749533711 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.3749533711
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_test_hmac_vectors.390561975
Short name T347
Test name
Test status
Simulation time 70591041 ps
CPU time 1.29 seconds
Started May 16 02:28:56 PM PDT 24
Finished May 16 02:29:01 PM PDT 24
Peak memory 200488 kb
Host smart-7a9d2b62-0874-4c72-9f8d-1cbcfd5c0ef0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390561975 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 9.hmac_test_hmac_vectors.390561975
Directory /workspace/9.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha_vectors.246765071
Short name T173
Test name
Test status
Simulation time 36278484266 ps
CPU time 521.28 seconds
Started May 16 02:28:59 PM PDT 24
Finished May 16 02:37:46 PM PDT 24
Peak memory 200656 kb
Host smart-b02478af-6602-49da-961b-7df61ec7b090
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246765071 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_sha_vectors.246765071
Directory /workspace/9.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/99.hmac_stress_all_with_rand_reset.291180383
Short name T12
Test name
Test status
Simulation time 61524015284 ps
CPU time 381.28 seconds
Started May 16 02:31:48 PM PDT 24
Finished May 16 02:38:11 PM PDT 24
Peak memory 226804 kb
Host smart-dd4cafe4-d038-4ac5-8b45-eca4335f5d5c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=291180383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.hmac_stress_all_with_rand_reset.291180383
Directory /workspace/99.hmac_stress_all_with_rand_reset/latest
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