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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.62 95.37 97.22 100.00 94.12 98.25 98.52 99.85


Total test records in report: 655
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html
T532 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.3202147040 Oct 15 12:21:03 AM UTC 24 Oct 15 12:21:08 AM UTC 24 52912765 ps
T533 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_hw_reset.1848878076 Oct 15 12:21:08 AM UTC 24 Oct 15 12:21:10 AM UTC 24 28041559 ps
T104 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_rw.3113950113 Oct 15 12:21:08 AM UTC 24 Oct 15 12:21:10 AM UTC 24 36940707 ps
T118 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_same_csr_outstanding.1463820083 Oct 15 12:21:09 AM UTC 24 Oct 15 12:21:13 AM UTC 24 515032464 ps
T534 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2765427301 Oct 15 12:21:10 AM UTC 24 Oct 15 12:21:14 AM UTC 24 318786538 ps
T535 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_tl_errors.3328630614 Oct 15 12:21:11 AM UTC 24 Oct 15 12:21:16 AM UTC 24 215486597 ps
T536 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_intr_test.47690164 Oct 15 12:21:15 AM UTC 24 Oct 15 12:21:17 AM UTC 24 26951477 ps
T105 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_aliasing.1148413722 Oct 15 12:21:09 AM UTC 24 Oct 15 12:21:18 AM UTC 24 401243994 ps
T106 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_hw_reset.2869353921 Oct 15 12:21:17 AM UTC 24 Oct 15 12:21:19 AM UTC 24 49484183 ps
T107 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_bit_bash.2697472599 Oct 15 12:20:59 AM UTC 24 Oct 15 12:21:21 AM UTC 24 1281694050 ps
T108 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_rw.2425851242 Oct 15 12:21:19 AM UTC 24 Oct 15 12:21:21 AM UTC 24 39883899 ps
T63 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_tl_intg_err.4279505802 Oct 15 12:21:14 AM UTC 24 Oct 15 12:21:22 AM UTC 24 4857783452 ps
T112 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_bit_bash.2199785320 Oct 15 12:21:09 AM UTC 24 Oct 15 12:21:24 AM UTC 24 713299506 ps
T119 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_same_csr_outstanding.3467271939 Oct 15 12:21:22 AM UTC 24 Oct 15 12:21:26 AM UTC 24 425516097 ps
T537 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.3330309180 Oct 15 12:21:22 AM UTC 24 Oct 15 12:21:27 AM UTC 24 109652145 ps
T538 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_tl_errors.950634174 Oct 15 12:21:23 AM UTC 24 Oct 15 12:21:27 AM UTC 24 180509564 ps
T539 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_intr_test.4153852388 Oct 15 12:21:27 AM UTC 24 Oct 15 12:21:29 AM UTC 24 40560068 ps
T134 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_tl_intg_err.569859325 Oct 15 12:21:24 AM UTC 24 Oct 15 12:21:29 AM UTC 24 213658734 ps
T109 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_hw_reset.475696845 Oct 15 12:21:27 AM UTC 24 Oct 15 12:21:30 AM UTC 24 33813534 ps
T120 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_rw.3475057837 Oct 15 12:21:28 AM UTC 24 Oct 15 12:21:30 AM UTC 24 13217905 ps
T110 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_aliasing.3682581217 Oct 15 12:21:21 AM UTC 24 Oct 15 12:21:33 AM UTC 24 1918079431 ps
T121 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_same_csr_outstanding.634591599 Oct 15 12:21:30 AM UTC 24 Oct 15 12:21:34 AM UTC 24 35609221 ps
T540 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.1612734237 Oct 15 12:21:32 AM UTC 24 Oct 15 12:21:35 AM UTC 24 117291717 ps
T541 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_bit_bash.3572789041 Oct 15 12:21:19 AM UTC 24 Oct 15 12:21:36 AM UTC 24 721294471 ps
T542 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_intr_test.457136948 Oct 15 12:21:36 AM UTC 24 Oct 15 12:21:38 AM UTC 24 17166030 ps
T543 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_hw_reset.2444945925 Oct 15 12:21:37 AM UTC 24 Oct 15 12:21:39 AM UTC 24 78852147 ps
T544 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_tl_errors.1759421731 Oct 15 12:21:34 AM UTC 24 Oct 15 12:21:39 AM UTC 24 127593422 ps
T135 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_tl_intg_err.119240304 Oct 15 12:21:35 AM UTC 24 Oct 15 12:21:42 AM UTC 24 135319412 ps
T111 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_rw.2305373206 Oct 15 12:21:39 AM UTC 24 Oct 15 12:21:42 AM UTC 24 542958453 ps
T113 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_aliasing.148576361 Oct 15 12:21:30 AM UTC 24 Oct 15 12:21:43 AM UTC 24 580610266 ps
T122 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_same_csr_outstanding.1784289350 Oct 15 12:21:42 AM UTC 24 Oct 15 12:21:45 AM UTC 24 85030974 ps
T545 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_bit_bash.3285731549 Oct 15 12:21:30 AM UTC 24 Oct 15 12:21:48 AM UTC 24 2533942278 ps
T546 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_tl_errors.3377869214 Oct 15 12:21:44 AM UTC 24 Oct 15 12:21:49 AM UTC 24 43230917 ps
T142 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_tl_intg_err.994910757 Oct 15 12:21:45 AM UTC 24 Oct 15 12:21:49 AM UTC 24 163008898 ps
T547 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_intr_test.639875440 Oct 15 12:21:47 AM UTC 24 Oct 15 12:21:49 AM UTC 24 44012767 ps
T548 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_csr_rw.1573700982 Oct 15 12:21:47 AM UTC 24 Oct 15 12:21:49 AM UTC 24 18039370 ps
T114 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_aliasing.1623507514 Oct 15 12:21:40 AM UTC 24 Oct 15 12:21:51 AM UTC 24 736645556 ps
T549 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_tl_errors.1639737105 Oct 15 12:22:07 AM UTC 24 Oct 15 12:22:11 AM UTC 24 106824831 ps
T550 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.3176071310 Oct 15 12:21:49 AM UTC 24 Oct 15 12:21:52 AM UTC 24 171876821 ps
T551 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_same_csr_outstanding.2080549644 Oct 15 12:21:49 AM UTC 24 Oct 15 12:21:52 AM UTC 24 113123438 ps
T552 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_intr_test.2990151663 Oct 15 12:21:50 AM UTC 24 Oct 15 12:21:52 AM UTC 24 15175258 ps
T115 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_bit_bash.566684938 Oct 15 12:21:40 AM UTC 24 Oct 15 12:21:53 AM UTC 24 2945783473 ps
T553 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_csr_rw.2785961402 Oct 15 12:21:51 AM UTC 24 Oct 15 12:21:54 AM UTC 24 27836238 ps
T554 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_tl_errors.2043974711 Oct 15 12:21:49 AM UTC 24 Oct 15 12:21:54 AM UTC 24 191998124 ps
T139 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_tl_intg_err.1552828706 Oct 15 12:21:49 AM UTC 24 Oct 15 12:21:55 AM UTC 24 358010282 ps
T555 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_same_csr_outstanding.1932695527 Oct 15 12:21:53 AM UTC 24 Oct 15 12:21:56 AM UTC 24 106067468 ps
T556 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_intr_test.901505552 Oct 15 12:21:57 AM UTC 24 Oct 15 12:22:00 AM UTC 24 52888787 ps
T557 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_tl_errors.183400388 Oct 15 12:21:54 AM UTC 24 Oct 15 12:22:00 AM UTC 24 122430383 ps
T116 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_csr_rw.2475267059 Oct 15 12:21:57 AM UTC 24 Oct 15 12:22:00 AM UTC 24 53554245 ps
T143 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_tl_intg_err.2589179364 Oct 15 12:21:54 AM UTC 24 Oct 15 12:22:00 AM UTC 24 478290460 ps
T558 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3081291077 Oct 15 12:21:58 AM UTC 24 Oct 15 12:22:01 AM UTC 24 323590011 ps
T559 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.3620586125 Oct 15 12:21:58 AM UTC 24 Oct 15 12:22:02 AM UTC 24 101286229 ps
T560 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_intr_test.2260826798 Oct 15 12:22:01 AM UTC 24 Oct 15 12:22:03 AM UTC 24 25376682 ps
T561 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_csr_rw.1393440867 Oct 15 12:22:01 AM UTC 24 Oct 15 12:22:03 AM UTC 24 75968073 ps
T562 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_tl_errors.839449543 Oct 15 12:21:58 AM UTC 24 Oct 15 12:22:04 AM UTC 24 61117343 ps
T563 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_same_csr_outstanding.3115893098 Oct 15 12:22:01 AM UTC 24 Oct 15 12:22:05 AM UTC 24 145231742 ps
T564 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_intr_test.752362513 Oct 15 12:22:04 AM UTC 24 Oct 15 12:22:06 AM UTC 24 22238805 ps
T565 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_tl_intg_err.3913834988 Oct 15 12:22:01 AM UTC 24 Oct 15 12:22:07 AM UTC 24 511713330 ps
T137 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_tl_intg_err.391550387 Oct 15 12:22:04 AM UTC 24 Oct 15 12:22:08 AM UTC 24 212600158 ps
T566 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_csr_rw.4224004897 Oct 15 12:22:05 AM UTC 24 Oct 15 12:22:08 AM UTC 24 60070287 ps
T567 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_same_csr_outstanding.1873306748 Oct 15 12:22:05 AM UTC 24 Oct 15 12:22:08 AM UTC 24 107018809 ps
T568 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_tl_errors.1972152467 Oct 15 12:22:03 AM UTC 24 Oct 15 12:22:09 AM UTC 24 352935188 ps
T569 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_intr_test.421676931 Oct 15 12:22:09 AM UTC 24 Oct 15 12:22:11 AM UTC 24 18553995 ps
T570 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_csr_rw.626064449 Oct 15 12:22:09 AM UTC 24 Oct 15 12:22:11 AM UTC 24 16624713 ps
T571 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_same_csr_outstanding.1583055670 Oct 15 12:22:10 AM UTC 24 Oct 15 12:22:12 AM UTC 24 23670685 ps
T138 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_tl_intg_err.2047687199 Oct 15 12:22:09 AM UTC 24 Oct 15 12:22:15 AM UTC 24 186514118 ps
T572 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_intr_test.2231404012 Oct 15 12:22:13 AM UTC 24 Oct 15 12:22:15 AM UTC 24 76349545 ps
T573 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_tl_intg_err.4190967112 Oct 15 12:22:12 AM UTC 24 Oct 15 12:22:15 AM UTC 24 47211463 ps
T574 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.3275578919 Oct 15 12:22:12 AM UTC 24 Oct 15 12:22:15 AM UTC 24 61352926 ps
T575 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_csr_rw.2916357296 Oct 15 12:22:15 AM UTC 24 Oct 15 12:22:17 AM UTC 24 43665216 ps
T576 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_same_csr_outstanding.174884286 Oct 15 12:22:16 AM UTC 24 Oct 15 12:22:19 AM UTC 24 164206974 ps
T577 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_tl_errors.1903920007 Oct 15 12:22:12 AM UTC 24 Oct 15 12:22:19 AM UTC 24 200599556 ps
T578 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_tl_errors.3739981204 Oct 15 12:22:16 AM UTC 24 Oct 15 12:22:20 AM UTC 24 96748086 ps
T579 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_intr_test.2020361072 Oct 15 12:22:21 AM UTC 24 Oct 15 12:22:23 AM UTC 24 49500773 ps
T580 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_csr_rw.3447014043 Oct 15 12:22:21 AM UTC 24 Oct 15 12:22:24 AM UTC 24 100198963 ps
T581 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.3594320676 Oct 15 12:22:21 AM UTC 24 Oct 15 12:22:25 AM UTC 24 122688965 ps
T582 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_intr_test.1036642894 Oct 15 12:22:27 AM UTC 24 Oct 15 12:22:29 AM UTC 24 48492215 ps
T583 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_same_csr_outstanding.3708611161 Oct 15 12:22:21 AM UTC 24 Oct 15 12:22:26 AM UTC 24 110590916 ps
T140 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_tl_intg_err.1503825003 Oct 15 12:22:21 AM UTC 24 Oct 15 12:22:26 AM UTC 24 249397714 ps
T584 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_csr_rw.2201865869 Oct 15 12:22:27 AM UTC 24 Oct 15 12:22:29 AM UTC 24 26179918 ps
T585 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_tl_errors.2831403054 Oct 15 12:22:25 AM UTC 24 Oct 15 12:22:30 AM UTC 24 226366978 ps
T586 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_tl_intg_err.859918097 Oct 15 12:22:25 AM UTC 24 Oct 15 12:22:30 AM UTC 24 2828059441 ps
T587 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_same_csr_outstanding.4012954904 Oct 15 12:22:27 AM UTC 24 Oct 15 12:22:31 AM UTC 24 172493976 ps
T588 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.447534114 Oct 15 12:22:30 AM UTC 24 Oct 15 12:22:33 AM UTC 24 514783102 ps
T589 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_intr_test.319134035 Oct 15 12:22:34 AM UTC 24 Oct 15 12:22:36 AM UTC 24 30473523 ps
T590 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_tl_errors.946714775 Oct 15 12:22:30 AM UTC 24 Oct 15 12:22:36 AM UTC 24 740541817 ps
T591 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_csr_rw.304188611 Oct 15 12:22:34 AM UTC 24 Oct 15 12:22:36 AM UTC 24 56788318 ps
T592 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_same_csr_outstanding.512889464 Oct 15 12:22:34 AM UTC 24 Oct 15 12:22:37 AM UTC 24 300825145 ps
T593 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.3221790478 Oct 15 12:22:34 AM UTC 24 Oct 15 12:22:37 AM UTC 24 67505502 ps
T594 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_intr_test.1985625063 Oct 15 12:22:38 AM UTC 24 Oct 15 12:22:39 AM UTC 24 15432221 ps
T595 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_csr_rw.224950672 Oct 15 12:22:38 AM UTC 24 Oct 15 12:22:40 AM UTC 24 77446448 ps
T141 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_tl_intg_err.3274219859 Oct 15 12:22:34 AM UTC 24 Oct 15 12:22:40 AM UTC 24 170945494 ps
T596 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.772858778 Oct 15 12:22:38 AM UTC 24 Oct 15 12:22:41 AM UTC 24 69990499 ps
T597 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_same_csr_outstanding.2604760483 Oct 15 12:22:38 AM UTC 24 Oct 15 12:22:41 AM UTC 24 109724494 ps
T598 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_intr_test.2171419406 Oct 15 12:22:41 AM UTC 24 Oct 15 12:22:43 AM UTC 24 118004897 ps
T599 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_tl_errors.3634913125 Oct 15 12:22:37 AM UTC 24 Oct 15 12:22:43 AM UTC 24 157832411 ps
T144 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_tl_intg_err.1986858160 Oct 15 12:22:37 AM UTC 24 Oct 15 12:22:43 AM UTC 24 2661002673 ps
T600 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_csr_rw.1141144176 Oct 15 12:22:42 AM UTC 24 Oct 15 12:22:44 AM UTC 24 51127442 ps
T601 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_same_csr_outstanding.4293574211 Oct 15 12:22:42 AM UTC 24 Oct 15 12:22:45 AM UTC 24 62067236 ps
T602 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_tl_errors.2466508227 Oct 15 12:22:41 AM UTC 24 Oct 15 12:22:45 AM UTC 24 434829702 ps
T603 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_intr_test.3886365987 Oct 15 12:22:44 AM UTC 24 Oct 15 12:22:46 AM UTC 24 77993343 ps
T145 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_tl_intg_err.3656809346 Oct 15 12:22:41 AM UTC 24 Oct 15 12:22:47 AM UTC 24 306750246 ps
T604 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.959966927 Oct 15 12:22:44 AM UTC 24 Oct 15 12:22:47 AM UTC 24 700712697 ps
T605 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_csr_rw.2198753951 Oct 15 12:22:45 AM UTC 24 Oct 15 12:22:47 AM UTC 24 17601973 ps
T606 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_tl_errors.4221695097 Oct 15 12:22:44 AM UTC 24 Oct 15 12:22:48 AM UTC 24 536855896 ps
T607 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_tl_intg_err.2160237682 Oct 15 12:22:44 AM UTC 24 Oct 15 12:22:49 AM UTC 24 179227518 ps
T608 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_same_csr_outstanding.1113871984 Oct 15 12:22:45 AM UTC 24 Oct 15 12:22:49 AM UTC 24 206823591 ps
T609 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_intr_test.3279694556 Oct 15 12:22:48 AM UTC 24 Oct 15 12:22:50 AM UTC 24 23943009 ps
T610 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.781038724 Oct 15 12:22:47 AM UTC 24 Oct 15 12:22:51 AM UTC 24 161214982 ps
T611 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_csr_rw.4140538143 Oct 15 12:22:49 AM UTC 24 Oct 15 12:22:51 AM UTC 24 32711898 ps
T612 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_tl_errors.4233132778 Oct 15 12:22:47 AM UTC 24 Oct 15 12:22:52 AM UTC 24 212220678 ps
T613 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_same_csr_outstanding.1840086029 Oct 15 12:22:49 AM UTC 24 Oct 15 12:22:52 AM UTC 24 532900667 ps
T614 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_intr_test.183461083 Oct 15 12:22:51 AM UTC 24 Oct 15 12:22:53 AM UTC 24 14797194 ps
T615 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.2629177268 Oct 15 12:22:50 AM UTC 24 Oct 15 12:22:54 AM UTC 24 253753162 ps
T616 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_tl_intg_err.788462503 Oct 15 12:22:50 AM UTC 24 Oct 15 12:22:54 AM UTC 24 170856236 ps
T136 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_tl_intg_err.3609138379 Oct 15 12:22:48 AM UTC 24 Oct 15 12:22:54 AM UTC 24 1101893592 ps
T617 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_csr_rw.1981301018 Oct 15 12:22:53 AM UTC 24 Oct 15 12:22:55 AM UTC 24 55869626 ps
T618 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_tl_errors.2681997816 Oct 15 12:22:50 AM UTC 24 Oct 15 12:22:55 AM UTC 24 64352442 ps
T619 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/20.hmac_intr_test.2793897512 Oct 15 12:22:54 AM UTC 24 Oct 15 12:22:56 AM UTC 24 46068644 ps
T620 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/21.hmac_intr_test.284707010 Oct 15 12:22:54 AM UTC 24 Oct 15 12:22:56 AM UTC 24 15390298 ps
T621 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_same_csr_outstanding.4214453669 Oct 15 12:22:53 AM UTC 24 Oct 15 12:22:56 AM UTC 24 240642977 ps
T622 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/22.hmac_intr_test.65153136 Oct 15 12:22:55 AM UTC 24 Oct 15 12:22:57 AM UTC 24 29795274 ps
T623 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/24.hmac_intr_test.4118826191 Oct 15 12:22:55 AM UTC 24 Oct 15 12:22:57 AM UTC 24 36991095 ps
T624 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/25.hmac_intr_test.941780266 Oct 15 12:22:55 AM UTC 24 Oct 15 12:22:57 AM UTC 24 82804849 ps
T625 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/23.hmac_intr_test.161149394 Oct 15 12:22:55 AM UTC 24 Oct 15 12:22:57 AM UTC 24 27784207 ps
T626 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/27.hmac_intr_test.3668125499 Oct 15 12:22:56 AM UTC 24 Oct 15 12:22:58 AM UTC 24 16151111 ps
T627 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/26.hmac_intr_test.246328872 Oct 15 12:22:56 AM UTC 24 Oct 15 12:22:58 AM UTC 24 35472593 ps
T628 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/28.hmac_intr_test.2214786404 Oct 15 12:22:56 AM UTC 24 Oct 15 12:22:58 AM UTC 24 64753813 ps
T629 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.1422828475 Oct 15 12:22:54 AM UTC 24 Oct 15 12:22:59 AM UTC 24 42322534 ps
T630 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/29.hmac_intr_test.3826339732 Oct 15 12:22:57 AM UTC 24 Oct 15 12:22:59 AM UTC 24 16115585 ps
T631 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/30.hmac_intr_test.2440708329 Oct 15 12:22:57 AM UTC 24 Oct 15 12:23:00 AM UTC 24 54170633 ps
T632 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/31.hmac_intr_test.3809894283 Oct 15 12:22:58 AM UTC 24 Oct 15 12:23:00 AM UTC 24 11396670 ps
T633 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/32.hmac_intr_test.1552309277 Oct 15 12:22:58 AM UTC 24 Oct 15 12:23:00 AM UTC 24 14847439 ps
T634 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/33.hmac_intr_test.2025759319 Oct 15 12:22:58 AM UTC 24 Oct 15 12:23:00 AM UTC 24 19625819 ps
T635 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/34.hmac_intr_test.134186125 Oct 15 12:22:59 AM UTC 24 Oct 15 12:23:00 AM UTC 24 12273121 ps
T636 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/35.hmac_intr_test.98844298 Oct 15 12:22:59 AM UTC 24 Oct 15 12:23:01 AM UTC 24 13098627 ps
T637 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/36.hmac_intr_test.3896627272 Oct 15 12:22:59 AM UTC 24 Oct 15 12:23:01 AM UTC 24 87558916 ps
T638 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/37.hmac_intr_test.4091867780 Oct 15 12:23:00 AM UTC 24 Oct 15 12:23:02 AM UTC 24 14246089 ps
T639 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/38.hmac_intr_test.1464471934 Oct 15 12:23:00 AM UTC 24 Oct 15 12:23:02 AM UTC 24 20861922 ps
T640 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/40.hmac_intr_test.3974417561 Oct 15 12:23:00 AM UTC 24 Oct 15 12:23:02 AM UTC 24 30707904 ps
T641 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/39.hmac_intr_test.1749549077 Oct 15 12:23:00 AM UTC 24 Oct 15 12:23:02 AM UTC 24 14279919 ps
T642 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/41.hmac_intr_test.3698062969 Oct 15 12:23:01 AM UTC 24 Oct 15 12:23:03 AM UTC 24 18600661 ps
T643 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/42.hmac_intr_test.1212408334 Oct 15 12:23:01 AM UTC 24 Oct 15 12:23:03 AM UTC 24 43755492 ps
T644 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/43.hmac_intr_test.1134538273 Oct 15 12:23:01 AM UTC 24 Oct 15 12:23:03 AM UTC 24 18775451 ps
T645 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/44.hmac_intr_test.4085682013 Oct 15 12:23:01 AM UTC 24 Oct 15 12:23:03 AM UTC 24 37535869 ps
T646 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/45.hmac_intr_test.242663172 Oct 15 12:23:01 AM UTC 24 Oct 15 12:23:03 AM UTC 24 15219155 ps
T647 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/47.hmac_intr_test.1365693762 Oct 15 12:23:03 AM UTC 24 Oct 15 12:23:04 AM UTC 24 43857926 ps
T648 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/46.hmac_intr_test.2594562650 Oct 15 12:23:03 AM UTC 24 Oct 15 12:23:04 AM UTC 24 16241600 ps
T649 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/49.hmac_intr_test.1630105345 Oct 15 12:23:03 AM UTC 24 Oct 15 12:23:04 AM UTC 24 47386885 ps
T650 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/48.hmac_intr_test.2792960289 Oct 15 12:23:03 AM UTC 24 Oct 15 12:23:05 AM UTC 24 13010622 ps
T651 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.2770043523 Oct 15 12:22:16 AM UTC 24 Oct 15 12:28:33 AM UTC 24 26769868727 ps
T652 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.2875040532 Oct 15 12:21:42 AM UTC 24 Oct 15 12:34:03 AM UTC 24 139788952718 ps
T653 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.3422126269 Oct 15 12:22:07 AM UTC 24 Oct 15 12:35:36 AM UTC 24 914071830974 ps
T654 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.2257470056 Oct 15 12:21:53 AM UTC 24 Oct 15 12:36:21 AM UTC 24 86179234867 ps
T655 /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.3566990619 Oct 15 12:22:02 AM UTC 24 Oct 15 12:38:45 AM UTC 24 64438954344 ps

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/0.hmac_smoke.510712581
Short name T4
Test name
Test status
Simulation time 839122581 ps
CPU time 13.04 seconds
Started Oct 14 11:52:54 PM UTC 24
Finished Oct 14 11:53:09 PM UTC 24
Peak memory 207852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=510712581 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.510712581
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/0.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/3.hmac_burst_wr.4226927982
Short name T18
Test name
Test status
Simulation time 10344443266 ps
CPU time 69.52 seconds
Started Oct 14 11:53:33 PM UTC 24
Finished Oct 14 11:54:44 PM UTC 24
Peak memory 218268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4226927982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.4226927982
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/3.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/3.hmac_stress_all_with_rand_reset.551562623
Short name T20
Test name
Test status
Simulation time 82926203167 ps
CPU time 145.36 seconds
Started Oct 14 11:53:45 PM UTC 24
Finished Oct 14 11:56:13 PM UTC 24
Peak memory 226360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55156262
3 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all_with_rand_reset.551562623
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/3.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/1.hmac_smoke.2567898349
Short name T3
Test name
Test status
Simulation time 1119931574 ps
CPU time 5.74 seconds
Started Oct 14 11:53:01 PM UTC 24
Finished Oct 14 11:53:08 PM UTC 24
Peak memory 209896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2567898349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.2567898349
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/1.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_tl_intg_err.119240304
Short name T135
Test name
Test status
Simulation time 135319412 ps
CPU time 5.29 seconds
Started Oct 15 12:21:35 AM UTC 24
Finished Oct 15 12:21:42 AM UTC 24
Peak memory 207636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119240304 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_14/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.119240304
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/4.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/2.hmac_error.3995687416
Short name T30
Test name
Test status
Simulation time 1599616452 ps
CPU time 44.81 seconds
Started Oct 14 11:53:17 PM UTC 24
Finished Oct 14 11:54:03 PM UTC 24
Peak memory 209768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3995687416 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.3995687416
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/2.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/1.hmac_sec_cm.1577693755
Short name T27
Test name
Test status
Simulation time 290630876 ps
CPU time 1.34 seconds
Started Oct 14 11:53:10 PM UTC 24
Finished Oct 14 11:53:13 PM UTC 24
Peak memory 238012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1577693755 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.1577693755
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/1.hmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/2.hmac_wipe_secret.2035038055
Short name T166
Test name
Test status
Simulation time 1830275656 ps
CPU time 104.38 seconds
Started Oct 14 11:53:18 PM UTC 24
Finished Oct 14 11:55:05 PM UTC 24
Peak memory 209704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2035038055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.2035038055
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/2.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/42.hmac_back_pressure.3805855194
Short name T33
Test name
Test status
Simulation time 2145683737 ps
CPU time 64.63 seconds
Started Oct 15 12:14:48 AM UTC 24
Finished Oct 15 12:15:54 AM UTC 24
Peak memory 209640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805855194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.3805855194
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/42.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_rw.3113950113
Short name T104
Test name
Test status
Simulation time 36940707 ps
CPU time 1.29 seconds
Started Oct 15 12:21:08 AM UTC 24
Finished Oct 15 12:21:10 AM UTC 24
Peak memory 206572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3113950113 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.3113950113
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/1.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/2.hmac_stress_all_with_rand_reset.1067549208
Short name T65
Test name
Test status
Simulation time 5062130944 ps
CPU time 381.79 seconds
Started Oct 14 11:53:29 PM UTC 24
Finished Oct 14 11:59:56 PM UTC 24
Peak memory 514868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10675492
08 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all_with_rand_reset.1067549208
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/2.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/8.hmac_back_pressure.582280372
Short name T154
Test name
Test status
Simulation time 5073437423 ps
CPU time 70.19 seconds
Started Oct 14 11:55:23 PM UTC 24
Finished Oct 14 11:56:36 PM UTC 24
Peak memory 209704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=582280372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.582280372
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/8.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/6.hmac_stress_all.3443312741
Short name T25
Test name
Test status
Simulation time 5165546773 ps
CPU time 299.15 seconds
Started Oct 14 11:55:01 PM UTC 24
Finished Oct 15 12:00:04 AM UTC 24
Peak memory 218536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3443312741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.3443312741
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/6.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/0.hmac_alert_test.2258965431
Short name T1
Test name
Test status
Simulation time 12086302 ps
CPU time 0.65 seconds
Started Oct 14 11:53:00 PM UTC 24
Finished Oct 14 11:53:02 PM UTC 24
Peak memory 207224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2258965431 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.2258965431
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/0.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_tl_intg_err.1503825003
Short name T140
Test name
Test status
Simulation time 249397714 ps
CPU time 3.62 seconds
Started Oct 15 12:22:21 AM UTC 24
Finished Oct 15 12:22:26 AM UTC 24
Peak memory 207708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1503825003 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.1503825003
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/12.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/10.hmac_burst_wr.2159464206
Short name T157
Test name
Test status
Simulation time 888416297 ps
CPU time 54.18 seconds
Started Oct 14 11:56:03 PM UTC 24
Finished Oct 14 11:56:59 PM UTC 24
Peak memory 209696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2159464206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.2159464206
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/10.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_tl_intg_err.2047687199
Short name T138
Test name
Test status
Simulation time 186514118 ps
CPU time 4.89 seconds
Started Oct 15 12:22:09 AM UTC 24
Finished Oct 15 12:22:15 AM UTC 24
Peak memory 207568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2047687199 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.2047687199
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/10.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/0.hmac_test_hmac256_vectors.2808698385
Short name T64
Test name
Test status
Simulation time 13134120917 ps
CPU time 40.64 seconds
Started Oct 14 11:52:58 PM UTC 24
Finished Oct 14 11:53:43 PM UTC 24
Peak memory 209760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2808698385 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac256_vectors.2808698385
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/0.hmac_test_hmac256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/0.hmac_test_sha256_vectors.526888838
Short name T272
Test name
Test status
Simulation time 107412154834 ps
CPU time 676.74 seconds
Started Oct 14 11:52:57 PM UTC 24
Finished Oct 15 12:04:26 AM UTC 24
Peak memory 213356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526888838 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha256_vectors.526888838
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/0.hmac_test_sha256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/22.hmac_stress_all.2064981109
Short name T164
Test name
Test status
Simulation time 17325255056 ps
CPU time 1418.66 seconds
Started Oct 15 12:02:27 AM UTC 24
Finished Oct 15 12:26:20 AM UTC 24
Peak memory 731636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2064981109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.2064981109
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/22.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_tl_intg_err.4039439527
Short name T61
Test name
Test status
Simulation time 155297039 ps
CPU time 3.47 seconds
Started Oct 15 12:20:56 AM UTC 24
Finished Oct 15 12:21:00 AM UTC 24
Peak memory 207616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039439527 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.4039439527
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/0.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_aliasing.2961097985
Short name T531
Test name
Test status
Simulation time 303397629 ps
CPU time 6.12 seconds
Started Oct 15 12:21:00 AM UTC 24
Finished Oct 15 12:21:07 AM UTC 24
Peak memory 207640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2961097985 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.2961097985
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/0.hmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_bit_bash.2697472599
Short name T107
Test name
Test status
Simulation time 1281694050 ps
CPU time 19.9 seconds
Started Oct 15 12:20:59 AM UTC 24
Finished Oct 15 12:21:21 AM UTC 24
Peak memory 207440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697472599 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.2697472599
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/0.hmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_hw_reset.3631768176
Short name T103
Test name
Test status
Simulation time 38487350 ps
CPU time 1.33 seconds
Started Oct 15 12:20:58 AM UTC 24
Finished Oct 15 12:21:01 AM UTC 24
Peak memory 206628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3631768176 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.3631768176
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/0.hmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.3202147040
Short name T532
Test name
Test status
Simulation time 52912765 ps
CPU time 4.55 seconds
Started Oct 15 12:21:03 AM UTC 24
Finished Oct 15 12:21:08 AM UTC 24
Peak memory 216048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3202147040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_r
eset.3202147040
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_rw.1196722430
Short name T102
Test name
Test status
Simulation time 76719609 ps
CPU time 1.22 seconds
Started Oct 15 12:20:58 AM UTC 24
Finished Oct 15 12:21:00 AM UTC 24
Peak memory 206572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1196722430 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.1196722430
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/0.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_intr_test.846704219
Short name T529
Test name
Test status
Simulation time 14653889 ps
CPU time 0.84 seconds
Started Oct 15 12:20:56 AM UTC 24
Finished Oct 15 12:20:58 AM UTC 24
Peak memory 204536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=846704219 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.846704219
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/0.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_same_csr_outstanding.1894205008
Short name T117
Test name
Test status
Simulation time 609155747 ps
CPU time 2.54 seconds
Started Oct 15 12:21:01 AM UTC 24
Finished Oct 15 12:21:04 AM UTC 24
Peak memory 207492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1894205008 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr_outstanding.1894205008
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/0.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_tl_errors.2506118296
Short name T67
Test name
Test status
Simulation time 60861583 ps
CPU time 5.11 seconds
Started Oct 15 12:20:52 AM UTC 24
Finished Oct 15 12:20:58 AM UTC 24
Peak memory 207492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2506118296 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.2506118296
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/0.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_aliasing.1148413722
Short name T105
Test name
Test status
Simulation time 401243994 ps
CPU time 7.52 seconds
Started Oct 15 12:21:09 AM UTC 24
Finished Oct 15 12:21:18 AM UTC 24
Peak memory 207432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1148413722 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.1148413722
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/1.hmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_bit_bash.2199785320
Short name T112
Test name
Test status
Simulation time 713299506 ps
CPU time 13.37 seconds
Started Oct 15 12:21:09 AM UTC 24
Finished Oct 15 12:21:24 AM UTC 24
Peak memory 207868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2199785320 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.2199785320
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/1.hmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_hw_reset.1848878076
Short name T533
Test name
Test status
Simulation time 28041559 ps
CPU time 0.95 seconds
Started Oct 15 12:21:08 AM UTC 24
Finished Oct 15 12:21:10 AM UTC 24
Peak memory 205776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1848878076 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.1848878076
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/1.hmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2765427301
Short name T534
Test name
Test status
Simulation time 318786538 ps
CPU time 3.17 seconds
Started Oct 15 12:21:10 AM UTC 24
Finished Oct 15 12:21:14 AM UTC 24
Peak memory 215720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2765427301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_r
eset.2765427301
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_intr_test.2688402324
Short name T530
Test name
Test status
Simulation time 17565899 ps
CPU time 0.85 seconds
Started Oct 15 12:21:05 AM UTC 24
Finished Oct 15 12:21:07 AM UTC 24
Peak memory 203092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2688402324 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.2688402324
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/1.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_same_csr_outstanding.1463820083
Short name T118
Test name
Test status
Simulation time 515032464 ps
CPU time 3.17 seconds
Started Oct 15 12:21:09 AM UTC 24
Finished Oct 15 12:21:13 AM UTC 24
Peak memory 207480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1463820083 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr_outstanding.1463820083
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/1.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_tl_errors.1831357564
Short name T68
Test name
Test status
Simulation time 536841331 ps
CPU time 4.26 seconds
Started Oct 15 12:21:03 AM UTC 24
Finished Oct 15 12:21:08 AM UTC 24
Peak memory 207500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1831357564 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.1831357564
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/1.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_tl_intg_err.1719870756
Short name T62
Test name
Test status
Simulation time 686375381 ps
CPU time 4.43 seconds
Started Oct 15 12:21:03 AM UTC 24
Finished Oct 15 12:21:08 AM UTC 24
Peak memory 207452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1719870756 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.1719870756
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/1.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.3275578919
Short name T574
Test name
Test status
Simulation time 61352926 ps
CPU time 2.53 seconds
Started Oct 15 12:22:12 AM UTC 24
Finished Oct 15 12:22:15 AM UTC 24
Peak memory 215544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3275578919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_
reset.3275578919
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_csr_rw.626064449
Short name T570
Test name
Test status
Simulation time 16624713 ps
CPU time 1.37 seconds
Started Oct 15 12:22:09 AM UTC 24
Finished Oct 15 12:22:11 AM UTC 24
Peak memory 206568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=626064449 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.626064449
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/10.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_intr_test.421676931
Short name T569
Test name
Test status
Simulation time 18553995 ps
CPU time 0.93 seconds
Started Oct 15 12:22:09 AM UTC 24
Finished Oct 15 12:22:11 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=421676931 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.421676931
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/10.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_same_csr_outstanding.1583055670
Short name T571
Test name
Test status
Simulation time 23670685 ps
CPU time 1.62 seconds
Started Oct 15 12:22:10 AM UTC 24
Finished Oct 15 12:22:12 AM UTC 24
Peak memory 206688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1583055670 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_csr_outstanding.1583055670
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/10.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_tl_errors.1639737105
Short name T549
Test name
Test status
Simulation time 106824831 ps
CPU time 3.01 seconds
Started Oct 15 12:22:07 AM UTC 24
Finished Oct 15 12:22:11 AM UTC 24
Peak memory 207496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639737105 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.1639737105
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/10.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.2770043523
Short name T651
Test name
Test status
Simulation time 26769868727 ps
CPU time 372.2 seconds
Started Oct 15 12:22:16 AM UTC 24
Finished Oct 15 12:28:33 AM UTC 24
Peak memory 215804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2770043523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_
reset.2770043523
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_csr_rw.2916357296
Short name T575
Test name
Test status
Simulation time 43665216 ps
CPU time 1.11 seconds
Started Oct 15 12:22:15 AM UTC 24
Finished Oct 15 12:22:17 AM UTC 24
Peak memory 206568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2916357296 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.2916357296
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/11.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_intr_test.2231404012
Short name T572
Test name
Test status
Simulation time 76349545 ps
CPU time 0.89 seconds
Started Oct 15 12:22:13 AM UTC 24
Finished Oct 15 12:22:15 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2231404012 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.2231404012
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/11.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_same_csr_outstanding.174884286
Short name T576
Test name
Test status
Simulation time 164206974 ps
CPU time 1.59 seconds
Started Oct 15 12:22:16 AM UTC 24
Finished Oct 15 12:22:19 AM UTC 24
Peak memory 206540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=174884286 -assert nopostproc +UVM
_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_csr_outstanding.174884286
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/11.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_tl_errors.1903920007
Short name T577
Test name
Test status
Simulation time 200599556 ps
CPU time 6.25 seconds
Started Oct 15 12:22:12 AM UTC 24
Finished Oct 15 12:22:19 AM UTC 24
Peak memory 207192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1903920007 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.1903920007
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/11.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_tl_intg_err.4190967112
Short name T573
Test name
Test status
Simulation time 47211463 ps
CPU time 2.25 seconds
Started Oct 15 12:22:12 AM UTC 24
Finished Oct 15 12:22:15 AM UTC 24
Peak memory 207440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4190967112 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.4190967112
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/11.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.3594320676
Short name T581
Test name
Test status
Simulation time 122688965 ps
CPU time 2.77 seconds
Started Oct 15 12:22:21 AM UTC 24
Finished Oct 15 12:22:25 AM UTC 24
Peak memory 207564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3594320676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_
reset.3594320676
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_csr_rw.3447014043
Short name T580
Test name
Test status
Simulation time 100198963 ps
CPU time 1.1 seconds
Started Oct 15 12:22:21 AM UTC 24
Finished Oct 15 12:22:24 AM UTC 24
Peak memory 206356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3447014043 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.3447014043
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/12.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_intr_test.2020361072
Short name T579
Test name
Test status
Simulation time 49500773 ps
CPU time 0.9 seconds
Started Oct 15 12:22:21 AM UTC 24
Finished Oct 15 12:22:23 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2020361072 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.2020361072
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/12.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_same_csr_outstanding.3708611161
Short name T583
Test name
Test status
Simulation time 110590916 ps
CPU time 3.4 seconds
Started Oct 15 12:22:21 AM UTC 24
Finished Oct 15 12:22:26 AM UTC 24
Peak memory 207704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3708611161 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_csr_outstanding.3708611161
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/12.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_tl_errors.3739981204
Short name T578
Test name
Test status
Simulation time 96748086 ps
CPU time 2.95 seconds
Started Oct 15 12:22:16 AM UTC 24
Finished Oct 15 12:22:20 AM UTC 24
Peak memory 207780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3739981204 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.3739981204
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/12.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.447534114
Short name T588
Test name
Test status
Simulation time 514783102 ps
CPU time 2.04 seconds
Started Oct 15 12:22:30 AM UTC 24
Finished Oct 15 12:22:33 AM UTC 24
Peak memory 207612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=447534114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_r
eset.447534114
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_csr_rw.2201865869
Short name T584
Test name
Test status
Simulation time 26179918 ps
CPU time 1.15 seconds
Started Oct 15 12:22:27 AM UTC 24
Finished Oct 15 12:22:29 AM UTC 24
Peak memory 206568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2201865869 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.2201865869
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/13.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_intr_test.1036642894
Short name T582
Test name
Test status
Simulation time 48492215 ps
CPU time 0.89 seconds
Started Oct 15 12:22:27 AM UTC 24
Finished Oct 15 12:22:29 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1036642894 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.1036642894
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/13.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_same_csr_outstanding.4012954904
Short name T587
Test name
Test status
Simulation time 172493976 ps
CPU time 3.04 seconds
Started Oct 15 12:22:27 AM UTC 24
Finished Oct 15 12:22:31 AM UTC 24
Peak memory 207568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4012954904 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_csr_outstanding.4012954904
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/13.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_tl_errors.2831403054
Short name T585
Test name
Test status
Simulation time 226366978 ps
CPU time 4.48 seconds
Started Oct 15 12:22:25 AM UTC 24
Finished Oct 15 12:22:30 AM UTC 24
Peak memory 207844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2831403054 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.2831403054
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/13.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_tl_intg_err.859918097
Short name T586
Test name
Test status
Simulation time 2828059441 ps
CPU time 4.74 seconds
Started Oct 15 12:22:25 AM UTC 24
Finished Oct 15 12:22:30 AM UTC 24
Peak memory 207608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=859918097 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_14/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.859918097
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/13.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.3221790478
Short name T593
Test name
Test status
Simulation time 67505502 ps
CPU time 1.69 seconds
Started Oct 15 12:22:34 AM UTC 24
Finished Oct 15 12:22:37 AM UTC 24
Peak memory 206692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3221790478 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_
reset.3221790478
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_csr_rw.304188611
Short name T591
Test name
Test status
Simulation time 56788318 ps
CPU time 1.18 seconds
Started Oct 15 12:22:34 AM UTC 24
Finished Oct 15 12:22:36 AM UTC 24
Peak memory 206620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304188611 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.304188611
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/14.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_intr_test.319134035
Short name T589
Test name
Test status
Simulation time 30473523 ps
CPU time 0.88 seconds
Started Oct 15 12:22:34 AM UTC 24
Finished Oct 15 12:22:36 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319134035 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.319134035
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/14.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_same_csr_outstanding.512889464
Short name T592
Test name
Test status
Simulation time 300825145 ps
CPU time 1.42 seconds
Started Oct 15 12:22:34 AM UTC 24
Finished Oct 15 12:22:37 AM UTC 24
Peak memory 206572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=512889464 -assert nopostproc +UVM
_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_csr_outstanding.512889464
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/14.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_tl_errors.946714775
Short name T590
Test name
Test status
Simulation time 740541817 ps
CPU time 5.39 seconds
Started Oct 15 12:22:30 AM UTC 24
Finished Oct 15 12:22:36 AM UTC 24
Peak memory 207492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=946714775 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.946714775
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/14.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_tl_intg_err.3274219859
Short name T141
Test name
Test status
Simulation time 170945494 ps
CPU time 4.91 seconds
Started Oct 15 12:22:34 AM UTC 24
Finished Oct 15 12:22:40 AM UTC 24
Peak memory 207764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3274219859 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.3274219859
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/14.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.772858778
Short name T596
Test name
Test status
Simulation time 69990499 ps
CPU time 2.26 seconds
Started Oct 15 12:22:38 AM UTC 24
Finished Oct 15 12:22:41 AM UTC 24
Peak memory 223140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=772858778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_r
eset.772858778
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_csr_rw.224950672
Short name T595
Test name
Test status
Simulation time 77446448 ps
CPU time 1.3 seconds
Started Oct 15 12:22:38 AM UTC 24
Finished Oct 15 12:22:40 AM UTC 24
Peak memory 206568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=224950672 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.224950672
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/15.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_intr_test.1985625063
Short name T594
Test name
Test status
Simulation time 15432221 ps
CPU time 0.94 seconds
Started Oct 15 12:22:38 AM UTC 24
Finished Oct 15 12:22:39 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1985625063 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.1985625063
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/15.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_same_csr_outstanding.2604760483
Short name T597
Test name
Test status
Simulation time 109724494 ps
CPU time 2.81 seconds
Started Oct 15 12:22:38 AM UTC 24
Finished Oct 15 12:22:41 AM UTC 24
Peak memory 207568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2604760483 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_csr_outstanding.2604760483
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/15.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_tl_errors.3634913125
Short name T599
Test name
Test status
Simulation time 157832411 ps
CPU time 4.36 seconds
Started Oct 15 12:22:37 AM UTC 24
Finished Oct 15 12:22:43 AM UTC 24
Peak memory 207564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3634913125 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.3634913125
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/15.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_tl_intg_err.1986858160
Short name T144
Test name
Test status
Simulation time 2661002673 ps
CPU time 4.47 seconds
Started Oct 15 12:22:37 AM UTC 24
Finished Oct 15 12:22:43 AM UTC 24
Peak memory 207892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1986858160 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.1986858160
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/15.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.959966927
Short name T604
Test name
Test status
Simulation time 700712697 ps
CPU time 1.87 seconds
Started Oct 15 12:22:44 AM UTC 24
Finished Oct 15 12:22:47 AM UTC 24
Peak memory 206632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=959966927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_r
eset.959966927
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_csr_rw.1141144176
Short name T600
Test name
Test status
Simulation time 51127442 ps
CPU time 1.02 seconds
Started Oct 15 12:22:42 AM UTC 24
Finished Oct 15 12:22:44 AM UTC 24
Peak memory 205768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1141144176 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.1141144176
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/16.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_intr_test.2171419406
Short name T598
Test name
Test status
Simulation time 118004897 ps
CPU time 0.83 seconds
Started Oct 15 12:22:41 AM UTC 24
Finished Oct 15 12:22:43 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2171419406 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.2171419406
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/16.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_same_csr_outstanding.4293574211
Short name T601
Test name
Test status
Simulation time 62067236 ps
CPU time 1.65 seconds
Started Oct 15 12:22:42 AM UTC 24
Finished Oct 15 12:22:45 AM UTC 24
Peak memory 206844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4293574211 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_csr_outstanding.4293574211
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/16.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_tl_errors.2466508227
Short name T602
Test name
Test status
Simulation time 434829702 ps
CPU time 3.46 seconds
Started Oct 15 12:22:41 AM UTC 24
Finished Oct 15 12:22:45 AM UTC 24
Peak memory 207700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466508227 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.2466508227
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/16.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_tl_intg_err.3656809346
Short name T145
Test name
Test status
Simulation time 306750246 ps
CPU time 4.95 seconds
Started Oct 15 12:22:41 AM UTC 24
Finished Oct 15 12:22:47 AM UTC 24
Peak memory 207828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3656809346 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.3656809346
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/16.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.781038724
Short name T610
Test name
Test status
Simulation time 161214982 ps
CPU time 3.12 seconds
Started Oct 15 12:22:47 AM UTC 24
Finished Oct 15 12:22:51 AM UTC 24
Peak memory 215748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=781038724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_r
eset.781038724
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_csr_rw.2198753951
Short name T605
Test name
Test status
Simulation time 17601973 ps
CPU time 1.1 seconds
Started Oct 15 12:22:45 AM UTC 24
Finished Oct 15 12:22:47 AM UTC 24
Peak memory 206568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198753951 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.2198753951
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/17.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_intr_test.3886365987
Short name T603
Test name
Test status
Simulation time 77993343 ps
CPU time 0.88 seconds
Started Oct 15 12:22:44 AM UTC 24
Finished Oct 15 12:22:46 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3886365987 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.3886365987
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/17.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_same_csr_outstanding.1113871984
Short name T608
Test name
Test status
Simulation time 206823591 ps
CPU time 2.16 seconds
Started Oct 15 12:22:45 AM UTC 24
Finished Oct 15 12:22:49 AM UTC 24
Peak memory 207568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1113871984 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_csr_outstanding.1113871984
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/17.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_tl_errors.4221695097
Short name T606
Test name
Test status
Simulation time 536855896 ps
CPU time 3.05 seconds
Started Oct 15 12:22:44 AM UTC 24
Finished Oct 15 12:22:48 AM UTC 24
Peak memory 207476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4221695097 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.4221695097
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/17.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_tl_intg_err.2160237682
Short name T607
Test name
Test status
Simulation time 179227518 ps
CPU time 3.35 seconds
Started Oct 15 12:22:44 AM UTC 24
Finished Oct 15 12:22:49 AM UTC 24
Peak memory 207444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2160237682 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.2160237682
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/17.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.2629177268
Short name T615
Test name
Test status
Simulation time 253753162 ps
CPU time 2.67 seconds
Started Oct 15 12:22:50 AM UTC 24
Finished Oct 15 12:22:54 AM UTC 24
Peak memory 215852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2629177268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_
reset.2629177268
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_csr_rw.4140538143
Short name T611
Test name
Test status
Simulation time 32711898 ps
CPU time 1.23 seconds
Started Oct 15 12:22:49 AM UTC 24
Finished Oct 15 12:22:51 AM UTC 24
Peak memory 206568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4140538143 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.4140538143
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/18.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_intr_test.3279694556
Short name T609
Test name
Test status
Simulation time 23943009 ps
CPU time 0.85 seconds
Started Oct 15 12:22:48 AM UTC 24
Finished Oct 15 12:22:50 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279694556 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.3279694556
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/18.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_same_csr_outstanding.1840086029
Short name T613
Test name
Test status
Simulation time 532900667 ps
CPU time 2.66 seconds
Started Oct 15 12:22:49 AM UTC 24
Finished Oct 15 12:22:52 AM UTC 24
Peak memory 207492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840086029 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_csr_outstanding.1840086029
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/18.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_tl_errors.4233132778
Short name T612
Test name
Test status
Simulation time 212220678 ps
CPU time 4.74 seconds
Started Oct 15 12:22:47 AM UTC 24
Finished Oct 15 12:22:52 AM UTC 24
Peak memory 207544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4233132778 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.4233132778
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/18.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_tl_intg_err.3609138379
Short name T136
Test name
Test status
Simulation time 1101893592 ps
CPU time 5.51 seconds
Started Oct 15 12:22:48 AM UTC 24
Finished Oct 15 12:22:54 AM UTC 24
Peak memory 207832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3609138379 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.3609138379
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/18.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.1422828475
Short name T629
Test name
Test status
Simulation time 42322534 ps
CPU time 3.72 seconds
Started Oct 15 12:22:54 AM UTC 24
Finished Oct 15 12:22:59 AM UTC 24
Peak memory 215740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1422828475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_
reset.1422828475
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_csr_rw.1981301018
Short name T617
Test name
Test status
Simulation time 55869626 ps
CPU time 0.98 seconds
Started Oct 15 12:22:53 AM UTC 24
Finished Oct 15 12:22:55 AM UTC 24
Peak memory 207156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1981301018 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.1981301018
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/19.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_intr_test.183461083
Short name T614
Test name
Test status
Simulation time 14797194 ps
CPU time 0.89 seconds
Started Oct 15 12:22:51 AM UTC 24
Finished Oct 15 12:22:53 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=183461083 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.183461083
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/19.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_same_csr_outstanding.4214453669
Short name T621
Test name
Test status
Simulation time 240642977 ps
CPU time 2.62 seconds
Started Oct 15 12:22:53 AM UTC 24
Finished Oct 15 12:22:56 AM UTC 24
Peak memory 207496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4214453669 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_csr_outstanding.4214453669
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/19.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_tl_errors.2681997816
Short name T618
Test name
Test status
Simulation time 64352442 ps
CPU time 4.3 seconds
Started Oct 15 12:22:50 AM UTC 24
Finished Oct 15 12:22:55 AM UTC 24
Peak memory 207700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2681997816 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.2681997816
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/19.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_tl_intg_err.788462503
Short name T616
Test name
Test status
Simulation time 170856236 ps
CPU time 2.61 seconds
Started Oct 15 12:22:50 AM UTC 24
Finished Oct 15 12:22:54 AM UTC 24
Peak memory 207516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=788462503 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_14/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.788462503
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/19.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_aliasing.3682581217
Short name T110
Test name
Test status
Simulation time 1918079431 ps
CPU time 11.42 seconds
Started Oct 15 12:21:21 AM UTC 24
Finished Oct 15 12:21:33 AM UTC 24
Peak memory 207496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682581217 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.3682581217
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/2.hmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_bit_bash.3572789041
Short name T541
Test name
Test status
Simulation time 721294471 ps
CPU time 16.24 seconds
Started Oct 15 12:21:19 AM UTC 24
Finished Oct 15 12:21:36 AM UTC 24
Peak memory 207440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3572789041 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.3572789041
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/2.hmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_hw_reset.2869353921
Short name T106
Test name
Test status
Simulation time 49484183 ps
CPU time 1.01 seconds
Started Oct 15 12:21:17 AM UTC 24
Finished Oct 15 12:21:19 AM UTC 24
Peak memory 206280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2869353921 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.2869353921
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/2.hmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.3330309180
Short name T537
Test name
Test status
Simulation time 109652145 ps
CPU time 3.71 seconds
Started Oct 15 12:21:22 AM UTC 24
Finished Oct 15 12:21:27 AM UTC 24
Peak memory 223468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3330309180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_r
eset.3330309180
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_rw.2425851242
Short name T108
Test name
Test status
Simulation time 39883899 ps
CPU time 1.37 seconds
Started Oct 15 12:21:19 AM UTC 24
Finished Oct 15 12:21:21 AM UTC 24
Peak memory 206572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2425851242 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.2425851242
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/2.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_intr_test.47690164
Short name T536
Test name
Test status
Simulation time 26951477 ps
CPU time 0.86 seconds
Started Oct 15 12:21:15 AM UTC 24
Finished Oct 15 12:21:17 AM UTC 24
Peak memory 203092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47690164 -assert nopostproc +UVM_TESTNAME=hmac_base_te
st +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.47690164
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/2.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_same_csr_outstanding.3467271939
Short name T119
Test name
Test status
Simulation time 425516097 ps
CPU time 3.42 seconds
Started Oct 15 12:21:22 AM UTC 24
Finished Oct 15 12:21:26 AM UTC 24
Peak memory 207688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3467271939 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr_outstanding.3467271939
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/2.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_tl_errors.3328630614
Short name T535
Test name
Test status
Simulation time 215486597 ps
CPU time 4.13 seconds
Started Oct 15 12:21:11 AM UTC 24
Finished Oct 15 12:21:16 AM UTC 24
Peak memory 207516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328630614 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.3328630614
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/2.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_tl_intg_err.4279505802
Short name T63
Test name
Test status
Simulation time 4857783452 ps
CPU time 6.36 seconds
Started Oct 15 12:21:14 AM UTC 24
Finished Oct 15 12:21:22 AM UTC 24
Peak memory 207828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4279505802 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.4279505802
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/2.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/20.hmac_intr_test.2793897512
Short name T619
Test name
Test status
Simulation time 46068644 ps
CPU time 0.91 seconds
Started Oct 15 12:22:54 AM UTC 24
Finished Oct 15 12:22:56 AM UTC 24
Peak memory 203084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793897512 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.2793897512
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/20.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/21.hmac_intr_test.284707010
Short name T620
Test name
Test status
Simulation time 15390298 ps
CPU time 0.91 seconds
Started Oct 15 12:22:54 AM UTC 24
Finished Oct 15 12:22:56 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284707010 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.284707010
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/21.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/22.hmac_intr_test.65153136
Short name T622
Test name
Test status
Simulation time 29795274 ps
CPU time 0.89 seconds
Started Oct 15 12:22:55 AM UTC 24
Finished Oct 15 12:22:57 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=65153136 -assert nopostproc +UVM_TESTNAME=hmac_base_te
st +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.65153136
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/22.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/23.hmac_intr_test.161149394
Short name T625
Test name
Test status
Simulation time 27784207 ps
CPU time 0.9 seconds
Started Oct 15 12:22:55 AM UTC 24
Finished Oct 15 12:22:57 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=161149394 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.161149394
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/23.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/24.hmac_intr_test.4118826191
Short name T623
Test name
Test status
Simulation time 36991095 ps
CPU time 0.8 seconds
Started Oct 15 12:22:55 AM UTC 24
Finished Oct 15 12:22:57 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4118826191 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.4118826191
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/24.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/25.hmac_intr_test.941780266
Short name T624
Test name
Test status
Simulation time 82804849 ps
CPU time 0.85 seconds
Started Oct 15 12:22:55 AM UTC 24
Finished Oct 15 12:22:57 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941780266 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.941780266
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/25.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/26.hmac_intr_test.246328872
Short name T627
Test name
Test status
Simulation time 35472593 ps
CPU time 0.92 seconds
Started Oct 15 12:22:56 AM UTC 24
Finished Oct 15 12:22:58 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246328872 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.246328872
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/26.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/27.hmac_intr_test.3668125499
Short name T626
Test name
Test status
Simulation time 16151111 ps
CPU time 0.8 seconds
Started Oct 15 12:22:56 AM UTC 24
Finished Oct 15 12:22:58 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3668125499 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.3668125499
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/27.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/28.hmac_intr_test.2214786404
Short name T628
Test name
Test status
Simulation time 64753813 ps
CPU time 0.93 seconds
Started Oct 15 12:22:56 AM UTC 24
Finished Oct 15 12:22:58 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214786404 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.2214786404
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/28.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/29.hmac_intr_test.3826339732
Short name T630
Test name
Test status
Simulation time 16115585 ps
CPU time 0.82 seconds
Started Oct 15 12:22:57 AM UTC 24
Finished Oct 15 12:22:59 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3826339732 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.3826339732
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/29.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_aliasing.148576361
Short name T113
Test name
Test status
Simulation time 580610266 ps
CPU time 11.76 seconds
Started Oct 15 12:21:30 AM UTC 24
Finished Oct 15 12:21:43 AM UTC 24
Peak memory 207504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=148576361 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.148576361
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/3.hmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_bit_bash.3285731549
Short name T545
Test name
Test status
Simulation time 2533942278 ps
CPU time 16.66 seconds
Started Oct 15 12:21:30 AM UTC 24
Finished Oct 15 12:21:48 AM UTC 24
Peak memory 207504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3285731549 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.3285731549
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/3.hmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_hw_reset.475696845
Short name T109
Test name
Test status
Simulation time 33813534 ps
CPU time 1.43 seconds
Started Oct 15 12:21:27 AM UTC 24
Finished Oct 15 12:21:30 AM UTC 24
Peak memory 206628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475696845 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.475696845
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/3.hmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.1612734237
Short name T540
Test name
Test status
Simulation time 117291717 ps
CPU time 2.38 seconds
Started Oct 15 12:21:32 AM UTC 24
Finished Oct 15 12:21:35 AM UTC 24
Peak memory 215824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1612734237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_r
eset.1612734237
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_rw.3475057837
Short name T120
Test name
Test status
Simulation time 13217905 ps
CPU time 0.99 seconds
Started Oct 15 12:21:28 AM UTC 24
Finished Oct 15 12:21:30 AM UTC 24
Peak memory 207100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475057837 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.3475057837
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/3.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_intr_test.4153852388
Short name T539
Test name
Test status
Simulation time 40560068 ps
CPU time 0.83 seconds
Started Oct 15 12:21:27 AM UTC 24
Finished Oct 15 12:21:29 AM UTC 24
Peak memory 203092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4153852388 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.4153852388
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/3.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_same_csr_outstanding.634591599
Short name T121
Test name
Test status
Simulation time 35609221 ps
CPU time 2.27 seconds
Started Oct 15 12:21:30 AM UTC 24
Finished Oct 15 12:21:34 AM UTC 24
Peak memory 207708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=634591599 -assert nopostproc +UVM
_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr_outstanding.634591599
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/3.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_tl_errors.950634174
Short name T538
Test name
Test status
Simulation time 180509564 ps
CPU time 2.85 seconds
Started Oct 15 12:21:23 AM UTC 24
Finished Oct 15 12:21:27 AM UTC 24
Peak memory 207760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=950634174 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.950634174
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/3.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_tl_intg_err.569859325
Short name T134
Test name
Test status
Simulation time 213658734 ps
CPU time 4.36 seconds
Started Oct 15 12:21:24 AM UTC 24
Finished Oct 15 12:21:29 AM UTC 24
Peak memory 207540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=569859325 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_14/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.569859325
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/3.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/30.hmac_intr_test.2440708329
Short name T631
Test name
Test status
Simulation time 54170633 ps
CPU time 0.87 seconds
Started Oct 15 12:22:57 AM UTC 24
Finished Oct 15 12:23:00 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440708329 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.2440708329
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/30.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/31.hmac_intr_test.3809894283
Short name T632
Test name
Test status
Simulation time 11396670 ps
CPU time 0.86 seconds
Started Oct 15 12:22:58 AM UTC 24
Finished Oct 15 12:23:00 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3809894283 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.3809894283
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/31.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/32.hmac_intr_test.1552309277
Short name T633
Test name
Test status
Simulation time 14847439 ps
CPU time 0.85 seconds
Started Oct 15 12:22:58 AM UTC 24
Finished Oct 15 12:23:00 AM UTC 24
Peak memory 203084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1552309277 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.1552309277
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/32.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/33.hmac_intr_test.2025759319
Short name T634
Test name
Test status
Simulation time 19625819 ps
CPU time 0.86 seconds
Started Oct 15 12:22:58 AM UTC 24
Finished Oct 15 12:23:00 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025759319 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.2025759319
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/33.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/34.hmac_intr_test.134186125
Short name T635
Test name
Test status
Simulation time 12273121 ps
CPU time 0.81 seconds
Started Oct 15 12:22:59 AM UTC 24
Finished Oct 15 12:23:00 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=134186125 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.134186125
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/34.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/35.hmac_intr_test.98844298
Short name T636
Test name
Test status
Simulation time 13098627 ps
CPU time 0.87 seconds
Started Oct 15 12:22:59 AM UTC 24
Finished Oct 15 12:23:01 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=98844298 -assert nopostproc +UVM_TESTNAME=hmac_base_te
st +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.98844298
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/35.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/36.hmac_intr_test.3896627272
Short name T637
Test name
Test status
Simulation time 87558916 ps
CPU time 0.92 seconds
Started Oct 15 12:22:59 AM UTC 24
Finished Oct 15 12:23:01 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896627272 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.3896627272
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/36.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/37.hmac_intr_test.4091867780
Short name T638
Test name
Test status
Simulation time 14246089 ps
CPU time 0.87 seconds
Started Oct 15 12:23:00 AM UTC 24
Finished Oct 15 12:23:02 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4091867780 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.4091867780
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/37.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/38.hmac_intr_test.1464471934
Short name T639
Test name
Test status
Simulation time 20861922 ps
CPU time 0.85 seconds
Started Oct 15 12:23:00 AM UTC 24
Finished Oct 15 12:23:02 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1464471934 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.1464471934
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/38.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/39.hmac_intr_test.1749549077
Short name T641
Test name
Test status
Simulation time 14279919 ps
CPU time 0.85 seconds
Started Oct 15 12:23:00 AM UTC 24
Finished Oct 15 12:23:02 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749549077 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.1749549077
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/39.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_aliasing.1623507514
Short name T114
Test name
Test status
Simulation time 736645556 ps
CPU time 9.35 seconds
Started Oct 15 12:21:40 AM UTC 24
Finished Oct 15 12:21:51 AM UTC 24
Peak memory 207496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623507514 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.1623507514
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/4.hmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_bit_bash.566684938
Short name T115
Test name
Test status
Simulation time 2945783473 ps
CPU time 11.31 seconds
Started Oct 15 12:21:40 AM UTC 24
Finished Oct 15 12:21:53 AM UTC 24
Peak memory 207872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=566684938 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.566684938
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/4.hmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_hw_reset.2444945925
Short name T543
Test name
Test status
Simulation time 78852147 ps
CPU time 0.97 seconds
Started Oct 15 12:21:37 AM UTC 24
Finished Oct 15 12:21:39 AM UTC 24
Peak memory 205512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2444945925 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.2444945925
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/4.hmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.2875040532
Short name T652
Test name
Test status
Simulation time 139788952718 ps
CPU time 731.58 seconds
Started Oct 15 12:21:42 AM UTC 24
Finished Oct 15 12:34:03 AM UTC 24
Peak memory 230152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2875040532 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_r
eset.2875040532
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_rw.2305373206
Short name T111
Test name
Test status
Simulation time 542958453 ps
CPU time 1.38 seconds
Started Oct 15 12:21:39 AM UTC 24
Finished Oct 15 12:21:42 AM UTC 24
Peak memory 206572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2305373206 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.2305373206
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/4.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_intr_test.457136948
Short name T542
Test name
Test status
Simulation time 17166030 ps
CPU time 0.78 seconds
Started Oct 15 12:21:36 AM UTC 24
Finished Oct 15 12:21:38 AM UTC 24
Peak memory 203096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=457136948 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.457136948
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/4.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_same_csr_outstanding.1784289350
Short name T122
Test name
Test status
Simulation time 85030974 ps
CPU time 1.62 seconds
Started Oct 15 12:21:42 AM UTC 24
Finished Oct 15 12:21:45 AM UTC 24
Peak memory 206568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784289350 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr_outstanding.1784289350
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/4.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_tl_errors.1759421731
Short name T544
Test name
Test status
Simulation time 127593422 ps
CPU time 4.84 seconds
Started Oct 15 12:21:34 AM UTC 24
Finished Oct 15 12:21:39 AM UTC 24
Peak memory 207784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1759421731 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.1759421731
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/4.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/40.hmac_intr_test.3974417561
Short name T640
Test name
Test status
Simulation time 30707904 ps
CPU time 0.8 seconds
Started Oct 15 12:23:00 AM UTC 24
Finished Oct 15 12:23:02 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3974417561 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.3974417561
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/40.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/41.hmac_intr_test.3698062969
Short name T642
Test name
Test status
Simulation time 18600661 ps
CPU time 0.91 seconds
Started Oct 15 12:23:01 AM UTC 24
Finished Oct 15 12:23:03 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3698062969 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.3698062969
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/41.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/42.hmac_intr_test.1212408334
Short name T643
Test name
Test status
Simulation time 43755492 ps
CPU time 0.87 seconds
Started Oct 15 12:23:01 AM UTC 24
Finished Oct 15 12:23:03 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1212408334 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.1212408334
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/42.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/43.hmac_intr_test.1134538273
Short name T644
Test name
Test status
Simulation time 18775451 ps
CPU time 0.96 seconds
Started Oct 15 12:23:01 AM UTC 24
Finished Oct 15 12:23:03 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1134538273 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.1134538273
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/43.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/44.hmac_intr_test.4085682013
Short name T645
Test name
Test status
Simulation time 37535869 ps
CPU time 0.95 seconds
Started Oct 15 12:23:01 AM UTC 24
Finished Oct 15 12:23:03 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085682013 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.4085682013
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/44.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/45.hmac_intr_test.242663172
Short name T646
Test name
Test status
Simulation time 15219155 ps
CPU time 0.86 seconds
Started Oct 15 12:23:01 AM UTC 24
Finished Oct 15 12:23:03 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=242663172 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.242663172
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/45.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/46.hmac_intr_test.2594562650
Short name T648
Test name
Test status
Simulation time 16241600 ps
CPU time 0.92 seconds
Started Oct 15 12:23:03 AM UTC 24
Finished Oct 15 12:23:04 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2594562650 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.2594562650
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/46.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/47.hmac_intr_test.1365693762
Short name T647
Test name
Test status
Simulation time 43857926 ps
CPU time 0.89 seconds
Started Oct 15 12:23:03 AM UTC 24
Finished Oct 15 12:23:04 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365693762 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.1365693762
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/47.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/48.hmac_intr_test.2792960289
Short name T650
Test name
Test status
Simulation time 13010622 ps
CPU time 0.86 seconds
Started Oct 15 12:23:03 AM UTC 24
Finished Oct 15 12:23:05 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2792960289 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.2792960289
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/48.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/49.hmac_intr_test.1630105345
Short name T649
Test name
Test status
Simulation time 47386885 ps
CPU time 0.8 seconds
Started Oct 15 12:23:03 AM UTC 24
Finished Oct 15 12:23:04 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630105345 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.1630105345
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/49.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.3176071310
Short name T550
Test name
Test status
Simulation time 171876821 ps
CPU time 1.88 seconds
Started Oct 15 12:21:49 AM UTC 24
Finished Oct 15 12:21:52 AM UTC 24
Peak memory 206652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3176071310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_r
eset.3176071310
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_csr_rw.1573700982
Short name T548
Test name
Test status
Simulation time 18039370 ps
CPU time 1.05 seconds
Started Oct 15 12:21:47 AM UTC 24
Finished Oct 15 12:21:49 AM UTC 24
Peak memory 206572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573700982 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.1573700982
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/5.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_intr_test.639875440
Short name T547
Test name
Test status
Simulation time 44012767 ps
CPU time 0.77 seconds
Started Oct 15 12:21:47 AM UTC 24
Finished Oct 15 12:21:49 AM UTC 24
Peak memory 203096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639875440 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.639875440
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/5.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_same_csr_outstanding.2080549644
Short name T551
Test name
Test status
Simulation time 113123438 ps
CPU time 1.88 seconds
Started Oct 15 12:21:49 AM UTC 24
Finished Oct 15 12:21:52 AM UTC 24
Peak memory 206588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2080549644 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr_outstanding.2080549644
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/5.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_tl_errors.3377869214
Short name T546
Test name
Test status
Simulation time 43230917 ps
CPU time 3.64 seconds
Started Oct 15 12:21:44 AM UTC 24
Finished Oct 15 12:21:49 AM UTC 24
Peak memory 207436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3377869214 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.3377869214
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/5.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_tl_intg_err.994910757
Short name T142
Test name
Test status
Simulation time 163008898 ps
CPU time 2.64 seconds
Started Oct 15 12:21:45 AM UTC 24
Finished Oct 15 12:21:49 AM UTC 24
Peak memory 207552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=994910757 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_14/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.994910757
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/5.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.2257470056
Short name T654
Test name
Test status
Simulation time 86179234867 ps
CPU time 858.34 seconds
Started Oct 15 12:21:53 AM UTC 24
Finished Oct 15 12:36:21 AM UTC 24
Peak memory 224268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2257470056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_r
eset.2257470056
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_csr_rw.2785961402
Short name T553
Test name
Test status
Simulation time 27836238 ps
CPU time 1.18 seconds
Started Oct 15 12:21:51 AM UTC 24
Finished Oct 15 12:21:54 AM UTC 24
Peak memory 206804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2785961402 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.2785961402
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/6.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_intr_test.2990151663
Short name T552
Test name
Test status
Simulation time 15175258 ps
CPU time 0.87 seconds
Started Oct 15 12:21:50 AM UTC 24
Finished Oct 15 12:21:52 AM UTC 24
Peak memory 203092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2990151663 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.2990151663
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/6.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_same_csr_outstanding.1932695527
Short name T555
Test name
Test status
Simulation time 106067468 ps
CPU time 2.46 seconds
Started Oct 15 12:21:53 AM UTC 24
Finished Oct 15 12:21:56 AM UTC 24
Peak memory 207440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932695527 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr_outstanding.1932695527
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/6.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_tl_errors.2043974711
Short name T554
Test name
Test status
Simulation time 191998124 ps
CPU time 3.79 seconds
Started Oct 15 12:21:49 AM UTC 24
Finished Oct 15 12:21:54 AM UTC 24
Peak memory 207436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043974711 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.2043974711
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/6.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_tl_intg_err.1552828706
Short name T139
Test name
Test status
Simulation time 358010282 ps
CPU time 4.28 seconds
Started Oct 15 12:21:49 AM UTC 24
Finished Oct 15 12:21:55 AM UTC 24
Peak memory 207516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1552828706 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.1552828706
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/6.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.3620586125
Short name T559
Test name
Test status
Simulation time 101286229 ps
CPU time 3.35 seconds
Started Oct 15 12:21:58 AM UTC 24
Finished Oct 15 12:22:02 AM UTC 24
Peak memory 216052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3620586125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_r
eset.3620586125
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_csr_rw.2475267059
Short name T116
Test name
Test status
Simulation time 53554245 ps
CPU time 1.31 seconds
Started Oct 15 12:21:57 AM UTC 24
Finished Oct 15 12:22:00 AM UTC 24
Peak memory 206624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2475267059 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.2475267059
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/7.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_intr_test.901505552
Short name T556
Test name
Test status
Simulation time 52888787 ps
CPU time 0.88 seconds
Started Oct 15 12:21:57 AM UTC 24
Finished Oct 15 12:22:00 AM UTC 24
Peak memory 203096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=901505552 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.901505552
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/7.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3081291077
Short name T558
Test name
Test status
Simulation time 323590011 ps
CPU time 2.16 seconds
Started Oct 15 12:21:58 AM UTC 24
Finished Oct 15 12:22:01 AM UTC 24
Peak memory 207440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3081291077 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr_outstanding.3081291077
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/7.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_tl_errors.183400388
Short name T557
Test name
Test status
Simulation time 122430383 ps
CPU time 4.98 seconds
Started Oct 15 12:21:54 AM UTC 24
Finished Oct 15 12:22:00 AM UTC 24
Peak memory 207740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=183400388 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.183400388
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/7.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_tl_intg_err.2589179364
Short name T143
Test name
Test status
Simulation time 478290460 ps
CPU time 5.35 seconds
Started Oct 15 12:21:54 AM UTC 24
Finished Oct 15 12:22:00 AM UTC 24
Peak memory 207572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589179364 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.2589179364
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/7.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.3566990619
Short name T655
Test name
Test status
Simulation time 64438954344 ps
CPU time 991.36 seconds
Started Oct 15 12:22:02 AM UTC 24
Finished Oct 15 12:38:45 AM UTC 24
Peak memory 224012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3566990619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_r
eset.3566990619
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_csr_rw.1393440867
Short name T561
Test name
Test status
Simulation time 75968073 ps
CPU time 1.37 seconds
Started Oct 15 12:22:01 AM UTC 24
Finished Oct 15 12:22:03 AM UTC 24
Peak memory 206572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1393440867 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.1393440867
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/8.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_intr_test.2260826798
Short name T560
Test name
Test status
Simulation time 25376682 ps
CPU time 0.91 seconds
Started Oct 15 12:22:01 AM UTC 24
Finished Oct 15 12:22:03 AM UTC 24
Peak memory 203092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2260826798 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.2260826798
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/8.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_same_csr_outstanding.3115893098
Short name T563
Test name
Test status
Simulation time 145231742 ps
CPU time 2.63 seconds
Started Oct 15 12:22:01 AM UTC 24
Finished Oct 15 12:22:05 AM UTC 24
Peak memory 207440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3115893098 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr_outstanding.3115893098
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/8.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_tl_errors.839449543
Short name T562
Test name
Test status
Simulation time 61117343 ps
CPU time 4.73 seconds
Started Oct 15 12:21:58 AM UTC 24
Finished Oct 15 12:22:04 AM UTC 24
Peak memory 207440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839449543 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.839449543
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/8.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_tl_intg_err.3913834988
Short name T565
Test name
Test status
Simulation time 511713330 ps
CPU time 4.72 seconds
Started Oct 15 12:22:01 AM UTC 24
Finished Oct 15 12:22:07 AM UTC 24
Peak memory 207408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3913834988 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.3913834988
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/8.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.3422126269
Short name T653
Test name
Test status
Simulation time 914071830974 ps
CPU time 798.72 seconds
Started Oct 15 12:22:07 AM UTC 24
Finished Oct 15 12:35:36 AM UTC 24
Peak memory 224116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3422126269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_r
eset.3422126269
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_csr_rw.4224004897
Short name T566
Test name
Test status
Simulation time 60070287 ps
CPU time 1.31 seconds
Started Oct 15 12:22:05 AM UTC 24
Finished Oct 15 12:22:08 AM UTC 24
Peak memory 206572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4224004897 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.4224004897
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/9.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_intr_test.752362513
Short name T564
Test name
Test status
Simulation time 22238805 ps
CPU time 0.88 seconds
Started Oct 15 12:22:04 AM UTC 24
Finished Oct 15 12:22:06 AM UTC 24
Peak memory 203096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=752362513 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.752362513
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/9.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_same_csr_outstanding.1873306748
Short name T567
Test name
Test status
Simulation time 107018809 ps
CPU time 1.74 seconds
Started Oct 15 12:22:05 AM UTC 24
Finished Oct 15 12:22:08 AM UTC 24
Peak memory 206568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1873306748 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr_outstanding.1873306748
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/9.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_tl_errors.1972152467
Short name T568
Test name
Test status
Simulation time 352935188 ps
CPU time 4.84 seconds
Started Oct 15 12:22:03 AM UTC 24
Finished Oct 15 12:22:09 AM UTC 24
Peak memory 207472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1972152467 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.1972152467
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/9.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_tl_intg_err.391550387
Short name T137
Test name
Test status
Simulation time 212600158 ps
CPU time 2.36 seconds
Started Oct 15 12:22:04 AM UTC 24
Finished Oct 15 12:22:08 AM UTC 24
Peak memory 207688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=391550387 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_14/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.391550387
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/9.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/0.hmac_back_pressure.1321443833
Short name T7
Test name
Test status
Simulation time 430401332 ps
CPU time 22.37 seconds
Started Oct 14 11:52:55 PM UTC 24
Finished Oct 14 11:53:19 PM UTC 24
Peak memory 209696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1321443833 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.1321443833
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/0.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/0.hmac_burst_wr.954182065
Short name T6
Test name
Test status
Simulation time 263070790 ps
CPU time 14.34 seconds
Started Oct 14 11:52:56 PM UTC 24
Finished Oct 14 11:53:22 PM UTC 24
Peak memory 209640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=954182065 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.954182065
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/0.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/0.hmac_datapath_stress.2467841918
Short name T76
Test name
Test status
Simulation time 9803745281 ps
CPU time 210.61 seconds
Started Oct 14 11:52:55 PM UTC 24
Finished Oct 14 11:56:29 PM UTC 24
Peak memory 662008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2467841918 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.2467841918
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/0.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/0.hmac_error.2710947836
Short name T52
Test name
Test status
Simulation time 28928365514 ps
CPU time 119.65 seconds
Started Oct 14 11:52:56 PM UTC 24
Finished Oct 14 11:55:08 PM UTC 24
Peak memory 209728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2710947836 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.2710947836
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/0.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/0.hmac_long_msg.3970261373
Short name T47
Test name
Test status
Simulation time 37391097322 ps
CPU time 161.41 seconds
Started Oct 14 11:52:54 PM UTC 24
Finished Oct 14 11:55:39 PM UTC 24
Peak memory 207960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3970261373 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.3970261373
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/0.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/0.hmac_sec_cm.2882749482
Short name T2
Test name
Test status
Simulation time 82799146 ps
CPU time 0.9 seconds
Started Oct 14 11:52:59 PM UTC 24
Finished Oct 14 11:53:02 PM UTC 24
Peak memory 238012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882749482 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.2882749482
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/0.hmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/0.hmac_stress_all.2166637515
Short name T29
Test name
Test status
Simulation time 8539565128 ps
CPU time 32.81 seconds
Started Oct 14 11:52:59 PM UTC 24
Finished Oct 14 11:53:34 PM UTC 24
Peak memory 209696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2166637515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.2166637515
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/0.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/0.hmac_test_hmac384_vectors.4275303305
Short name T168
Test name
Test status
Simulation time 21012172974 ps
CPU time 75.99 seconds
Started Oct 14 11:52:58 PM UTC 24
Finished Oct 14 11:54:18 PM UTC 24
Peak memory 209768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4275303305 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac384_vectors.4275303305
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/0.hmac_test_hmac384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/0.hmac_test_hmac512_vectors.1150531382
Short name T175
Test name
Test status
Simulation time 11859447247 ps
CPU time 112.49 seconds
Started Oct 14 11:52:58 PM UTC 24
Finished Oct 14 11:54:55 PM UTC 24
Peak memory 209840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1150531382 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac512_vectors.1150531382
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/0.hmac_test_hmac512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/0.hmac_test_sha384_vectors.1598929612
Short name T510
Test name
Test status
Simulation time 565431851975 ps
CPU time 2504.61 seconds
Started Oct 14 11:52:58 PM UTC 24
Finished Oct 15 12:35:13 AM UTC 24
Peak memory 229736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1598929612 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha384_vectors.1598929612
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/0.hmac_test_sha384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/0.hmac_test_sha512_vectors.3562372474
Short name T503
Test name
Test status
Simulation time 39739360023 ps
CPU time 2360 seconds
Started Oct 14 11:52:58 PM UTC 24
Finished Oct 15 12:32:48 AM UTC 24
Peak memory 228268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3562372474 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha512_vectors.3562372474
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/0.hmac_test_sha512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/0.hmac_wipe_secret.1667531519
Short name T16
Test name
Test status
Simulation time 4121713384 ps
CPU time 26.06 seconds
Started Oct 14 11:52:57 PM UTC 24
Finished Oct 14 11:53:28 PM UTC 24
Peak memory 209704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1667531519 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.1667531519
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/0.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/1.hmac_alert_test.850883262
Short name T28
Test name
Test status
Simulation time 12869126 ps
CPU time 0.87 seconds
Started Oct 14 11:53:11 PM UTC 24
Finished Oct 14 11:53:13 PM UTC 24
Peak memory 206316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=850883262 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.850883262
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/1.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/1.hmac_back_pressure.104531246
Short name T17
Test name
Test status
Simulation time 2888470470 ps
CPU time 92.55 seconds
Started Oct 14 11:53:02 PM UTC 24
Finished Oct 14 11:54:37 PM UTC 24
Peak memory 209760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=104531246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.104531246
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/1.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/1.hmac_burst_wr.2239546880
Short name T5
Test name
Test status
Simulation time 335752792 ps
CPU time 5.68 seconds
Started Oct 14 11:53:04 PM UTC 24
Finished Oct 14 11:53:12 PM UTC 24
Peak memory 209708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239546880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.2239546880
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/1.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/1.hmac_datapath_stress.845675407
Short name T287
Test name
Test status
Simulation time 4464392054 ps
CPU time 747.68 seconds
Started Oct 14 11:53:02 PM UTC 24
Finished Oct 15 12:05:38 AM UTC 24
Peak memory 735788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=845675407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.845675407
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/1.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/1.hmac_error.2417874931
Short name T146
Test name
Test status
Simulation time 20776948572 ps
CPU time 150.96 seconds
Started Oct 14 11:53:05 PM UTC 24
Finished Oct 14 11:55:39 PM UTC 24
Peak memory 209688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2417874931 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.2417874931
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/1.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/1.hmac_long_msg.1513861124
Short name T190
Test name
Test status
Simulation time 34907213746 ps
CPU time 242.35 seconds
Started Oct 14 11:53:02 PM UTC 24
Finished Oct 14 11:57:08 PM UTC 24
Peak memory 218408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1513861124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.1513861124
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/1.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/1.hmac_stress_all.3486912493
Short name T78
Test name
Test status
Simulation time 173197338034 ps
CPU time 987.55 seconds
Started Oct 14 11:53:07 PM UTC 24
Finished Oct 15 12:09:45 AM UTC 24
Peak memory 764412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3486912493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.3486912493
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/1.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/1.hmac_test_hmac256_vectors.3933290367
Short name T54
Test name
Test status
Simulation time 4892654134 ps
CPU time 48.86 seconds
Started Oct 14 11:53:07 PM UTC 24
Finished Oct 14 11:53:57 PM UTC 24
Peak memory 209840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933290367 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac256_vectors.3933290367
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/1.hmac_test_hmac256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/1.hmac_test_hmac384_vectors.3880093678
Short name T50
Test name
Test status
Simulation time 2233750872 ps
CPU time 78.8 seconds
Started Oct 14 11:53:07 PM UTC 24
Finished Oct 14 11:54:27 PM UTC 24
Peak memory 209840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3880093678 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac384_vectors.3880093678
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/1.hmac_test_hmac384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/1.hmac_test_hmac512_vectors.728665370
Short name T167
Test name
Test status
Simulation time 5550646715 ps
CPU time 76.67 seconds
Started Oct 14 11:53:07 PM UTC 24
Finished Oct 14 11:54:25 PM UTC 24
Peak memory 209848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=728665370 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac512_vectors.728665370
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/1.hmac_test_hmac512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/1.hmac_test_sha256_vectors.1675455808
Short name T152
Test name
Test status
Simulation time 31985271488 ps
CPU time 664.32 seconds
Started Oct 14 11:53:06 PM UTC 24
Finished Oct 15 12:04:18 AM UTC 24
Peak memory 209648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1675455808 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha256_vectors.1675455808
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/1.hmac_test_sha256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/1.hmac_test_sha384_vectors.3232338621
Short name T507
Test name
Test status
Simulation time 135932403961 ps
CPU time 2451.45 seconds
Started Oct 14 11:53:06 PM UTC 24
Finished Oct 15 12:34:24 AM UTC 24
Peak memory 229736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3232338621 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha384_vectors.3232338621
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/1.hmac_test_sha384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/1.hmac_test_sha512_vectors.740156059
Short name T505
Test name
Test status
Simulation time 136049186368 ps
CPU time 2396.61 seconds
Started Oct 14 11:53:06 PM UTC 24
Finished Oct 15 12:33:29 AM UTC 24
Peak memory 223796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740156059 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha512_vectors.740156059
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/1.hmac_test_sha512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/1.hmac_wipe_secret.3542005490
Short name T10
Test name
Test status
Simulation time 919720933 ps
CPU time 21.52 seconds
Started Oct 14 11:53:05 PM UTC 24
Finished Oct 14 11:53:28 PM UTC 24
Peak memory 209696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3542005490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.3542005490
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/1.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/10.hmac_alert_test.3413859749
Short name T72
Test name
Test status
Simulation time 33145718 ps
CPU time 0.88 seconds
Started Oct 14 11:56:17 PM UTC 24
Finished Oct 14 11:56:19 PM UTC 24
Peak memory 206376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3413859749 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.3413859749
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/10.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/10.hmac_back_pressure.3369778658
Short name T192
Test name
Test status
Simulation time 2576442641 ps
CPU time 85.18 seconds
Started Oct 14 11:55:58 PM UTC 24
Finished Oct 14 11:57:25 PM UTC 24
Peak memory 209780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3369778658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.3369778658
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/10.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/10.hmac_datapath_stress.1944299975
Short name T324
Test name
Test status
Simulation time 16543202084 ps
CPU time 742.34 seconds
Started Oct 14 11:56:00 PM UTC 24
Finished Oct 15 12:08:31 AM UTC 24
Peak memory 707312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1944299975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.1944299975
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/10.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/10.hmac_error.1563021852
Short name T69
Test name
Test status
Simulation time 248661026 ps
CPU time 6.96 seconds
Started Oct 14 11:56:08 PM UTC 24
Finished Oct 14 11:56:16 PM UTC 24
Peak memory 209576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563021852 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.1563021852
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/10.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/10.hmac_long_msg.3954907124
Short name T36
Test name
Test status
Simulation time 5899630813 ps
CPU time 93.18 seconds
Started Oct 14 11:55:56 PM UTC 24
Finished Oct 14 11:57:31 PM UTC 24
Peak memory 209964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3954907124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.3954907124
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/10.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/10.hmac_smoke.285760210
Short name T153
Test name
Test status
Simulation time 382497087 ps
CPU time 13.28 seconds
Started Oct 14 11:55:55 PM UTC 24
Finished Oct 14 11:56:09 PM UTC 24
Peak memory 209720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=285760210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.285760210
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/10.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/10.hmac_stress_all.323129573
Short name T412
Test name
Test status
Simulation time 39171092842 ps
CPU time 1142.56 seconds
Started Oct 14 11:56:15 PM UTC 24
Finished Oct 15 12:15:31 AM UTC 24
Peak memory 422608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=323129573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.323129573
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/10.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/10.hmac_wipe_secret.2671914371
Short name T184
Test name
Test status
Simulation time 5974174260 ps
CPU time 26.64 seconds
Started Oct 14 11:56:10 PM UTC 24
Finished Oct 14 11:56:38 PM UTC 24
Peak memory 209964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2671914371 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.2671914371
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/10.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/11.hmac_alert_test.1242943187
Short name T182
Test name
Test status
Simulation time 39766153 ps
CPU time 0.88 seconds
Started Oct 14 11:56:32 PM UTC 24
Finished Oct 14 11:56:34 PM UTC 24
Peak memory 206316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1242943187 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.1242943187
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/11.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/11.hmac_back_pressure.577122766
Short name T181
Test name
Test status
Simulation time 145485652 ps
CPU time 10.95 seconds
Started Oct 14 11:56:20 PM UTC 24
Finished Oct 14 11:56:32 PM UTC 24
Peak memory 209652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577122766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.577122766
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/11.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/11.hmac_burst_wr.2547812151
Short name T186
Test name
Test status
Simulation time 2974007816 ps
CPU time 24.06 seconds
Started Oct 14 11:56:23 PM UTC 24
Finished Oct 14 11:56:48 PM UTC 24
Peak memory 209964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2547812151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.2547812151
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/11.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/11.hmac_datapath_stress.2788262180
Short name T335
Test name
Test status
Simulation time 28201520830 ps
CPU time 759.01 seconds
Started Oct 14 11:56:23 PM UTC 24
Finished Oct 15 12:09:10 AM UTC 24
Peak memory 717320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2788262180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.2788262180
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/11.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/11.hmac_error.1264302932
Short name T226
Test name
Test status
Simulation time 48179718493 ps
CPU time 230.6 seconds
Started Oct 14 11:56:26 PM UTC 24
Finished Oct 15 12:00:20 AM UTC 24
Peak memory 209952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264302932 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.1264302932
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/11.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/11.hmac_long_msg.3492754044
Short name T43
Test name
Test status
Simulation time 5551883178 ps
CPU time 102.5 seconds
Started Oct 14 11:56:20 PM UTC 24
Finished Oct 14 11:58:05 PM UTC 24
Peak memory 226072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3492754044 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.3492754044
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/11.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/11.hmac_smoke.200685924
Short name T150
Test name
Test status
Simulation time 821529883 ps
CPU time 10.28 seconds
Started Oct 14 11:56:20 PM UTC 24
Finished Oct 14 11:56:32 PM UTC 24
Peak memory 209644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=200685924 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.200685924
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/11.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/11.hmac_stress_all.751122481
Short name T495
Test name
Test status
Simulation time 262373943000 ps
CPU time 1814.02 seconds
Started Oct 14 11:56:30 PM UTC 24
Finished Oct 15 12:27:03 AM UTC 24
Peak memory 746176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=751122481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.751122481
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/11.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/11.hmac_wipe_secret.2254729663
Short name T41
Test name
Test status
Simulation time 2760374773 ps
CPU time 88.97 seconds
Started Oct 14 11:56:28 PM UTC 24
Finished Oct 14 11:57:59 PM UTC 24
Peak memory 209964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2254729663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.2254729663
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/11.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/12.hmac_alert_test.2000981903
Short name T187
Test name
Test status
Simulation time 17824504 ps
CPU time 0.89 seconds
Started Oct 14 11:56:49 PM UTC 24
Finished Oct 14 11:56:51 PM UTC 24
Peak memory 206376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2000981903 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.2000981903
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/12.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/12.hmac_back_pressure.2557717482
Short name T201
Test name
Test status
Simulation time 6158333883 ps
CPU time 107.88 seconds
Started Oct 14 11:56:37 PM UTC 24
Finished Oct 14 11:58:27 PM UTC 24
Peak memory 209688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2557717482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.2557717482
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/12.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/12.hmac_burst_wr.290901768
Short name T185
Test name
Test status
Simulation time 382993698 ps
CPU time 2.65 seconds
Started Oct 14 11:56:40 PM UTC 24
Finished Oct 14 11:56:43 PM UTC 24
Peak memory 209652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=290901768 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.290901768
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/12.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/12.hmac_datapath_stress.2462674768
Short name T347
Test name
Test status
Simulation time 12071846757 ps
CPU time 785.35 seconds
Started Oct 14 11:56:37 PM UTC 24
Finished Oct 15 12:09:51 AM UTC 24
Peak memory 754224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2462674768 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.2462674768
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/12.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/12.hmac_error.3669855427
Short name T215
Test name
Test status
Simulation time 12179719357 ps
CPU time 161.82 seconds
Started Oct 14 11:56:40 PM UTC 24
Finished Oct 14 11:59:24 PM UTC 24
Peak memory 209728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669855427 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.3669855427
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/12.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/12.hmac_long_msg.407875018
Short name T219
Test name
Test status
Simulation time 13858773756 ps
CPU time 180.15 seconds
Started Oct 14 11:56:34 PM UTC 24
Finished Oct 14 11:59:38 PM UTC 24
Peak memory 209768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=407875018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.407875018
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/12.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/12.hmac_smoke.3031247769
Short name T155
Test name
Test status
Simulation time 735896601 ps
CPU time 13.55 seconds
Started Oct 14 11:56:33 PM UTC 24
Finished Oct 14 11:56:48 PM UTC 24
Peak memory 209900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3031247769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.3031247769
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/12.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/12.hmac_stress_all.3963885133
Short name T306
Test name
Test status
Simulation time 112836296733 ps
CPU time 600.36 seconds
Started Oct 14 11:56:49 PM UTC 24
Finished Oct 15 12:06:56 AM UTC 24
Peak memory 218408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963885133 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.3963885133
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/12.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/12.hmac_wipe_secret.3744383572
Short name T40
Test name
Test status
Simulation time 5863763948 ps
CPU time 70.53 seconds
Started Oct 14 11:56:44 PM UTC 24
Finished Oct 14 11:57:56 PM UTC 24
Peak memory 209760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744383572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.3744383572
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/12.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/13.hmac_alert_test.1507845348
Short name T193
Test name
Test status
Simulation time 19091800 ps
CPU time 0.9 seconds
Started Oct 14 11:57:26 PM UTC 24
Finished Oct 14 11:57:29 PM UTC 24
Peak memory 206376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1507845348 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.1507845348
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/13.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/13.hmac_back_pressure.4207782081
Short name T24
Test name
Test status
Simulation time 409429427 ps
CPU time 28.05 seconds
Started Oct 14 11:57:00 PM UTC 24
Finished Oct 14 11:57:30 PM UTC 24
Peak memory 209692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4207782081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.4207782081
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/13.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/13.hmac_burst_wr.2688812180
Short name T205
Test name
Test status
Simulation time 8968588247 ps
CPU time 78.49 seconds
Started Oct 14 11:57:11 PM UTC 24
Finished Oct 14 11:58:32 PM UTC 24
Peak memory 209708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2688812180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.2688812180
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/13.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/13.hmac_datapath_stress.1857576
Short name T471
Test name
Test status
Simulation time 13887097427 ps
CPU time 1392.22 seconds
Started Oct 14 11:57:09 PM UTC 24
Finished Oct 15 12:20:35 AM UTC 24
Peak memory 772600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1857576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM
_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.1857576
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/13.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/13.hmac_error.2483651286
Short name T196
Test name
Test status
Simulation time 4219467780 ps
CPU time 55.49 seconds
Started Oct 14 11:57:21 PM UTC 24
Finished Oct 14 11:58:18 PM UTC 24
Peak memory 209640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2483651286 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.2483651286
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/13.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/13.hmac_long_msg.2208253410
Short name T156
Test name
Test status
Simulation time 33309974796 ps
CPU time 87.63 seconds
Started Oct 14 11:57:00 PM UTC 24
Finished Oct 14 11:58:30 PM UTC 24
Peak memory 209704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2208253410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.2208253410
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/13.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/13.hmac_smoke.36483273
Short name T188
Test name
Test status
Simulation time 446094971 ps
CPU time 6.06 seconds
Started Oct 14 11:56:52 PM UTC 24
Finished Oct 14 11:56:59 PM UTC 24
Peak memory 209968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36483273 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 13.hmac_smoke.36483273
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/13.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/13.hmac_stress_all.780744492
Short name T162
Test name
Test status
Simulation time 20315363873 ps
CPU time 312.15 seconds
Started Oct 14 11:57:23 PM UTC 24
Finished Oct 15 12:02:40 AM UTC 24
Peak memory 220404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=780744492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.780744492
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/13.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/13.hmac_wipe_secret.2092131723
Short name T98
Test name
Test status
Simulation time 8903316235 ps
CPU time 60.32 seconds
Started Oct 14 11:57:21 PM UTC 24
Finished Oct 14 11:58:23 PM UTC 24
Peak memory 209908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2092131723 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.2092131723
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/13.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/14.hmac_alert_test.2533562329
Short name T44
Test name
Test status
Simulation time 44101241 ps
CPU time 0.89 seconds
Started Oct 14 11:58:04 PM UTC 24
Finished Oct 14 11:58:06 PM UTC 24
Peak memory 206316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533562329 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.2533562329
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/14.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/14.hmac_back_pressure.3764868268
Short name T37
Test name
Test status
Simulation time 231794661 ps
CPU time 5.08 seconds
Started Oct 14 11:57:33 PM UTC 24
Finished Oct 14 11:57:39 PM UTC 24
Peak memory 209564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3764868268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.3764868268
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/14.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/14.hmac_burst_wr.3166073270
Short name T204
Test name
Test status
Simulation time 10496014967 ps
CPU time 45.71 seconds
Started Oct 14 11:57:42 PM UTC 24
Finished Oct 14 11:58:30 PM UTC 24
Peak memory 218524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3166073270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.3166073270
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/14.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/14.hmac_datapath_stress.93794394
Short name T322
Test name
Test status
Simulation time 3333545021 ps
CPU time 631.55 seconds
Started Oct 14 11:57:40 PM UTC 24
Finished Oct 15 12:08:19 AM UTC 24
Peak memory 717432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93794394 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UV
M_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.93794394
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/14.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/14.hmac_error.2973194421
Short name T225
Test name
Test status
Simulation time 10882534339 ps
CPU time 151.32 seconds
Started Oct 14 11:57:45 PM UTC 24
Finished Oct 15 12:00:20 AM UTC 24
Peak memory 209900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2973194421 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.2973194421
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/14.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/14.hmac_long_msg.12097939
Short name T224
Test name
Test status
Simulation time 2467604478 ps
CPU time 149.3 seconds
Started Oct 14 11:57:31 PM UTC 24
Finished Oct 15 12:00:03 AM UTC 24
Peak memory 209784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12097939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac
_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.12097939
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/14.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/14.hmac_smoke.2122751084
Short name T39
Test name
Test status
Simulation time 765389334 ps
CPU time 13.51 seconds
Started Oct 14 11:57:29 PM UTC 24
Finished Oct 14 11:57:45 PM UTC 24
Peak memory 209644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2122751084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.2122751084
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/14.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/14.hmac_stress_all.729449569
Short name T197
Test name
Test status
Simulation time 4305081306 ps
CPU time 16.67 seconds
Started Oct 14 11:58:00 PM UTC 24
Finished Oct 14 11:58:18 PM UTC 24
Peak memory 209764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=729449569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.729449569
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/14.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/14.hmac_wipe_secret.110531832
Short name T42
Test name
Test status
Simulation time 843199281 ps
CPU time 5.76 seconds
Started Oct 14 11:57:57 PM UTC 24
Finished Oct 14 11:58:03 PM UTC 24
Peak memory 209776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=110531832 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.110531832
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/14.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/15.hmac_alert_test.2059196379
Short name T202
Test name
Test status
Simulation time 11916460 ps
CPU time 0.87 seconds
Started Oct 14 11:58:25 PM UTC 24
Finished Oct 14 11:58:27 PM UTC 24
Peak memory 204328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2059196379 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.2059196379
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/15.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/15.hmac_back_pressure.630527313
Short name T212
Test name
Test status
Simulation time 1155500677 ps
CPU time 40.71 seconds
Started Oct 14 11:58:11 PM UTC 24
Finished Oct 14 11:58:53 PM UTC 24
Peak memory 209636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=630527313 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.630527313
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/15.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/15.hmac_burst_wr.77918876
Short name T199
Test name
Test status
Simulation time 197776637 ps
CPU time 3.97 seconds
Started Oct 14 11:58:19 PM UTC 24
Finished Oct 14 11:58:25 PM UTC 24
Peak memory 209696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=77918876 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac
_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.77918876
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/15.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/15.hmac_datapath_stress.1149398513
Short name T357
Test name
Test status
Simulation time 18771037685 ps
CPU time 743.41 seconds
Started Oct 14 11:58:11 PM UTC 24
Finished Oct 15 12:10:42 AM UTC 24
Peak memory 768820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1149398513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.1149398513
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/15.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/15.hmac_error.1658649488
Short name T230
Test name
Test status
Simulation time 5526045008 ps
CPU time 140.52 seconds
Started Oct 14 11:58:20 PM UTC 24
Finished Oct 15 12:00:43 AM UTC 24
Peak memory 209900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658649488 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.1658649488
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/15.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/15.hmac_long_msg.3022441888
Short name T200
Test name
Test status
Simulation time 230291629 ps
CPU time 17.79 seconds
Started Oct 14 11:58:07 PM UTC 24
Finished Oct 14 11:58:26 PM UTC 24
Peak memory 209632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3022441888 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.3022441888
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/15.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/15.hmac_smoke.3745493191
Short name T198
Test name
Test status
Simulation time 1240153360 ps
CPU time 12.81 seconds
Started Oct 14 11:58:06 PM UTC 24
Finished Oct 14 11:58:20 PM UTC 24
Peak memory 209776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3745493191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.3745493191
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/15.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/15.hmac_stress_all.4287810084
Short name T83
Test name
Test status
Simulation time 211570432922 ps
CPU time 2963.36 seconds
Started Oct 14 11:58:24 PM UTC 24
Finished Oct 15 12:48:17 AM UTC 24
Peak memory 840180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287810084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.4287810084
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/15.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/15.hmac_wipe_secret.1095588649
Short name T218
Test name
Test status
Simulation time 22464975474 ps
CPU time 72.67 seconds
Started Oct 14 11:58:21 PM UTC 24
Finished Oct 14 11:59:35 PM UTC 24
Peak memory 209700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095588649 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.1095588649
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/15.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/16.hmac_alert_test.1267652737
Short name T208
Test name
Test status
Simulation time 48490313 ps
CPU time 0.9 seconds
Started Oct 14 11:58:39 PM UTC 24
Finished Oct 14 11:58:41 PM UTC 24
Peak memory 206376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1267652737 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.1267652737
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/16.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/16.hmac_back_pressure.3305430757
Short name T211
Test name
Test status
Simulation time 247231586 ps
CPU time 19.17 seconds
Started Oct 14 11:58:29 PM UTC 24
Finished Oct 14 11:58:50 PM UTC 24
Peak memory 209772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3305430757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.3305430757
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/16.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/16.hmac_burst_wr.3471937460
Short name T207
Test name
Test status
Simulation time 206411013 ps
CPU time 5.87 seconds
Started Oct 14 11:58:31 PM UTC 24
Finished Oct 14 11:58:38 PM UTC 24
Peak memory 209704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3471937460 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.3471937460
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/16.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/16.hmac_datapath_stress.3331266985
Short name T259
Test name
Test status
Simulation time 1525579078 ps
CPU time 281.55 seconds
Started Oct 14 11:58:29 PM UTC 24
Finished Oct 15 12:03:15 AM UTC 24
Peak memory 426656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331266985 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.3331266985
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/16.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/16.hmac_error.3459541782
Short name T242
Test name
Test status
Simulation time 13893092158 ps
CPU time 199.79 seconds
Started Oct 14 11:58:31 PM UTC 24
Finished Oct 15 12:01:54 AM UTC 24
Peak memory 209696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459541782 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.3459541782
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/16.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/16.hmac_long_msg.1917917923
Short name T245
Test name
Test status
Simulation time 87338420198 ps
CPU time 213.99 seconds
Started Oct 14 11:58:27 PM UTC 24
Finished Oct 15 12:02:04 AM UTC 24
Peak memory 209732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1917917923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.1917917923
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/16.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/16.hmac_smoke.1866584431
Short name T203
Test name
Test status
Simulation time 209708915 ps
CPU time 1.99 seconds
Started Oct 14 11:58:27 PM UTC 24
Finished Oct 14 11:58:30 PM UTC 24
Peak memory 208368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1866584431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.1866584431
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/16.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/16.hmac_stress_all.1679556733
Short name T428
Test name
Test status
Simulation time 149125862723 ps
CPU time 1091.88 seconds
Started Oct 14 11:58:33 PM UTC 24
Finished Oct 15 12:16:57 AM UTC 24
Peak memory 686792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1679556733 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.1679556733
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/16.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/16.hmac_wipe_secret.3742645773
Short name T130
Test name
Test status
Simulation time 1028968224 ps
CPU time 70.76 seconds
Started Oct 14 11:58:31 PM UTC 24
Finished Oct 14 11:59:44 PM UTC 24
Peak memory 209964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3742645773 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.3742645773
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/16.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/17.hmac_alert_test.2601277064
Short name T216
Test name
Test status
Simulation time 38480946 ps
CPU time 0.82 seconds
Started Oct 14 11:59:26 PM UTC 24
Finished Oct 14 11:59:28 PM UTC 24
Peak memory 206376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2601277064 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.2601277064
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/17.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/17.hmac_back_pressure.944722965
Short name T214
Test name
Test status
Simulation time 7618970788 ps
CPU time 34.73 seconds
Started Oct 14 11:58:44 PM UTC 24
Finished Oct 14 11:59:20 PM UTC 24
Peak memory 209836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944722965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.944722965
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/17.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/17.hmac_burst_wr.2605863789
Short name T213
Test name
Test status
Simulation time 218818474 ps
CPU time 2.42 seconds
Started Oct 14 11:58:50 PM UTC 24
Finished Oct 14 11:58:54 PM UTC 24
Peak memory 209564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2605863789 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.2605863789
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/17.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/17.hmac_datapath_stress.3011148387
Short name T362
Test name
Test status
Simulation time 7660457583 ps
CPU time 748.86 seconds
Started Oct 14 11:58:44 PM UTC 24
Finished Oct 15 12:11:21 AM UTC 24
Peak memory 697072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3011148387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.3011148387
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/17.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/17.hmac_error.1535390139
Short name T240
Test name
Test status
Simulation time 2008456238 ps
CPU time 159.06 seconds
Started Oct 14 11:58:54 PM UTC 24
Finished Oct 15 12:01:36 AM UTC 24
Peak memory 209704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1535390139 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.1535390139
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/17.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/17.hmac_long_msg.4229247281
Short name T217
Test name
Test status
Simulation time 923478248 ps
CPU time 48.6 seconds
Started Oct 14 11:58:42 PM UTC 24
Finished Oct 14 11:59:32 PM UTC 24
Peak memory 209712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4229247281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.4229247281
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/17.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/17.hmac_smoke.3761607600
Short name T209
Test name
Test status
Simulation time 36771499 ps
CPU time 1.82 seconds
Started Oct 14 11:58:39 PM UTC 24
Finished Oct 14 11:58:41 PM UTC 24
Peak memory 208496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3761607600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.3761607600
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/17.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/17.hmac_stress_all.1482489324
Short name T82
Test name
Test status
Simulation time 98384772628 ps
CPU time 1901.41 seconds
Started Oct 14 11:59:21 PM UTC 24
Finished Oct 15 12:31:24 AM UTC 24
Peak memory 743984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1482489324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.1482489324
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/17.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/17.hmac_wipe_secret.587864492
Short name T99
Test name
Test status
Simulation time 24065082076 ps
CPU time 99.09 seconds
Started Oct 14 11:58:55 PM UTC 24
Finished Oct 15 12:00:36 AM UTC 24
Peak memory 209772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=587864492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.587864492
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/17.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/18.hmac_alert_test.2354754876
Short name T222
Test name
Test status
Simulation time 22210879 ps
CPU time 0.91 seconds
Started Oct 14 11:59:53 PM UTC 24
Finished Oct 14 11:59:55 PM UTC 24
Peak memory 206316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2354754876 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.2354754876
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/18.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/18.hmac_back_pressure.955249849
Short name T26
Test name
Test status
Simulation time 3116657013 ps
CPU time 91.13 seconds
Started Oct 14 11:59:37 PM UTC 24
Finished Oct 15 12:01:10 AM UTC 24
Peak memory 210032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=955249849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.955249849
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/18.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/18.hmac_burst_wr.3972538273
Short name T220
Test name
Test status
Simulation time 65918696 ps
CPU time 3.3 seconds
Started Oct 14 11:59:45 PM UTC 24
Finished Oct 14 11:59:49 PM UTC 24
Peak memory 209632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3972538273 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.3972538273
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/18.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/18.hmac_datapath_stress.4230503286
Short name T401
Test name
Test status
Simulation time 23622285149 ps
CPU time 870.71 seconds
Started Oct 14 11:59:40 PM UTC 24
Finished Oct 15 12:14:20 AM UTC 24
Peak memory 770536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4230503286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.4230503286
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/18.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/18.hmac_error.122216931
Short name T221
Test name
Test status
Simulation time 28417832 ps
CPU time 0.94 seconds
Started Oct 14 11:59:48 PM UTC 24
Finished Oct 14 11:59:50 PM UTC 24
Peak memory 206376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=122216931 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.122216931
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/18.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/18.hmac_long_msg.112466004
Short name T248
Test name
Test status
Simulation time 9032365080 ps
CPU time 176.46 seconds
Started Oct 14 11:59:33 PM UTC 24
Finished Oct 15 12:02:33 AM UTC 24
Peak memory 218540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112466004 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.112466004
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/18.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/18.hmac_smoke.1479298019
Short name T149
Test name
Test status
Simulation time 2105776945 ps
CPU time 22.07 seconds
Started Oct 14 11:59:29 PM UTC 24
Finished Oct 14 11:59:52 PM UTC 24
Peak memory 209648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1479298019 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.1479298019
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/18.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/18.hmac_stress_all.1163117352
Short name T131
Test name
Test status
Simulation time 8317361928 ps
CPU time 79.43 seconds
Started Oct 14 11:59:51 PM UTC 24
Finished Oct 15 12:01:12 AM UTC 24
Peak memory 209772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1163117352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.1163117352
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/18.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/18.hmac_wipe_secret.1009547161
Short name T234
Test name
Test status
Simulation time 4154778093 ps
CPU time 78.42 seconds
Started Oct 14 11:59:50 PM UTC 24
Finished Oct 15 12:01:10 AM UTC 24
Peak memory 209756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1009547161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.1009547161
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/18.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/19.hmac_alert_test.80168651
Short name T229
Test name
Test status
Simulation time 33184257 ps
CPU time 0.82 seconds
Started Oct 15 12:00:35 AM UTC 24
Finished Oct 15 12:00:37 AM UTC 24
Peak memory 206308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80168651 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.80168651
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/19.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/19.hmac_back_pressure.3207163078
Short name T237
Test name
Test status
Simulation time 2186488811 ps
CPU time 71.33 seconds
Started Oct 15 12:00:03 AM UTC 24
Finished Oct 15 12:01:19 AM UTC 24
Peak memory 209760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207163078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.3207163078
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/19.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/19.hmac_burst_wr.774688074
Short name T231
Test name
Test status
Simulation time 2036399712 ps
CPU time 35.84 seconds
Started Oct 15 12:00:10 AM UTC 24
Finished Oct 15 12:00:48 AM UTC 24
Peak memory 218088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=774688074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.774688074
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/19.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/19.hmac_datapath_stress.1879137254
Short name T485
Test name
Test status
Simulation time 8207695714 ps
CPU time 1314.58 seconds
Started Oct 15 12:00:10 AM UTC 24
Finished Oct 15 12:22:18 AM UTC 24
Peak memory 797232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1879137254 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.1879137254
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/19.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/19.hmac_error.300661186
Short name T263
Test name
Test status
Simulation time 40977995326 ps
CPU time 219.4 seconds
Started Oct 15 12:00:18 AM UTC 24
Finished Oct 15 12:04:02 AM UTC 24
Peak memory 209956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300661186 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.300661186
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/19.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/19.hmac_long_msg.38682801
Short name T244
Test name
Test status
Simulation time 1709685051 ps
CPU time 117.61 seconds
Started Oct 14 11:59:59 PM UTC 24
Finished Oct 15 12:01:59 AM UTC 24
Peak memory 209708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38682801 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac
_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.38682801
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/19.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/19.hmac_smoke.3988099648
Short name T223
Test name
Test status
Simulation time 713021460 ps
CPU time 4.42 seconds
Started Oct 14 11:59:56 PM UTC 24
Finished Oct 15 12:00:02 AM UTC 24
Peak memory 209676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3988099648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.3988099648
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/19.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/19.hmac_stress_all.3748035468
Short name T336
Test name
Test status
Simulation time 42944836792 ps
CPU time 522.17 seconds
Started Oct 15 12:00:23 AM UTC 24
Finished Oct 15 12:09:12 AM UTC 24
Peak memory 465404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3748035468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.3748035468
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/19.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/19.hmac_wipe_secret.563912656
Short name T233
Test name
Test status
Simulation time 4323757994 ps
CPU time 38.13 seconds
Started Oct 15 12:00:21 AM UTC 24
Finished Oct 15 12:01:01 AM UTC 24
Peak memory 209708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=563912656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.563912656
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/19.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/2.hmac_alert_test.3062537091
Short name T56
Test name
Test status
Simulation time 20578315 ps
CPU time 0.89 seconds
Started Oct 14 11:53:29 PM UTC 24
Finished Oct 14 11:53:31 PM UTC 24
Peak memory 206376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3062537091 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.3062537091
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/2.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/2.hmac_back_pressure.3383850530
Short name T9
Test name
Test status
Simulation time 54748470 ps
CPU time 2.96 seconds
Started Oct 14 11:53:15 PM UTC 24
Finished Oct 14 11:53:19 PM UTC 24
Peak memory 209288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3383850530 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.3383850530
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/2.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/2.hmac_burst_wr.1541872285
Short name T12
Test name
Test status
Simulation time 734660933 ps
CPU time 53.45 seconds
Started Oct 14 11:53:17 PM UTC 24
Finished Oct 14 11:54:12 PM UTC 24
Peak memory 209640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541872285 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.1541872285
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/2.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/2.hmac_datapath_stress.3683581902
Short name T293
Test name
Test status
Simulation time 73161382713 ps
CPU time 770.83 seconds
Started Oct 14 11:53:15 PM UTC 24
Finished Oct 15 12:06:14 AM UTC 24
Peak memory 702676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3683581902 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.3683581902
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/2.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/2.hmac_long_msg.2524868966
Short name T8
Test name
Test status
Simulation time 407575385 ps
CPU time 21.98 seconds
Started Oct 14 11:53:14 PM UTC 24
Finished Oct 14 11:53:37 PM UTC 24
Peak memory 209640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2524868966 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.2524868966
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/2.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/2.hmac_sec_cm.1144238189
Short name T58
Test name
Test status
Simulation time 36947178 ps
CPU time 1.3 seconds
Started Oct 14 11:53:29 PM UTC 24
Finished Oct 14 11:53:32 PM UTC 24
Peak memory 238012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1144238189 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.1144238189
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/2.hmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/2.hmac_smoke.3154812520
Short name T13
Test name
Test status
Simulation time 824643110 ps
CPU time 15.51 seconds
Started Oct 14 11:53:13 PM UTC 24
Finished Oct 14 11:53:30 PM UTC 24
Peak memory 209704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3154812520 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.3154812520
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/2.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/2.hmac_stress_all.2990290919
Short name T81
Test name
Test status
Simulation time 80909723734 ps
CPU time 2219.12 seconds
Started Oct 14 11:53:28 PM UTC 24
Finished Oct 15 12:30:51 AM UTC 24
Peak memory 764432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2990290919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.2990290919
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/2.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/2.hmac_test_hmac256_vectors.547634807
Short name T55
Test name
Test status
Simulation time 23566246064 ps
CPU time 43 seconds
Started Oct 14 11:53:25 PM UTC 24
Finished Oct 14 11:54:09 PM UTC 24
Peak memory 209772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=547634807 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac256_vectors.547634807
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/2.hmac_test_hmac256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/2.hmac_test_hmac384_vectors.1578956091
Short name T169
Test name
Test status
Simulation time 4437697075 ps
CPU time 59.7 seconds
Started Oct 14 11:53:27 PM UTC 24
Finished Oct 14 11:54:28 PM UTC 24
Peak memory 209712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1578956091 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac384_vectors.1578956091
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/2.hmac_test_hmac384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/2.hmac_test_hmac512_vectors.502570785
Short name T173
Test name
Test status
Simulation time 5785986720 ps
CPU time 80.9 seconds
Started Oct 14 11:53:28 PM UTC 24
Finished Oct 14 11:54:51 PM UTC 24
Peak memory 209980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=502570785 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac512_vectors.502570785
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/2.hmac_test_hmac512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/2.hmac_test_sha256_vectors.297198377
Short name T267
Test name
Test status
Simulation time 11357056427 ps
CPU time 647.49 seconds
Started Oct 14 11:53:20 PM UTC 24
Finished Oct 15 12:04:16 AM UTC 24
Peak memory 209720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297198377 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha256_vectors.297198377
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/2.hmac_test_sha256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/2.hmac_test_sha384_vectors.1192870280
Short name T501
Test name
Test status
Simulation time 216320705967 ps
CPU time 2297.71 seconds
Started Oct 14 11:53:20 PM UTC 24
Finished Oct 15 12:32:04 AM UTC 24
Peak memory 229932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1192870280 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha384_vectors.1192870280
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/2.hmac_test_sha384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/2.hmac_test_sha512_vectors.1352908686
Short name T506
Test name
Test status
Simulation time 269248961831 ps
CPU time 2425.96 seconds
Started Oct 14 11:53:23 PM UTC 24
Finished Oct 15 12:34:17 AM UTC 24
Peak memory 229940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1352908686 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha512_vectors.1352908686
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/2.hmac_test_sha512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/20.hmac_alert_test.2408521343
Short name T236
Test name
Test status
Simulation time 40573009 ps
CPU time 0.82 seconds
Started Oct 15 12:01:12 AM UTC 24
Finished Oct 15 12:01:14 AM UTC 24
Peak memory 206316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408521343 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.2408521343
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/20.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/20.hmac_back_pressure.2231203072
Short name T235
Test name
Test status
Simulation time 1758313757 ps
CPU time 31.3 seconds
Started Oct 15 12:00:38 AM UTC 24
Finished Oct 15 12:01:11 AM UTC 24
Peak memory 209900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2231203072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.2231203072
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/20.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/20.hmac_burst_wr.3251148614
Short name T239
Test name
Test status
Simulation time 3384098870 ps
CPU time 41.62 seconds
Started Oct 15 12:00:48 AM UTC 24
Finished Oct 15 12:01:32 AM UTC 24
Peak memory 209684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251148614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.3251148614
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/20.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/20.hmac_datapath_stress.2383897131
Short name T271
Test name
Test status
Simulation time 1250848007 ps
CPU time 218.11 seconds
Started Oct 15 12:00:44 AM UTC 24
Finished Oct 15 12:04:26 AM UTC 24
Peak memory 709096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383897131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.2383897131
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/20.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/20.hmac_error.1799093646
Short name T251
Test name
Test status
Simulation time 25043568175 ps
CPU time 104.92 seconds
Started Oct 15 12:00:56 AM UTC 24
Finished Oct 15 12:02:43 AM UTC 24
Peak memory 209828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1799093646 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.1799093646
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/20.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/20.hmac_long_msg.4130890028
Short name T261
Test name
Test status
Simulation time 9757317152 ps
CPU time 188.08 seconds
Started Oct 15 12:00:38 AM UTC 24
Finished Oct 15 12:03:50 AM UTC 24
Peak memory 218352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4130890028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.4130890028
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/20.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/20.hmac_smoke.2965281949
Short name T232
Test name
Test status
Simulation time 1001276793 ps
CPU time 16.49 seconds
Started Oct 15 12:00:37 AM UTC 24
Finished Oct 15 12:00:55 AM UTC 24
Peak memory 209624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2965281949 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.2965281949
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/20.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/20.hmac_stress_all.2245961196
Short name T77
Test name
Test status
Simulation time 157628536892 ps
CPU time 435.55 seconds
Started Oct 15 12:01:02 AM UTC 24
Finished Oct 15 12:08:23 AM UTC 24
Peak memory 500352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2245961196 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.2245961196
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/20.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/20.hmac_wipe_secret.3063726784
Short name T132
Test name
Test status
Simulation time 5616927750 ps
CPU time 56.68 seconds
Started Oct 15 12:01:01 AM UTC 24
Finished Oct 15 12:01:59 AM UTC 24
Peak memory 209760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3063726784 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.3063726784
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/20.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/21.hmac_alert_test.2042238121
Short name T243
Test name
Test status
Simulation time 15134213 ps
CPU time 0.82 seconds
Started Oct 15 12:01:48 AM UTC 24
Finished Oct 15 12:01:51 AM UTC 24
Peak memory 206316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2042238121 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.2042238121
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/21.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/21.hmac_back_pressure.1091710493
Short name T247
Test name
Test status
Simulation time 971101035 ps
CPU time 69.84 seconds
Started Oct 15 12:01:14 AM UTC 24
Finished Oct 15 12:02:26 AM UTC 24
Peak memory 209772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1091710493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.1091710493
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/21.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/21.hmac_datapath_stress.2120854022
Short name T320
Test name
Test status
Simulation time 2911187779 ps
CPU time 415.28 seconds
Started Oct 15 12:01:15 AM UTC 24
Finished Oct 15 12:08:16 AM UTC 24
Peak memory 660004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2120854022 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.2120854022
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/21.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/21.hmac_error.3241338047
Short name T285
Test name
Test status
Simulation time 6668890361 ps
CPU time 232.52 seconds
Started Oct 15 12:01:32 AM UTC 24
Finished Oct 15 12:05:29 AM UTC 24
Peak memory 209952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3241338047 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.3241338047
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/21.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/21.hmac_long_msg.2024633153
Short name T254
Test name
Test status
Simulation time 18218589510 ps
CPU time 98.77 seconds
Started Oct 15 12:01:13 AM UTC 24
Finished Oct 15 12:02:53 AM UTC 24
Peak memory 210028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2024633153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.2024633153
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/21.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/21.hmac_smoke.3043329939
Short name T238
Test name
Test status
Simulation time 299996108 ps
CPU time 17.57 seconds
Started Oct 15 12:01:13 AM UTC 24
Finished Oct 15 12:01:31 AM UTC 24
Peak memory 209716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3043329939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.3043329939
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/21.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/21.hmac_stress_all.3327038728
Short name T84
Test name
Test status
Simulation time 147649691929 ps
CPU time 3288.75 seconds
Started Oct 15 12:01:38 AM UTC 24
Finished Oct 15 12:57:00 AM UTC 24
Peak memory 756196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3327038728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.3327038728
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/21.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/21.hmac_wipe_secret.1511651328
Short name T241
Test name
Test status
Simulation time 210443093 ps
CPU time 14.29 seconds
Started Oct 15 12:01:32 AM UTC 24
Finished Oct 15 12:01:48 AM UTC 24
Peak memory 209636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1511651328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.1511651328
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/21.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/22.hmac_alert_test.1933845288
Short name T249
Test name
Test status
Simulation time 15209386 ps
CPU time 0.87 seconds
Started Oct 15 12:02:34 AM UTC 24
Finished Oct 15 12:02:36 AM UTC 24
Peak memory 206316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1933845288 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.1933845288
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/22.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/22.hmac_back_pressure.2058469210
Short name T256
Test name
Test status
Simulation time 1370375202 ps
CPU time 59.57 seconds
Started Oct 15 12:01:56 AM UTC 24
Finished Oct 15 12:02:57 AM UTC 24
Peak memory 209748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2058469210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.2058469210
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/22.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/22.hmac_burst_wr.4205722701
Short name T250
Test name
Test status
Simulation time 1450152311 ps
CPU time 35.29 seconds
Started Oct 15 12:02:01 AM UTC 24
Finished Oct 15 12:02:37 AM UTC 24
Peak memory 209704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4205722701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.4205722701
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/22.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/22.hmac_datapath_stress.2269657346
Short name T432
Test name
Test status
Simulation time 5700325395 ps
CPU time 902.95 seconds
Started Oct 15 12:02:01 AM UTC 24
Finished Oct 15 12:17:13 AM UTC 24
Peak memory 735788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2269657346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.2269657346
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/22.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/22.hmac_error.460024781
Short name T282
Test name
Test status
Simulation time 12458011790 ps
CPU time 188.96 seconds
Started Oct 15 12:02:06 AM UTC 24
Finished Oct 15 12:05:18 AM UTC 24
Peak memory 209700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=460024781 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.460024781
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/22.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/22.hmac_long_msg.1265698421
Short name T277
Test name
Test status
Simulation time 5397691245 ps
CPU time 167.83 seconds
Started Oct 15 12:01:52 AM UTC 24
Finished Oct 15 12:04:42 AM UTC 24
Peak memory 209680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1265698421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.1265698421
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/22.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/22.hmac_smoke.846120419
Short name T246
Test name
Test status
Simulation time 1225059865 ps
CPU time 22.28 seconds
Started Oct 15 12:01:52 AM UTC 24
Finished Oct 15 12:02:15 AM UTC 24
Peak memory 209724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=846120419 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.846120419
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/22.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/22.hmac_wipe_secret.3946717020
Short name T275
Test name
Test status
Simulation time 7790699241 ps
CPU time 141.48 seconds
Started Oct 15 12:02:16 AM UTC 24
Finished Oct 15 12:04:40 AM UTC 24
Peak memory 209760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3946717020 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.3946717020
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/22.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/23.hmac_alert_test.2094425350
Short name T257
Test name
Test status
Simulation time 43530893 ps
CPU time 0.92 seconds
Started Oct 15 12:02:58 AM UTC 24
Finished Oct 15 12:03:00 AM UTC 24
Peak memory 206376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2094425350 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.2094425350
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/23.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/23.hmac_back_pressure.323169155
Short name T269
Test name
Test status
Simulation time 6623345760 ps
CPU time 95.54 seconds
Started Oct 15 12:02:43 AM UTC 24
Finished Oct 15 12:04:20 AM UTC 24
Peak memory 209740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=323169155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.323169155
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/23.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/23.hmac_burst_wr.2080799884
Short name T255
Test name
Test status
Simulation time 279408682 ps
CPU time 5.67 seconds
Started Oct 15 12:02:47 AM UTC 24
Finished Oct 15 12:02:54 AM UTC 24
Peak memory 209832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2080799884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.2080799884
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/23.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/23.hmac_datapath_stress.1374389788
Short name T484
Test name
Test status
Simulation time 12971422336 ps
CPU time 1137.5 seconds
Started Oct 15 12:02:44 AM UTC 24
Finished Oct 15 12:21:53 AM UTC 24
Peak memory 737828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1374389788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.1374389788
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/23.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/23.hmac_error.1002227165
Short name T265
Test name
Test status
Simulation time 3570932974 ps
CPU time 74.01 seconds
Started Oct 15 12:02:48 AM UTC 24
Finished Oct 15 12:04:04 AM UTC 24
Peak memory 209756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1002227165 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.1002227165
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/23.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/23.hmac_long_msg.3804257468
Short name T264
Test name
Test status
Simulation time 2452750900 ps
CPU time 81.19 seconds
Started Oct 15 12:02:39 AM UTC 24
Finished Oct 15 12:04:02 AM UTC 24
Peak memory 209784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3804257468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.3804257468
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/23.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/23.hmac_smoke.11461029
Short name T253
Test name
Test status
Simulation time 1859057964 ps
CPU time 8.53 seconds
Started Oct 15 12:02:38 AM UTC 24
Finished Oct 15 12:02:47 AM UTC 24
Peak memory 209644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11461029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 23.hmac_smoke.11461029
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/23.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/23.hmac_stress_all.311592908
Short name T502
Test name
Test status
Simulation time 448131001444 ps
CPU time 1760.6 seconds
Started Oct 15 12:02:55 AM UTC 24
Finished Oct 15 12:32:35 AM UTC 24
Peak memory 743944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=311592908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.311592908
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/23.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/23.hmac_wipe_secret.3541895133
Short name T262
Test name
Test status
Simulation time 2524944283 ps
CPU time 62.43 seconds
Started Oct 15 12:02:55 AM UTC 24
Finished Oct 15 12:03:59 AM UTC 24
Peak memory 209784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3541895133 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.3541895133
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/23.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/24.hmac_alert_test.3779525996
Short name T266
Test name
Test status
Simulation time 13827571 ps
CPU time 0.9 seconds
Started Oct 15 12:04:04 AM UTC 24
Finished Oct 15 12:04:06 AM UTC 24
Peak memory 206316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3779525996 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.3779525996
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/24.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/24.hmac_back_pressure.1236533667
Short name T260
Test name
Test status
Simulation time 793073295 ps
CPU time 28.39 seconds
Started Oct 15 12:03:16 AM UTC 24
Finished Oct 15 12:03:46 AM UTC 24
Peak memory 209636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1236533667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.1236533667
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/24.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/24.hmac_burst_wr.2391973725
Short name T270
Test name
Test status
Simulation time 11654638725 ps
CPU time 31.49 seconds
Started Oct 15 12:03:47 AM UTC 24
Finished Oct 15 12:04:20 AM UTC 24
Peak memory 220456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2391973725 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.2391973725
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/24.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/24.hmac_datapath_stress.674360096
Short name T388
Test name
Test status
Simulation time 18530658161 ps
CPU time 599.69 seconds
Started Oct 15 12:03:23 AM UTC 24
Finished Oct 15 12:13:29 AM UTC 24
Peak memory 715232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=674360096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.674360096
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/24.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/24.hmac_error.81367710
Short name T333
Test name
Test status
Simulation time 37064164382 ps
CPU time 304.26 seconds
Started Oct 15 12:03:52 AM UTC 24
Finished Oct 15 12:09:00 AM UTC 24
Peak memory 209964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=81367710 -assert nopostproc +UVM_TESTNAME=hmac
_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.81367710
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/24.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/24.hmac_long_msg.4216246486
Short name T295
Test name
Test status
Simulation time 50170897836 ps
CPU time 183.97 seconds
Started Oct 15 12:03:10 AM UTC 24
Finished Oct 15 12:06:17 AM UTC 24
Peak memory 209700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4216246486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.4216246486
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/24.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/24.hmac_smoke.1915791925
Short name T258
Test name
Test status
Simulation time 1557014187 ps
CPU time 6.18 seconds
Started Oct 15 12:03:01 AM UTC 24
Finished Oct 15 12:03:09 AM UTC 24
Peak memory 209632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1915791925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.1915791925
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/24.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/24.hmac_stress_all.2550532013
Short name T35
Test name
Test status
Simulation time 32532921279 ps
CPU time 2559.26 seconds
Started Oct 15 12:04:04 AM UTC 24
Finished Oct 15 12:47:10 AM UTC 24
Peak memory 799276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2550532013 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.2550532013
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/24.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/24.hmac_wipe_secret.3478472131
Short name T296
Test name
Test status
Simulation time 7596285066 ps
CPU time 143.54 seconds
Started Oct 15 12:04:00 AM UTC 24
Finished Oct 15 12:06:26 AM UTC 24
Peak memory 209760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3478472131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.3478472131
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/24.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/25.hmac_alert_test.4215683585
Short name T273
Test name
Test status
Simulation time 42664921 ps
CPU time 0.85 seconds
Started Oct 15 12:04:29 AM UTC 24
Finished Oct 15 12:04:31 AM UTC 24
Peak memory 206376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4215683585 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.4215683585
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/25.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/25.hmac_back_pressure.1781739217
Short name T279
Test name
Test status
Simulation time 1655821944 ps
CPU time 27.85 seconds
Started Oct 15 12:04:20 AM UTC 24
Finished Oct 15 12:04:49 AM UTC 24
Peak memory 209636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781739217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.1781739217
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/25.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/25.hmac_burst_wr.3066262305
Short name T281
Test name
Test status
Simulation time 3641128031 ps
CPU time 51.1 seconds
Started Oct 15 12:04:25 AM UTC 24
Finished Oct 15 12:05:18 AM UTC 24
Peak memory 218308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066262305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.3066262305
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/25.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/25.hmac_datapath_stress.2947359637
Short name T425
Test name
Test status
Simulation time 3442140475 ps
CPU time 712.52 seconds
Started Oct 15 12:04:20 AM UTC 24
Finished Oct 15 12:16:21 AM UTC 24
Peak memory 670188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2947359637 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.2947359637
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/25.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/25.hmac_error.2307640674
Short name T274
Test name
Test status
Simulation time 324862223 ps
CPU time 6 seconds
Started Oct 15 12:04:25 AM UTC 24
Finished Oct 15 12:04:32 AM UTC 24
Peak memory 209764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307640674 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.2307640674
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/25.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/25.hmac_long_msg.3206493746
Short name T292
Test name
Test status
Simulation time 5623634204 ps
CPU time 121.07 seconds
Started Oct 15 12:04:06 AM UTC 24
Finished Oct 15 12:06:10 AM UTC 24
Peak memory 209904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3206493746 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.3206493746
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/25.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/25.hmac_smoke.430107014
Short name T268
Test name
Test status
Simulation time 449288709 ps
CPU time 10.94 seconds
Started Oct 15 12:04:05 AM UTC 24
Finished Oct 15 12:04:17 AM UTC 24
Peak memory 209848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=430107014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.430107014
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/25.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/25.hmac_stress_all.2461192664
Short name T523
Test name
Test status
Simulation time 79636992453 ps
CPU time 2819.04 seconds
Started Oct 15 12:04:29 AM UTC 24
Finished Oct 15 12:51:58 AM UTC 24
Peak memory 789244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2461192664 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.2461192664
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/25.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/25.hmac_wipe_secret.4020185362
Short name T291
Test name
Test status
Simulation time 24103858323 ps
CPU time 101.33 seconds
Started Oct 15 12:04:25 AM UTC 24
Finished Oct 15 12:06:09 AM UTC 24
Peak memory 209700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020185362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.4020185362
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/25.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/26.hmac_alert_test.962251406
Short name T283
Test name
Test status
Simulation time 38022280 ps
CPU time 0.84 seconds
Started Oct 15 12:05:19 AM UTC 24
Finished Oct 15 12:05:21 AM UTC 24
Peak memory 206376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=962251406 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.962251406
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/26.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/26.hmac_back_pressure.2639712255
Short name T288
Test name
Test status
Simulation time 1022130601 ps
CPU time 70.15 seconds
Started Oct 15 12:04:42 AM UTC 24
Finished Oct 15 12:05:54 AM UTC 24
Peak memory 209640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639712255 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.2639712255
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/26.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/26.hmac_burst_wr.2848482698
Short name T280
Test name
Test status
Simulation time 1541030762 ps
CPU time 23.03 seconds
Started Oct 15 12:04:47 AM UTC 24
Finished Oct 15 12:05:11 AM UTC 24
Peak memory 209672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2848482698 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.2848482698
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/26.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/26.hmac_datapath_stress.1771228163
Short name T415
Test name
Test status
Simulation time 3017073892 ps
CPU time 660.25 seconds
Started Oct 15 12:04:42 AM UTC 24
Finished Oct 15 12:15:50 AM UTC 24
Peak memory 694832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1771228163 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.1771228163
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/26.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/26.hmac_error.2788985984
Short name T314
Test name
Test status
Simulation time 29552068576 ps
CPU time 168.85 seconds
Started Oct 15 12:04:47 AM UTC 24
Finished Oct 15 12:07:39 AM UTC 24
Peak memory 209700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2788985984 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.2788985984
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/26.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/26.hmac_long_msg.3986488942
Short name T315
Test name
Test status
Simulation time 9625210499 ps
CPU time 186.78 seconds
Started Oct 15 12:04:34 AM UTC 24
Finished Oct 15 12:07:44 AM UTC 24
Peak memory 209764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986488942 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.3986488942
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/26.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/26.hmac_smoke.3810932571
Short name T276
Test name
Test status
Simulation time 295482518 ps
CPU time 7.18 seconds
Started Oct 15 12:04:33 AM UTC 24
Finished Oct 15 12:04:41 AM UTC 24
Peak memory 209648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3810932571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.3810932571
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/26.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/26.hmac_stress_all.1588143543
Short name T416
Test name
Test status
Simulation time 31491933907 ps
CPU time 633.57 seconds
Started Oct 15 12:05:13 AM UTC 24
Finished Oct 15 12:15:54 AM UTC 24
Peak memory 226292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1588143543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.1588143543
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/26.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/26.hmac_wipe_secret.1390811522
Short name T298
Test name
Test status
Simulation time 40262186319 ps
CPU time 95.71 seconds
Started Oct 15 12:04:50 AM UTC 24
Finished Oct 15 12:06:28 AM UTC 24
Peak memory 209704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390811522 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.1390811522
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/26.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/27.hmac_alert_test.2169313915
Short name T290
Test name
Test status
Simulation time 39044659 ps
CPU time 0.83 seconds
Started Oct 15 12:05:59 AM UTC 24
Finished Oct 15 12:06:01 AM UTC 24
Peak memory 206316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2169313915 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.2169313915
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/27.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/27.hmac_back_pressure.1216898238
Short name T289
Test name
Test status
Simulation time 1359398413 ps
CPU time 31.91 seconds
Started Oct 15 12:05:25 AM UTC 24
Finished Oct 15 12:05:58 AM UTC 24
Peak memory 209692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1216898238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.1216898238
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/27.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/27.hmac_burst_wr.1011157637
Short name T160
Test name
Test status
Simulation time 282977768 ps
CPU time 17.68 seconds
Started Oct 15 12:05:36 AM UTC 24
Finished Oct 15 12:05:55 AM UTC 24
Peak memory 209772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1011157637 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.1011157637
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/27.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/27.hmac_datapath_stress.978076950
Short name T302
Test name
Test status
Simulation time 354316642 ps
CPU time 69.78 seconds
Started Oct 15 12:05:31 AM UTC 24
Finished Oct 15 12:06:42 AM UTC 24
Peak memory 407004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=978076950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.978076950
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/27.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/27.hmac_error.1631068135
Short name T321
Test name
Test status
Simulation time 42072696321 ps
CPU time 155.06 seconds
Started Oct 15 12:05:41 AM UTC 24
Finished Oct 15 12:08:19 AM UTC 24
Peak memory 209752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1631068135 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.1631068135
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/27.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/27.hmac_long_msg.1061550906
Short name T286
Test name
Test status
Simulation time 694850527 ps
CPU time 12.43 seconds
Started Oct 15 12:05:22 AM UTC 24
Finished Oct 15 12:05:35 AM UTC 24
Peak memory 209696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061550906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.1061550906
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/27.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/27.hmac_smoke.459168973
Short name T284
Test name
Test status
Simulation time 76474834 ps
CPU time 2.34 seconds
Started Oct 15 12:05:21 AM UTC 24
Finished Oct 15 12:05:24 AM UTC 24
Peak memory 209512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459168973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.459168973
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/27.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/27.hmac_stress_all.3687092614
Short name T327
Test name
Test status
Simulation time 32515430367 ps
CPU time 159.43 seconds
Started Oct 15 12:05:56 AM UTC 24
Finished Oct 15 12:08:38 AM UTC 24
Peak memory 209968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3687092614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.3687092614
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/27.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/27.hmac_wipe_secret.4212142305
Short name T299
Test name
Test status
Simulation time 1622630190 ps
CPU time 32.63 seconds
Started Oct 15 12:05:56 AM UTC 24
Finished Oct 15 12:06:30 AM UTC 24
Peak memory 209644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4212142305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.4212142305
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/27.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/28.hmac_alert_test.3265378924
Short name T300
Test name
Test status
Simulation time 30705363 ps
CPU time 0.77 seconds
Started Oct 15 12:06:29 AM UTC 24
Finished Oct 15 12:06:31 AM UTC 24
Peak memory 206316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3265378924 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.3265378924
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/28.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/28.hmac_back_pressure.2046283403
Short name T297
Test name
Test status
Simulation time 226411531 ps
CPU time 14.53 seconds
Started Oct 15 12:06:11 AM UTC 24
Finished Oct 15 12:06:27 AM UTC 24
Peak memory 209700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2046283403 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.2046283403
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/28.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/28.hmac_burst_wr.2597709153
Short name T304
Test name
Test status
Simulation time 2061182721 ps
CPU time 35.65 seconds
Started Oct 15 12:06:19 AM UTC 24
Finished Oct 15 12:06:56 AM UTC 24
Peak memory 209684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2597709153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.2597709153
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/28.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/28.hmac_datapath_stress.3410626479
Short name T370
Test name
Test status
Simulation time 8216054558 ps
CPU time 334.7 seconds
Started Oct 15 12:06:16 AM UTC 24
Finished Oct 15 12:11:55 AM UTC 24
Peak memory 649784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3410626479 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.3410626479
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/28.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/28.hmac_error.682615869
Short name T301
Test name
Test status
Simulation time 763185928 ps
CPU time 13.22 seconds
Started Oct 15 12:06:19 AM UTC 24
Finished Oct 15 12:06:33 AM UTC 24
Peak memory 209840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=682615869 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.682615869
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/28.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/28.hmac_long_msg.4002746436
Short name T323
Test name
Test status
Simulation time 14733343628 ps
CPU time 136.1 seconds
Started Oct 15 12:06:10 AM UTC 24
Finished Oct 15 12:08:28 AM UTC 24
Peak memory 209968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4002746436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.4002746436
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/28.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/28.hmac_smoke.1744224167
Short name T294
Test name
Test status
Simulation time 387356972 ps
CPU time 12.65 seconds
Started Oct 15 12:06:02 AM UTC 24
Finished Oct 15 12:06:16 AM UTC 24
Peak memory 209964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744224167 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.1744224167
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/28.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/28.hmac_stress_all.3937401720
Short name T307
Test name
Test status
Simulation time 593442710 ps
CPU time 42.58 seconds
Started Oct 15 12:06:29 AM UTC 24
Finished Oct 15 12:07:14 AM UTC 24
Peak memory 209872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937401720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.3937401720
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/28.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/28.hmac_wipe_secret.796170387
Short name T305
Test name
Test status
Simulation time 1014123904 ps
CPU time 26.72 seconds
Started Oct 15 12:06:28 AM UTC 24
Finished Oct 15 12:06:56 AM UTC 24
Peak memory 209904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=796170387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.796170387
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/28.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/29.hmac_alert_test.258800346
Short name T309
Test name
Test status
Simulation time 14146085 ps
CPU time 0.79 seconds
Started Oct 15 12:07:15 AM UTC 24
Finished Oct 15 12:07:17 AM UTC 24
Peak memory 206316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258800346 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.258800346
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/29.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/29.hmac_back_pressure.3128678525
Short name T311
Test name
Test status
Simulation time 3268950875 ps
CPU time 51.57 seconds
Started Oct 15 12:06:34 AM UTC 24
Finished Oct 15 12:07:27 AM UTC 24
Peak memory 209740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3128678525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.3128678525
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/29.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/29.hmac_burst_wr.1573030982
Short name T312
Test name
Test status
Simulation time 13826773982 ps
CPU time 45.28 seconds
Started Oct 15 12:06:48 AM UTC 24
Finished Oct 15 12:07:35 AM UTC 24
Peak memory 209764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573030982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.1573030982
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/29.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/29.hmac_datapath_stress.2193079864
Short name T443
Test name
Test status
Simulation time 13739256153 ps
CPU time 679.78 seconds
Started Oct 15 12:06:43 AM UTC 24
Finished Oct 15 12:18:11 AM UTC 24
Peak memory 700964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2193079864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.2193079864
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/29.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/29.hmac_error.1831319473
Short name T329
Test name
Test status
Simulation time 3131496920 ps
CPU time 111.1 seconds
Started Oct 15 12:06:57 AM UTC 24
Finished Oct 15 12:08:50 AM UTC 24
Peak memory 209824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1831319473 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.1831319473
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/29.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/29.hmac_long_msg.3915482227
Short name T308
Test name
Test status
Simulation time 3792832905 ps
CPU time 42.62 seconds
Started Oct 15 12:06:32 AM UTC 24
Finished Oct 15 12:07:16 AM UTC 24
Peak memory 209736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3915482227 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.3915482227
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/29.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/29.hmac_smoke.346462205
Short name T303
Test name
Test status
Simulation time 653008667 ps
CPU time 14.76 seconds
Started Oct 15 12:06:31 AM UTC 24
Finished Oct 15 12:06:47 AM UTC 24
Peak memory 209880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=346462205 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.346462205
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/29.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/29.hmac_wipe_secret.510700715
Short name T313
Test name
Test status
Simulation time 2551210905 ps
CPU time 38.78 seconds
Started Oct 15 12:06:57 AM UTC 24
Finished Oct 15 12:07:37 AM UTC 24
Peak memory 209768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=510700715 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.510700715
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/29.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/3.hmac_alert_test.1255950616
Short name T57
Test name
Test status
Simulation time 52183821 ps
CPU time 0.87 seconds
Started Oct 14 11:53:48 PM UTC 24
Finished Oct 14 11:53:49 PM UTC 24
Peak memory 206376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255950616 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.1255950616
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/3.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/3.hmac_back_pressure.1008552397
Short name T15
Test name
Test status
Simulation time 504870492 ps
CPU time 17.72 seconds
Started Oct 14 11:53:32 PM UTC 24
Finished Oct 14 11:53:51 PM UTC 24
Peak memory 209528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1008552397 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.1008552397
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/3.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/3.hmac_datapath_stress.871268871
Short name T360
Test name
Test status
Simulation time 4873516911 ps
CPU time 1033.93 seconds
Started Oct 14 11:53:33 PM UTC 24
Finished Oct 15 12:10:59 AM UTC 24
Peak memory 727596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=871268871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.871268871
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/3.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/3.hmac_error.2141700559
Short name T51
Test name
Test status
Simulation time 4061398527 ps
CPU time 67.96 seconds
Started Oct 14 11:53:33 PM UTC 24
Finished Oct 14 11:54:43 PM UTC 24
Peak memory 209752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2141700559 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.2141700559
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/3.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/3.hmac_long_msg.1929312116
Short name T74
Test name
Test status
Simulation time 26184796899 ps
CPU time 169.12 seconds
Started Oct 14 11:53:32 PM UTC 24
Finished Oct 14 11:56:24 PM UTC 24
Peak memory 209824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929312116 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.1929312116
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/3.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/3.hmac_sec_cm.3893007918
Short name T59
Test name
Test status
Simulation time 318341109 ps
CPU time 1.46 seconds
Started Oct 14 11:53:46 PM UTC 24
Finished Oct 14 11:53:49 PM UTC 24
Peak memory 238012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893007918 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.3893007918
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/3.hmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/3.hmac_smoke.508532514
Short name T11
Test name
Test status
Simulation time 1236486074 ps
CPU time 13.79 seconds
Started Oct 14 11:53:31 PM UTC 24
Finished Oct 14 11:53:45 PM UTC 24
Peak memory 209688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=508532514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.508532514
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/3.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/3.hmac_stress_all.3074887572
Short name T526
Test name
Test status
Simulation time 216509552746 ps
CPU time 3955.92 seconds
Started Oct 14 11:53:45 PM UTC 24
Finished Oct 15 01:00:20 AM UTC 24
Peak memory 823856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3074887572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.3074887572
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/3.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/3.hmac_test_hmac256_vectors.3356447348
Short name T171
Test name
Test status
Simulation time 3102277710 ps
CPU time 49.13 seconds
Started Oct 14 11:53:39 PM UTC 24
Finished Oct 14 11:54:29 PM UTC 24
Peak memory 209968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3356447348 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac256_vectors.3356447348
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/3.hmac_test_hmac256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/3.hmac_test_hmac384_vectors.638308894
Short name T124
Test name
Test status
Simulation time 19240117611 ps
CPU time 129.68 seconds
Started Oct 14 11:53:44 PM UTC 24
Finished Oct 14 11:55:57 PM UTC 24
Peak memory 209768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638308894 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac384_vectors.638308894
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/3.hmac_test_hmac384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/3.hmac_test_hmac512_vectors.4161960761
Short name T180
Test name
Test status
Simulation time 5559562190 ps
CPU time 91.55 seconds
Started Oct 14 11:53:44 PM UTC 24
Finished Oct 14 11:55:18 PM UTC 24
Peak memory 209744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4161960761 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac512_vectors.4161960761
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/3.hmac_test_hmac512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/3.hmac_test_sha256_vectors.247192574
Short name T278
Test name
Test status
Simulation time 92331948356 ps
CPU time 659.22 seconds
Started Oct 14 11:53:35 PM UTC 24
Finished Oct 15 12:04:43 AM UTC 24
Peak memory 209704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247192574 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha256_vectors.247192574
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/3.hmac_test_sha256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/3.hmac_test_sha384_vectors.3629847671
Short name T518
Test name
Test status
Simulation time 257309456129 ps
CPU time 2805.88 seconds
Started Oct 14 11:53:38 PM UTC 24
Finished Oct 15 12:40:54 AM UTC 24
Peak memory 230004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3629847671 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha384_vectors.3629847671
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/3.hmac_test_sha384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/3.hmac_test_sha512_vectors.768718107
Short name T500
Test name
Test status
Simulation time 40000005856 ps
CPU time 2257.18 seconds
Started Oct 14 11:53:39 PM UTC 24
Finished Oct 15 12:31:42 AM UTC 24
Peak memory 229756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=768718107 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha512_vectors.768718107
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/3.hmac_test_sha512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/3.hmac_wipe_secret.1501786645
Short name T14
Test name
Test status
Simulation time 502051438 ps
CPU time 6.9 seconds
Started Oct 14 11:53:35 PM UTC 24
Finished Oct 14 11:53:43 PM UTC 24
Peak memory 209692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1501786645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.1501786645
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/3.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/30.hmac_alert_test.3286743143
Short name T316
Test name
Test status
Simulation time 12926379 ps
CPU time 0.8 seconds
Started Oct 15 12:07:47 AM UTC 24
Finished Oct 15 12:07:49 AM UTC 24
Peak memory 206316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286743143 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.3286743143
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/30.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/30.hmac_back_pressure.1518636404
Short name T319
Test name
Test status
Simulation time 2286528901 ps
CPU time 42.74 seconds
Started Oct 15 12:07:25 AM UTC 24
Finished Oct 15 12:08:10 AM UTC 24
Peak memory 209832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1518636404 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.1518636404
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/30.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/30.hmac_burst_wr.3883663878
Short name T158
Test name
Test status
Simulation time 585668037 ps
CPU time 9.35 seconds
Started Oct 15 12:07:36 AM UTC 24
Finished Oct 15 12:07:47 AM UTC 24
Peak memory 209900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3883663878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.3883663878
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/30.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/30.hmac_datapath_stress.1005781728
Short name T339
Test name
Test status
Simulation time 698852900 ps
CPU time 114.51 seconds
Started Oct 15 12:07:28 AM UTC 24
Finished Oct 15 12:09:25 AM UTC 24
Peak memory 665740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005781728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.1005781728
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/30.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/30.hmac_error.170229681
Short name T340
Test name
Test status
Simulation time 1695286960 ps
CPU time 107.76 seconds
Started Oct 15 12:07:37 AM UTC 24
Finished Oct 15 12:09:27 AM UTC 24
Peak memory 209708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=170229681 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.170229681
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/30.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/30.hmac_long_msg.968961241
Short name T331
Test name
Test status
Simulation time 4082668146 ps
CPU time 97.68 seconds
Started Oct 15 12:07:17 AM UTC 24
Finished Oct 15 12:08:57 AM UTC 24
Peak memory 209764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=968961241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.968961241
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/30.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/30.hmac_smoke.1058749353
Short name T310
Test name
Test status
Simulation time 113255030 ps
CPU time 6.33 seconds
Started Oct 15 12:07:17 AM UTC 24
Finished Oct 15 12:07:25 AM UTC 24
Peak memory 209700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1058749353 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.1058749353
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/30.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/30.hmac_stress_all.2253065889
Short name T515
Test name
Test status
Simulation time 19167736014 ps
CPU time 1744.74 seconds
Started Oct 15 12:07:45 AM UTC 24
Finished Oct 15 12:37:09 AM UTC 24
Peak memory 700992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2253065889 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.2253065889
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/30.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/30.hmac_wipe_secret.3069844158
Short name T330
Test name
Test status
Simulation time 8117212090 ps
CPU time 69.38 seconds
Started Oct 15 12:07:40 AM UTC 24
Finished Oct 15 12:08:51 AM UTC 24
Peak memory 209756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3069844158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.3069844158
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/30.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/31.hmac_alert_test.92953163
Short name T326
Test name
Test status
Simulation time 16675421 ps
CPU time 0.94 seconds
Started Oct 15 12:08:31 AM UTC 24
Finished Oct 15 12:08:33 AM UTC 24
Peak memory 206308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92953163 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.92953163
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/31.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/31.hmac_back_pressure.3059481382
Short name T338
Test name
Test status
Simulation time 13035555097 ps
CPU time 74.88 seconds
Started Oct 15 12:08:07 AM UTC 24
Finished Oct 15 12:09:24 AM UTC 24
Peak memory 220376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3059481382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.3059481382
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/31.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/31.hmac_burst_wr.358976183
Short name T341
Test name
Test status
Simulation time 13472972515 ps
CPU time 68.33 seconds
Started Oct 15 12:08:17 AM UTC 24
Finished Oct 15 12:09:27 AM UTC 24
Peak memory 218412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=358976183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.358976183
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/31.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/31.hmac_datapath_stress.3649365100
Short name T493
Test name
Test status
Simulation time 19805908420 ps
CPU time 1070.06 seconds
Started Oct 15 12:08:11 AM UTC 24
Finished Oct 15 12:26:13 AM UTC 24
Peak memory 760312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3649365100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.3649365100
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/31.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/31.hmac_error.3041964704
Short name T361
Test name
Test status
Simulation time 60743102926 ps
CPU time 162.17 seconds
Started Oct 15 12:08:21 AM UTC 24
Finished Oct 15 12:11:06 AM UTC 24
Peak memory 209768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041964704 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.3041964704
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/31.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/31.hmac_long_msg.950576211
Short name T318
Test name
Test status
Simulation time 1578628595 ps
CPU time 7.05 seconds
Started Oct 15 12:07:58 AM UTC 24
Finished Oct 15 12:08:06 AM UTC 24
Peak memory 209632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=950576211 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.950576211
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/31.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/31.hmac_smoke.547021192
Short name T317
Test name
Test status
Simulation time 72924365 ps
CPU time 4.97 seconds
Started Oct 15 12:07:51 AM UTC 24
Finished Oct 15 12:07:56 AM UTC 24
Peak memory 209904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=547021192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.547021192
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/31.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/31.hmac_stress_all.3374633707
Short name T528
Test name
Test status
Simulation time 118914227925 ps
CPU time 4170.89 seconds
Started Oct 15 12:08:25 AM UTC 24
Finished Oct 15 01:18:38 AM UTC 24
Peak memory 803444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374633707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.3374633707
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/31.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/31.hmac_wipe_secret.1441679428
Short name T325
Test name
Test status
Simulation time 1157348297 ps
CPU time 8.9 seconds
Started Oct 15 12:08:21 AM UTC 24
Finished Oct 15 12:08:31 AM UTC 24
Peak memory 209508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1441679428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.1441679428
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/31.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/32.hmac_alert_test.1386713914
Short name T334
Test name
Test status
Simulation time 11940497 ps
CPU time 0.94 seconds
Started Oct 15 12:09:00 AM UTC 24
Finished Oct 15 12:09:02 AM UTC 24
Peak memory 206376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1386713914 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.1386713914
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/32.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/32.hmac_back_pressure.3625276737
Short name T332
Test name
Test status
Simulation time 582656548 ps
CPU time 23.83 seconds
Started Oct 15 12:08:34 AM UTC 24
Finished Oct 15 12:09:00 AM UTC 24
Peak memory 209692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3625276737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.3625276737
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/32.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/32.hmac_burst_wr.1949139512
Short name T346
Test name
Test status
Simulation time 5526945911 ps
CPU time 66.76 seconds
Started Oct 15 12:08:42 AM UTC 24
Finished Oct 15 12:09:51 AM UTC 24
Peak memory 209764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1949139512 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.1949139512
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/32.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/32.hmac_datapath_stress.3274790072
Short name T377
Test name
Test status
Simulation time 1060026279 ps
CPU time 225.18 seconds
Started Oct 15 12:08:39 AM UTC 24
Finished Oct 15 12:12:28 AM UTC 24
Peak memory 684524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3274790072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.3274790072
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/32.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/32.hmac_error.3828241225
Short name T352
Test name
Test status
Simulation time 12835733927 ps
CPU time 89.53 seconds
Started Oct 15 12:08:52 AM UTC 24
Finished Oct 15 12:10:24 AM UTC 24
Peak memory 209800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3828241225 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.3828241225
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/32.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/32.hmac_long_msg.1298511904
Short name T366
Test name
Test status
Simulation time 5795297939 ps
CPU time 185.05 seconds
Started Oct 15 12:08:33 AM UTC 24
Finished Oct 15 12:11:42 AM UTC 24
Peak memory 209640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1298511904 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.1298511904
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/32.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/32.hmac_smoke.1629307240
Short name T328
Test name
Test status
Simulation time 1410869196 ps
CPU time 7.41 seconds
Started Oct 15 12:08:33 AM UTC 24
Finished Oct 15 12:08:42 AM UTC 24
Peak memory 209712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629307240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.1629307240
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/32.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/32.hmac_stress_all.3308343809
Short name T394
Test name
Test status
Simulation time 19182579868 ps
CPU time 282 seconds
Started Oct 15 12:08:58 AM UTC 24
Finished Oct 15 12:13:44 AM UTC 24
Peak memory 220380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3308343809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.3308343809
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/32.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/32.hmac_wipe_secret.2378866005
Short name T100
Test name
Test status
Simulation time 7633488005 ps
CPU time 108.41 seconds
Started Oct 15 12:08:52 AM UTC 24
Finished Oct 15 12:10:43 AM UTC 24
Peak memory 209916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2378866005 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.2378866005
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/32.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/33.hmac_alert_test.788259900
Short name T342
Test name
Test status
Simulation time 45125875 ps
CPU time 0.84 seconds
Started Oct 15 12:09:29 AM UTC 24
Finished Oct 15 12:09:31 AM UTC 24
Peak memory 206316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=788259900 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.788259900
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/33.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/33.hmac_back_pressure.4018176975
Short name T32
Test name
Test status
Simulation time 1040608451 ps
CPU time 68.96 seconds
Started Oct 15 12:09:12 AM UTC 24
Finished Oct 15 12:10:23 AM UTC 24
Peak memory 209636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4018176975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.4018176975
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/33.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/33.hmac_burst_wr.2100782228
Short name T345
Test name
Test status
Simulation time 2161151506 ps
CPU time 27.82 seconds
Started Oct 15 12:09:20 AM UTC 24
Finished Oct 15 12:09:49 AM UTC 24
Peak memory 209764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2100782228 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.2100782228
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/33.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/33.hmac_datapath_stress.2892928145
Short name T492
Test name
Test status
Simulation time 5271595495 ps
CPU time 941.37 seconds
Started Oct 15 12:09:16 AM UTC 24
Finished Oct 15 12:25:07 AM UTC 24
Peak memory 762484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2892928145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.2892928145
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/33.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/33.hmac_error.152304101
Short name T380
Test name
Test status
Simulation time 44809165679 ps
CPU time 185.69 seconds
Started Oct 15 12:09:23 AM UTC 24
Finished Oct 15 12:12:32 AM UTC 24
Peak memory 209700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152304101 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.152304101
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/33.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/33.hmac_long_msg.3238985559
Short name T371
Test name
Test status
Simulation time 33512461250 ps
CPU time 172.5 seconds
Started Oct 15 12:09:03 AM UTC 24
Finished Oct 15 12:11:58 AM UTC 24
Peak memory 209760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3238985559 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.3238985559
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/33.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/33.hmac_smoke.3056379875
Short name T337
Test name
Test status
Simulation time 1004957747 ps
CPU time 15.06 seconds
Started Oct 15 12:09:03 AM UTC 24
Finished Oct 15 12:09:19 AM UTC 24
Peak memory 209700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056379875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.3056379875
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/33.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/33.hmac_stress_all.2676131129
Short name T516
Test name
Test status
Simulation time 93447080143 ps
CPU time 1761.12 seconds
Started Oct 15 12:09:26 AM UTC 24
Finished Oct 15 12:39:05 AM UTC 24
Peak memory 776952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2676131129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.2676131129
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/33.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/33.hmac_wipe_secret.1378083229
Short name T349
Test name
Test status
Simulation time 21457524707 ps
CPU time 47.04 seconds
Started Oct 15 12:09:25 AM UTC 24
Finished Oct 15 12:10:13 AM UTC 24
Peak memory 209960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378083229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.1378083229
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/33.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/34.hmac_alert_test.1202792370
Short name T348
Test name
Test status
Simulation time 38261703 ps
CPU time 0.85 seconds
Started Oct 15 12:09:57 AM UTC 24
Finished Oct 15 12:09:59 AM UTC 24
Peak memory 206316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1202792370 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.1202792370
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/34.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/34.hmac_back_pressure.183331005
Short name T354
Test name
Test status
Simulation time 743314361 ps
CPU time 54.3 seconds
Started Oct 15 12:09:34 AM UTC 24
Finished Oct 15 12:10:30 AM UTC 24
Peak memory 209904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=183331005 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.183331005
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/34.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/34.hmac_burst_wr.4158078286
Short name T161
Test name
Test status
Simulation time 51856096 ps
CPU time 3.63 seconds
Started Oct 15 12:09:51 AM UTC 24
Finished Oct 15 12:09:56 AM UTC 24
Peak memory 209632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4158078286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.4158078286
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/34.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/34.hmac_datapath_stress.3013982138
Short name T494
Test name
Test status
Simulation time 20510368507 ps
CPU time 981.44 seconds
Started Oct 15 12:09:51 AM UTC 24
Finished Oct 15 12:26:23 AM UTC 24
Peak memory 702956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3013982138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.3013982138
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/34.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/34.hmac_error.532988440
Short name T353
Test name
Test status
Simulation time 4081244159 ps
CPU time 35.25 seconds
Started Oct 15 12:09:52 AM UTC 24
Finished Oct 15 12:10:28 AM UTC 24
Peak memory 209756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=532988440 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.532988440
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/34.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/34.hmac_long_msg.2925397167
Short name T350
Test name
Test status
Simulation time 879231229 ps
CPU time 41.61 seconds
Started Oct 15 12:09:32 AM UTC 24
Finished Oct 15 12:10:15 AM UTC 24
Peak memory 209696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2925397167 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.2925397167
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/34.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/34.hmac_smoke.111069007
Short name T343
Test name
Test status
Simulation time 529460586 ps
CPU time 3.41 seconds
Started Oct 15 12:09:29 AM UTC 24
Finished Oct 15 12:09:34 AM UTC 24
Peak memory 209588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=111069007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.111069007
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/34.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/34.hmac_stress_all.184923754
Short name T403
Test name
Test status
Simulation time 14723632059 ps
CPU time 272.62 seconds
Started Oct 15 12:09:54 AM UTC 24
Finished Oct 15 12:14:30 AM UTC 24
Peak memory 209768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184923754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.184923754
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/34.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/34.hmac_wipe_secret.4036052239
Short name T367
Test name
Test status
Simulation time 6586454773 ps
CPU time 115.09 seconds
Started Oct 15 12:09:52 AM UTC 24
Finished Oct 15 12:11:49 AM UTC 24
Peak memory 209884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4036052239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.4036052239
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/34.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/35.hmac_alert_test.1959519997
Short name T356
Test name
Test status
Simulation time 12104389 ps
CPU time 0.87 seconds
Started Oct 15 12:10:40 AM UTC 24
Finished Oct 15 12:10:42 AM UTC 24
Peak memory 206316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1959519997 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.1959519997
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/35.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/35.hmac_back_pressure.1145683835
Short name T374
Test name
Test status
Simulation time 4801142074 ps
CPU time 108.43 seconds
Started Oct 15 12:10:17 AM UTC 24
Finished Oct 15 12:12:08 AM UTC 24
Peak memory 209704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1145683835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.1145683835
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/35.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/35.hmac_burst_wr.3947323724
Short name T355
Test name
Test status
Simulation time 904302552 ps
CPU time 13.22 seconds
Started Oct 15 12:10:25 AM UTC 24
Finished Oct 15 12:10:39 AM UTC 24
Peak memory 209572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3947323724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.3947323724
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/35.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/35.hmac_datapath_stress.1300863584
Short name T466
Test name
Test status
Simulation time 4524710584 ps
CPU time 579.98 seconds
Started Oct 15 12:10:19 AM UTC 24
Finished Oct 15 12:20:06 AM UTC 24
Peak memory 641512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1300863584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.1300863584
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/35.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/35.hmac_error.1871481082
Short name T407
Test name
Test status
Simulation time 38102522577 ps
CPU time 252.22 seconds
Started Oct 15 12:10:26 AM UTC 24
Finished Oct 15 12:14:42 AM UTC 24
Peak memory 209800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871481082 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.1871481082
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/35.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/35.hmac_long_msg.2548157777
Short name T378
Test name
Test status
Simulation time 2215051090 ps
CPU time 132.89 seconds
Started Oct 15 12:10:14 AM UTC 24
Finished Oct 15 12:12:30 AM UTC 24
Peak memory 209840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548157777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.2548157777
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/35.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/35.hmac_smoke.2537856924
Short name T351
Test name
Test status
Simulation time 3024355310 ps
CPU time 16.09 seconds
Started Oct 15 12:10:00 AM UTC 24
Finished Oct 15 12:10:18 AM UTC 24
Peak memory 209764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2537856924 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.2537856924
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/35.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/35.hmac_stress_all.3285241331
Short name T80
Test name
Test status
Simulation time 152223388009 ps
CPU time 710.06 seconds
Started Oct 15 12:10:32 AM UTC 24
Finished Oct 15 12:22:30 AM UTC 24
Peak memory 218280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3285241331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.3285241331
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/35.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/35.hmac_wipe_secret.2611268103
Short name T365
Test name
Test status
Simulation time 12304396625 ps
CPU time 67.16 seconds
Started Oct 15 12:10:29 AM UTC 24
Finished Oct 15 12:11:38 AM UTC 24
Peak memory 209760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611268103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.2611268103
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/35.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/36.hmac_alert_test.2556111843
Short name T364
Test name
Test status
Simulation time 11579455 ps
CPU time 0.89 seconds
Started Oct 15 12:11:29 AM UTC 24
Finished Oct 15 12:11:31 AM UTC 24
Peak memory 206316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2556111843 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.2556111843
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/36.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/36.hmac_back_pressure.514531453
Short name T359
Test name
Test status
Simulation time 272655279 ps
CPU time 8.23 seconds
Started Oct 15 12:10:45 AM UTC 24
Finished Oct 15 12:10:54 AM UTC 24
Peak memory 209692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=514531453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.514531453
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/36.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/36.hmac_burst_wr.1987985621
Short name T159
Test name
Test status
Simulation time 1462876005 ps
CPU time 86.31 seconds
Started Oct 15 12:10:55 AM UTC 24
Finished Oct 15 12:12:24 AM UTC 24
Peak memory 218336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1987985621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.1987985621
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/36.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/36.hmac_datapath_stress.4217315848
Short name T450
Test name
Test status
Simulation time 4403644076 ps
CPU time 469.6 seconds
Started Oct 15 12:10:53 AM UTC 24
Finished Oct 15 12:18:48 AM UTC 24
Peak memory 715292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4217315848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.4217315848
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/36.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/36.hmac_error.1285929362
Short name T396
Test name
Test status
Simulation time 13387859700 ps
CPU time 165.53 seconds
Started Oct 15 12:11:01 AM UTC 24
Finished Oct 15 12:13:50 AM UTC 24
Peak memory 210020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1285929362 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.1285929362
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/36.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/36.hmac_long_msg.725125940
Short name T375
Test name
Test status
Simulation time 4653163858 ps
CPU time 85.51 seconds
Started Oct 15 12:10:45 AM UTC 24
Finished Oct 15 12:12:12 AM UTC 24
Peak memory 209716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725125940 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.725125940
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/36.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/36.hmac_smoke.1195073879
Short name T358
Test name
Test status
Simulation time 412473271 ps
CPU time 6.56 seconds
Started Oct 15 12:10:45 AM UTC 24
Finished Oct 15 12:10:53 AM UTC 24
Peak memory 209644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1195073879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.1195073879
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/36.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/36.hmac_stress_all.1438805428
Short name T521
Test name
Test status
Simulation time 328931461430 ps
CPU time 1950.22 seconds
Started Oct 15 12:11:23 AM UTC 24
Finished Oct 15 12:44:15 AM UTC 24
Peak memory 709160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1438805428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.1438805428
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/36.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/36.hmac_wipe_secret.2928069763
Short name T363
Test name
Test status
Simulation time 986813947 ps
CPU time 19.02 seconds
Started Oct 15 12:11:08 AM UTC 24
Finished Oct 15 12:11:28 AM UTC 24
Peak memory 209704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2928069763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.2928069763
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/36.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/37.hmac_alert_test.334211204
Short name T373
Test name
Test status
Simulation time 104013395 ps
CPU time 0.82 seconds
Started Oct 15 12:12:02 AM UTC 24
Finished Oct 15 12:12:04 AM UTC 24
Peak memory 206316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=334211204 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.334211204
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/37.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/37.hmac_back_pressure.2631218450
Short name T384
Test name
Test status
Simulation time 789865751 ps
CPU time 62.15 seconds
Started Oct 15 12:11:44 AM UTC 24
Finished Oct 15 12:12:48 AM UTC 24
Peak memory 209716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2631218450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.2631218450
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/37.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/37.hmac_burst_wr.2979105615
Short name T163
Test name
Test status
Simulation time 2152997270 ps
CPU time 33.67 seconds
Started Oct 15 12:11:51 AM UTC 24
Finished Oct 15 12:12:26 AM UTC 24
Peak memory 209756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2979105615 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.2979105615
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/37.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/37.hmac_datapath_stress.1665284807
Short name T489
Test name
Test status
Simulation time 4231749964 ps
CPU time 743.47 seconds
Started Oct 15 12:11:51 AM UTC 24
Finished Oct 15 12:24:23 AM UTC 24
Peak memory 735724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1665284807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.1665284807
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/37.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/37.hmac_error.938590126
Short name T395
Test name
Test status
Simulation time 1535749094 ps
CPU time 115.23 seconds
Started Oct 15 12:11:51 AM UTC 24
Finished Oct 15 12:13:49 AM UTC 24
Peak memory 209692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=938590126 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.938590126
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/37.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/37.hmac_long_msg.3921459647
Short name T369
Test name
Test status
Simulation time 1088700241 ps
CPU time 10.44 seconds
Started Oct 15 12:11:39 AM UTC 24
Finished Oct 15 12:11:50 AM UTC 24
Peak memory 209696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3921459647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.3921459647
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/37.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/37.hmac_smoke.3113743077
Short name T368
Test name
Test status
Simulation time 1374261384 ps
CPU time 16.73 seconds
Started Oct 15 12:11:32 AM UTC 24
Finished Oct 15 12:11:50 AM UTC 24
Peak memory 209700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3113743077 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.3113743077
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/37.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/37.hmac_stress_all.1818885937
Short name T514
Test name
Test status
Simulation time 126354293128 ps
CPU time 1482.07 seconds
Started Oct 15 12:12:00 AM UTC 24
Finished Oct 15 12:36:58 AM UTC 24
Peak memory 748080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1818885937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.1818885937
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/37.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/37.hmac_wipe_secret.116777739
Short name T372
Test name
Test status
Simulation time 65001008 ps
CPU time 2.32 seconds
Started Oct 15 12:11:57 AM UTC 24
Finished Oct 15 12:12:01 AM UTC 24
Peak memory 209636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116777739 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.116777739
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/37.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/38.hmac_alert_test.1020736034
Short name T381
Test name
Test status
Simulation time 11693483 ps
CPU time 0.88 seconds
Started Oct 15 12:12:32 AM UTC 24
Finished Oct 15 12:12:34 AM UTC 24
Peak memory 206376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020736034 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.1020736034
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/38.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/38.hmac_back_pressure.3892986270
Short name T383
Test name
Test status
Simulation time 2033431906 ps
CPU time 31.14 seconds
Started Oct 15 12:12:14 AM UTC 24
Finished Oct 15 12:12:46 AM UTC 24
Peak memory 209692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3892986270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.3892986270
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/38.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/38.hmac_burst_wr.3630372931
Short name T379
Test name
Test status
Simulation time 275668393 ps
CPU time 4.7 seconds
Started Oct 15 12:12:24 AM UTC 24
Finished Oct 15 12:12:30 AM UTC 24
Peak memory 209900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3630372931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.3630372931
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/38.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/38.hmac_datapath_stress.1348024836
Short name T513
Test name
Test status
Simulation time 45059096925 ps
CPU time 1446.29 seconds
Started Oct 15 12:12:14 AM UTC 24
Finished Oct 15 12:36:36 AM UTC 24
Peak memory 791284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348024836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.1348024836
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/38.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/38.hmac_error.1589361495
Short name T386
Test name
Test status
Simulation time 8888236544 ps
CPU time 49.47 seconds
Started Oct 15 12:12:27 AM UTC 24
Finished Oct 15 12:13:18 AM UTC 24
Peak memory 209640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1589361495 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.1589361495
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/38.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/38.hmac_long_msg.3352720717
Short name T389
Test name
Test status
Simulation time 6153032106 ps
CPU time 80.91 seconds
Started Oct 15 12:12:09 AM UTC 24
Finished Oct 15 12:13:32 AM UTC 24
Peak memory 209684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3352720717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.3352720717
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/38.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/38.hmac_smoke.878524382
Short name T376
Test name
Test status
Simulation time 365194148 ps
CPU time 6.59 seconds
Started Oct 15 12:12:05 AM UTC 24
Finished Oct 15 12:12:13 AM UTC 24
Peak memory 209700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=878524382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.878524382
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/38.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/38.hmac_stress_all.2998462880
Short name T498
Test name
Test status
Simulation time 131664744255 ps
CPU time 1065.28 seconds
Started Oct 15 12:12:32 AM UTC 24
Finished Oct 15 12:30:28 AM UTC 24
Peak memory 725572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2998462880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.2998462880
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/38.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/38.hmac_wipe_secret.3387511879
Short name T405
Test name
Test status
Simulation time 1950909407 ps
CPU time 124.6 seconds
Started Oct 15 12:12:29 AM UTC 24
Finished Oct 15 12:14:36 AM UTC 24
Peak memory 209696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3387511879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.3387511879
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/38.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/39.hmac_alert_test.603088604
Short name T390
Test name
Test status
Simulation time 14644716 ps
CPU time 0.8 seconds
Started Oct 15 12:13:31 AM UTC 24
Finished Oct 15 12:13:33 AM UTC 24
Peak memory 206316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=603088604 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.603088604
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/39.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/39.hmac_back_pressure.1113021261
Short name T385
Test name
Test status
Simulation time 264131898 ps
CPU time 15.53 seconds
Started Oct 15 12:12:46 AM UTC 24
Finished Oct 15 12:13:03 AM UTC 24
Peak memory 209692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1113021261 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.1113021261
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/39.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/39.hmac_burst_wr.1399506584
Short name T392
Test name
Test status
Simulation time 2781562873 ps
CPU time 49.88 seconds
Started Oct 15 12:12:49 AM UTC 24
Finished Oct 15 12:13:41 AM UTC 24
Peak memory 209776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1399506584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.1399506584
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/39.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/39.hmac_datapath_stress.1925242405
Short name T462
Test name
Test status
Simulation time 1878055142 ps
CPU time 395.77 seconds
Started Oct 15 12:12:48 AM UTC 24
Finished Oct 15 12:19:28 AM UTC 24
Peak memory 717272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1925242405 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.1925242405
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/39.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/39.hmac_error.3101343995
Short name T400
Test name
Test status
Simulation time 12794859773 ps
CPU time 72.91 seconds
Started Oct 15 12:13:04 AM UTC 24
Finished Oct 15 12:14:19 AM UTC 24
Peak memory 209824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3101343995 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.3101343995
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/39.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/39.hmac_long_msg.1903933270
Short name T391
Test name
Test status
Simulation time 868491448 ps
CPU time 62.02 seconds
Started Oct 15 12:12:34 AM UTC 24
Finished Oct 15 12:13:38 AM UTC 24
Peak memory 209844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1903933270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.1903933270
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/39.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/39.hmac_smoke.3463295392
Short name T382
Test name
Test status
Simulation time 2823090458 ps
CPU time 11.37 seconds
Started Oct 15 12:12:33 AM UTC 24
Finished Oct 15 12:12:46 AM UTC 24
Peak memory 209836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463295392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.3463295392
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/39.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/39.hmac_stress_all.2002432178
Short name T497
Test name
Test status
Simulation time 146167116571 ps
CPU time 863.83 seconds
Started Oct 15 12:13:28 AM UTC 24
Finished Oct 15 12:28:02 AM UTC 24
Peak memory 731876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002432178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.2002432178
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/39.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/39.hmac_wipe_secret.2932250644
Short name T387
Test name
Test status
Simulation time 276613894 ps
CPU time 5.3 seconds
Started Oct 15 12:13:20 AM UTC 24
Finished Oct 15 12:13:27 AM UTC 24
Peak memory 209604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2932250644 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.2932250644
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/39.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/4.hmac_alert_test.796996521
Short name T170
Test name
Test status
Simulation time 150011389 ps
CPU time 0.88 seconds
Started Oct 14 11:54:27 PM UTC 24
Finished Oct 14 11:54:29 PM UTC 24
Peak memory 206316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=796996521 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.796996521
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/4.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/4.hmac_back_pressure.2322303893
Short name T48
Test name
Test status
Simulation time 6965536581 ps
CPU time 123.98 seconds
Started Oct 14 11:53:52 PM UTC 24
Finished Oct 14 11:55:58 PM UTC 24
Peak memory 209620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2322303893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.2322303893
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/4.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/4.hmac_burst_wr.2968731594
Short name T45
Test name
Test status
Simulation time 3672715568 ps
CPU time 43.9 seconds
Started Oct 14 11:53:59 PM UTC 24
Finished Oct 14 11:54:44 PM UTC 24
Peak memory 218332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2968731594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.2968731594
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/4.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/4.hmac_datapath_stress.268897295
Short name T148
Test name
Test status
Simulation time 773118356 ps
CPU time 59.96 seconds
Started Oct 14 11:53:54 PM UTC 24
Finished Oct 14 11:54:56 PM UTC 24
Peak memory 372756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268897295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.268897295
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/4.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/4.hmac_error.2174432019
Short name T53
Test name
Test status
Simulation time 4181510790 ps
CPU time 69.93 seconds
Started Oct 14 11:53:59 PM UTC 24
Finished Oct 14 11:55:10 PM UTC 24
Peak memory 209752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2174432019 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.2174432019
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/4.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/4.hmac_long_msg.1943466631
Short name T206
Test name
Test status
Simulation time 33439670863 ps
CPU time 281.51 seconds
Started Oct 14 11:53:51 PM UTC 24
Finished Oct 14 11:58:36 PM UTC 24
Peak memory 220400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1943466631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.1943466631
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/4.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/4.hmac_sec_cm.2544520095
Short name T60
Test name
Test status
Simulation time 379064209 ps
CPU time 1.58 seconds
Started Oct 14 11:54:27 PM UTC 24
Finished Oct 14 11:54:29 PM UTC 24
Peak memory 238012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2544520095 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.2544520095
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/4.hmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/4.hmac_smoke.910240483
Short name T147
Test name
Test status
Simulation time 115955859 ps
CPU time 2.41 seconds
Started Oct 14 11:53:50 PM UTC 24
Finished Oct 14 11:53:53 PM UTC 24
Peak memory 209628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=910240483 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.910240483
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/4.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/4.hmac_stress_all.1439109541
Short name T79
Test name
Test status
Simulation time 64764283347 ps
CPU time 1297.62 seconds
Started Oct 14 11:54:20 PM UTC 24
Finished Oct 15 12:16:11 AM UTC 24
Peak memory 707260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1439109541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.1439109541
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/4.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/4.hmac_stress_all_with_rand_reset.827269907
Short name T66
Test name
Test status
Simulation time 4792337936 ps
CPU time 169.17 seconds
Started Oct 14 11:54:27 PM UTC 24
Finished Oct 14 11:57:18 PM UTC 24
Peak memory 692924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=82726990
7 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all_with_rand_reset.827269907
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/4.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/4.hmac_test_hmac256_vectors.1770084889
Short name T177
Test name
Test status
Simulation time 4884016755 ps
CPU time 45.62 seconds
Started Oct 14 11:54:13 PM UTC 24
Finished Oct 14 11:55:00 PM UTC 24
Peak memory 209840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1770084889 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac256_vectors.1770084889
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/4.hmac_test_hmac256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/4.hmac_test_hmac384_vectors.3374931084
Short name T95
Test name
Test status
Simulation time 22043665559 ps
CPU time 75.25 seconds
Started Oct 14 11:54:20 PM UTC 24
Finished Oct 14 11:55:37 PM UTC 24
Peak memory 209712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374931084 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_14/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac384_vectors.3374931084
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/4.hmac_test_hmac384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/4.hmac_test_hmac512_vectors.20724481
Short name T189
Test name
Test status
Simulation time 21799317479 ps
CPU time 164.5 seconds
Started Oct 14 11:54:20 PM UTC 24
Finished Oct 14 11:57:07 PM UTC 24
Peak memory 209780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20724481 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac512_vectors.20724481
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/4.hmac_test_hmac512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/4.hmac_test_sha256_vectors.1032581636
Short name T151
Test name
Test status
Simulation time 9966318924 ps
CPU time 548.84 seconds
Started Oct 14 11:54:04 PM UTC 24
Finished Oct 15 12:03:20 AM UTC 24
Peak memory 209700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032581636 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha256_vectors.1032581636
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/4.hmac_test_sha256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/4.hmac_test_sha384_vectors.1024088341
Short name T520
Test name
Test status
Simulation time 207114326067 ps
CPU time 2962.42 seconds
Started Oct 14 11:54:10 PM UTC 24
Finished Oct 15 12:44:07 AM UTC 24
Peak memory 229736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024088341 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha384_vectors.1024088341
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/4.hmac_test_sha384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/4.hmac_test_sha512_vectors.3253035890
Short name T499
Test name
Test status
Simulation time 60515932762 ps
CPU time 2157.4 seconds
Started Oct 14 11:54:12 PM UTC 24
Finished Oct 15 12:30:36 AM UTC 24
Peak memory 229940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253035890 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha512_vectors.3253035890
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/4.hmac_test_sha512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/4.hmac_wipe_secret.2983555879
Short name T86
Test name
Test status
Simulation time 5381682832 ps
CPU time 76.43 seconds
Started Oct 14 11:54:00 PM UTC 24
Finished Oct 14 11:55:18 PM UTC 24
Peak memory 209756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2983555879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.2983555879
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/4.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/40.hmac_alert_test.1169926484
Short name T398
Test name
Test status
Simulation time 16524632 ps
CPU time 0.84 seconds
Started Oct 15 12:14:06 AM UTC 24
Finished Oct 15 12:14:08 AM UTC 24
Peak memory 206316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1169926484 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.1169926484
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/40.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/40.hmac_back_pressure.1847992644
Short name T406
Test name
Test status
Simulation time 3731027496 ps
CPU time 57.94 seconds
Started Oct 15 12:13:39 AM UTC 24
Finished Oct 15 12:14:39 AM UTC 24
Peak memory 209764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847992644 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.1847992644
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/40.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/40.hmac_burst_wr.862407650
Short name T402
Test name
Test status
Simulation time 1561533452 ps
CPU time 38.82 seconds
Started Oct 15 12:13:42 AM UTC 24
Finished Oct 15 12:14:23 AM UTC 24
Peak memory 209968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=862407650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.862407650
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/40.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/40.hmac_datapath_stress.2667767586
Short name T444
Test name
Test status
Simulation time 9758955756 ps
CPU time 266.09 seconds
Started Oct 15 12:13:41 AM UTC 24
Finished Oct 15 12:18:11 AM UTC 24
Peak memory 647668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2667767586 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.2667767586
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/40.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/40.hmac_error.1351758927
Short name T431
Test name
Test status
Simulation time 24958722579 ps
CPU time 203.6 seconds
Started Oct 15 12:13:46 AM UTC 24
Finished Oct 15 12:17:13 AM UTC 24
Peak memory 209760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1351758927 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.1351758927
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/40.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/40.hmac_long_msg.1554657130
Short name T413
Test name
Test status
Simulation time 23802663524 ps
CPU time 120.88 seconds
Started Oct 15 12:13:34 AM UTC 24
Finished Oct 15 12:15:37 AM UTC 24
Peak memory 209704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1554657130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.1554657130
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/40.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/40.hmac_smoke.3396124768
Short name T393
Test name
Test status
Simulation time 222532145 ps
CPU time 6.12 seconds
Started Oct 15 12:13:34 AM UTC 24
Finished Oct 15 12:13:41 AM UTC 24
Peak memory 209900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3396124768 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.3396124768
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/40.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/40.hmac_stress_all.3956604442
Short name T437
Test name
Test status
Simulation time 41950097039 ps
CPU time 212.95 seconds
Started Oct 15 12:13:52 AM UTC 24
Finished Oct 15 12:17:28 AM UTC 24
Peak memory 218348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3956604442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.3956604442
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/40.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/40.hmac_wipe_secret.1384350837
Short name T397
Test name
Test status
Simulation time 187372845 ps
CPU time 13.74 seconds
Started Oct 15 12:13:50 AM UTC 24
Finished Oct 15 12:14:05 AM UTC 24
Peak memory 209840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1384350837 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.1384350837
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/40.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/41.hmac_alert_test.741312969
Short name T408
Test name
Test status
Simulation time 18529819 ps
CPU time 0.88 seconds
Started Oct 15 12:14:40 AM UTC 24
Finished Oct 15 12:14:42 AM UTC 24
Peak memory 206316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741312969 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.741312969
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/41.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/41.hmac_back_pressure.4050843411
Short name T404
Test name
Test status
Simulation time 196478992 ps
CPU time 12.4 seconds
Started Oct 15 12:14:20 AM UTC 24
Finished Oct 15 12:14:34 AM UTC 24
Peak memory 209572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4050843411 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.4050843411
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/41.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/41.hmac_burst_wr.106784036
Short name T419
Test name
Test status
Simulation time 3851535052 ps
CPU time 92.71 seconds
Started Oct 15 12:14:23 AM UTC 24
Finished Oct 15 12:15:58 AM UTC 24
Peak memory 218312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=106784036 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.106784036
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/41.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/41.hmac_datapath_stress.1715461564
Short name T448
Test name
Test status
Simulation time 6697860423 ps
CPU time 258.37 seconds
Started Oct 15 12:14:23 AM UTC 24
Finished Oct 15 12:18:45 AM UTC 24
Peak memory 729776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1715461564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.1715461564
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/41.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/41.hmac_error.96864976
Short name T445
Test name
Test status
Simulation time 10871013812 ps
CPU time 218.87 seconds
Started Oct 15 12:14:33 AM UTC 24
Finished Oct 15 12:18:15 AM UTC 24
Peak memory 209952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=96864976 -assert nopostproc +UVM_TESTNAME=hmac
_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.96864976
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/41.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/41.hmac_long_msg.1472244903
Short name T409
Test name
Test status
Simulation time 4550029103 ps
CPU time 31.11 seconds
Started Oct 15 12:14:14 AM UTC 24
Finished Oct 15 12:14:46 AM UTC 24
Peak memory 209776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1472244903 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.1472244903
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/41.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/41.hmac_smoke.4006499666
Short name T399
Test name
Test status
Simulation time 300137952 ps
CPU time 3.45 seconds
Started Oct 15 12:14:09 AM UTC 24
Finished Oct 15 12:14:13 AM UTC 24
Peak memory 209644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4006499666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.4006499666
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/41.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/41.hmac_stress_all.3265491402
Short name T490
Test name
Test status
Simulation time 194069463780 ps
CPU time 906.6 seconds
Started Oct 15 12:14:38 AM UTC 24
Finished Oct 15 12:29:55 AM UTC 24
Peak memory 254560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3265491402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.3265491402
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/41.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/41.hmac_wipe_secret.3185059626
Short name T411
Test name
Test status
Simulation time 4294932745 ps
CPU time 40.2 seconds
Started Oct 15 12:14:35 AM UTC 24
Finished Oct 15 12:15:16 AM UTC 24
Peak memory 209936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3185059626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.3185059626
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/41.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/42.hmac_alert_test.2592974637
Short name T417
Test name
Test status
Simulation time 14169244 ps
CPU time 0.85 seconds
Started Oct 15 12:15:53 AM UTC 24
Finished Oct 15 12:15:54 AM UTC 24
Peak memory 206316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2592974637 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.2592974637
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/42.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/42.hmac_burst_wr.3693086990
Short name T422
Test name
Test status
Simulation time 3603982615 ps
CPU time 58.23 seconds
Started Oct 15 12:15:17 AM UTC 24
Finished Oct 15 12:16:17 AM UTC 24
Peak memory 209832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693086990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.3693086990
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/42.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/42.hmac_datapath_stress.3754868194
Short name T511
Test name
Test status
Simulation time 25501550210 ps
CPU time 1222.26 seconds
Started Oct 15 12:14:59 AM UTC 24
Finished Oct 15 12:35:35 AM UTC 24
Peak memory 748276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754868194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.3754868194
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/42.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/42.hmac_error.3014890702
Short name T418
Test name
Test status
Simulation time 1339967151 ps
CPU time 16.31 seconds
Started Oct 15 12:15:39 AM UTC 24
Finished Oct 15 12:15:56 AM UTC 24
Peak memory 209504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3014890702 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.3014890702
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/42.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/42.hmac_long_msg.724984289
Short name T414
Test name
Test status
Simulation time 805296268 ps
CPU time 58.17 seconds
Started Oct 15 12:14:45 AM UTC 24
Finished Oct 15 12:15:44 AM UTC 24
Peak memory 209704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=724984289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.724984289
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/42.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/42.hmac_smoke.892147148
Short name T410
Test name
Test status
Simulation time 196894823 ps
CPU time 12.13 seconds
Started Oct 15 12:14:44 AM UTC 24
Finished Oct 15 12:14:58 AM UTC 24
Peak memory 209700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=892147148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.892147148
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/42.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/42.hmac_stress_all.2361570854
Short name T522
Test name
Test status
Simulation time 59559201633 ps
CPU time 1804.19 seconds
Started Oct 15 12:15:45 AM UTC 24
Finished Oct 15 12:46:09 AM UTC 24
Peak memory 774680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2361570854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.2361570854
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/42.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/42.hmac_wipe_secret.3185435812
Short name T430
Test name
Test status
Simulation time 17599328908 ps
CPU time 90.42 seconds
Started Oct 15 12:15:39 AM UTC 24
Finished Oct 15 12:17:11 AM UTC 24
Peak memory 209764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3185435812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.3185435812
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/42.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/43.hmac_alert_test.1780607120
Short name T424
Test name
Test status
Simulation time 38086072 ps
CPU time 0.76 seconds
Started Oct 15 12:16:18 AM UTC 24
Finished Oct 15 12:16:20 AM UTC 24
Peak memory 206316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1780607120 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.1780607120
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/43.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/43.hmac_back_pressure.675718828
Short name T429
Test name
Test status
Simulation time 17231435291 ps
CPU time 57.35 seconds
Started Oct 15 12:15:59 AM UTC 24
Finished Oct 15 12:16:58 AM UTC 24
Peak memory 226088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=675718828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.675718828
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/43.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/43.hmac_burst_wr.2958165163
Short name T427
Test name
Test status
Simulation time 530965983 ps
CPU time 37.87 seconds
Started Oct 15 12:16:00 AM UTC 24
Finished Oct 15 12:16:40 AM UTC 24
Peak memory 218536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958165163 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.2958165163
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/43.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/43.hmac_datapath_stress.3548709538
Short name T519
Test name
Test status
Simulation time 7695166304 ps
CPU time 1576.15 seconds
Started Oct 15 12:15:59 AM UTC 24
Finished Oct 15 12:42:31 AM UTC 24
Peak memory 805336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3548709538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.3548709538
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/43.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/43.hmac_error.1773482457
Short name T460
Test name
Test status
Simulation time 15830259046 ps
CPU time 192.19 seconds
Started Oct 15 12:16:06 AM UTC 24
Finished Oct 15 12:19:22 AM UTC 24
Peak memory 209704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1773482457 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.1773482457
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/43.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/43.hmac_long_msg.1626341005
Short name T420
Test name
Test status
Simulation time 334360276 ps
CPU time 5.61 seconds
Started Oct 15 12:15:59 AM UTC 24
Finished Oct 15 12:16:06 AM UTC 24
Peak memory 209640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626341005 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.1626341005
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/43.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/43.hmac_smoke.3734067567
Short name T421
Test name
Test status
Simulation time 1105903472 ps
CPU time 14.37 seconds
Started Oct 15 12:15:59 AM UTC 24
Finished Oct 15 12:16:14 AM UTC 24
Peak memory 209752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3734067567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.3734067567
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/43.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/43.hmac_stress_all.2435274739
Short name T512
Test name
Test status
Simulation time 63712266415 ps
CPU time 1145.51 seconds
Started Oct 15 12:16:18 AM UTC 24
Finished Oct 15 12:35:37 AM UTC 24
Peak memory 658212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2435274739 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.2435274739
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/43.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/43.hmac_wipe_secret.881919264
Short name T433
Test name
Test status
Simulation time 16181385158 ps
CPU time 55.02 seconds
Started Oct 15 12:16:18 AM UTC 24
Finished Oct 15 12:17:15 AM UTC 24
Peak memory 209744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=881919264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.881919264
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/43.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/44.hmac_alert_test.733509386
Short name T434
Test name
Test status
Simulation time 33334494 ps
CPU time 0.92 seconds
Started Oct 15 12:17:14 AM UTC 24
Finished Oct 15 12:17:16 AM UTC 24
Peak memory 206316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=733509386 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.733509386
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/44.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/44.hmac_back_pressure.1731882841
Short name T440
Test name
Test status
Simulation time 1782870381 ps
CPU time 66.48 seconds
Started Oct 15 12:16:25 AM UTC 24
Finished Oct 15 12:17:33 AM UTC 24
Peak memory 209636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1731882841 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.1731882841
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/44.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/44.hmac_burst_wr.31185092
Short name T435
Test name
Test status
Simulation time 1474946197 ps
CPU time 35.89 seconds
Started Oct 15 12:16:40 AM UTC 24
Finished Oct 15 12:17:17 AM UTC 24
Peak memory 209716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31185092 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac
_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.31185092
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/44.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/44.hmac_datapath_stress.2065685505
Short name T509
Test name
Test status
Simulation time 6090727286 ps
CPU time 1079.06 seconds
Started Oct 15 12:16:36 AM UTC 24
Finished Oct 15 12:34:47 AM UTC 24
Peak memory 713272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2065685505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.2065685505
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/44.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/44.hmac_error.3256283038
Short name T447
Test name
Test status
Simulation time 19451980218 ps
CPU time 73.02 seconds
Started Oct 15 12:17:02 AM UTC 24
Finished Oct 15 12:18:17 AM UTC 24
Peak memory 209760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3256283038 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.3256283038
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/44.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/44.hmac_long_msg.2265076780
Short name T446
Test name
Test status
Simulation time 3547177972 ps
CPU time 107.97 seconds
Started Oct 15 12:16:25 AM UTC 24
Finished Oct 15 12:18:15 AM UTC 24
Peak memory 209752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2265076780 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.2265076780
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/44.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/44.hmac_smoke.2261839032
Short name T426
Test name
Test status
Simulation time 1672709262 ps
CPU time 8.75 seconds
Started Oct 15 12:16:25 AM UTC 24
Finished Oct 15 12:16:35 AM UTC 24
Peak memory 209660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2261839032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.2261839032
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/44.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/44.hmac_stress_all.2061941058
Short name T34
Test name
Test status
Simulation time 7032811071 ps
CPU time 407.1 seconds
Started Oct 15 12:17:13 AM UTC 24
Finished Oct 15 12:24:05 AM UTC 24
Peak memory 220456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2061941058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.2061941058
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/44.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/44.hmac_wipe_secret.1444636447
Short name T452
Test name
Test status
Simulation time 24008434116 ps
CPU time 107.33 seconds
Started Oct 15 12:17:02 AM UTC 24
Finished Oct 15 12:18:51 AM UTC 24
Peak memory 209704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1444636447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.1444636447
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/44.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/45.hmac_alert_test.1863313660
Short name T441
Test name
Test status
Simulation time 118338002 ps
CPU time 0.91 seconds
Started Oct 15 12:17:34 AM UTC 24
Finished Oct 15 12:17:36 AM UTC 24
Peak memory 206376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1863313660 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.1863313660
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/45.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/45.hmac_back_pressure.46588493
Short name T453
Test name
Test status
Simulation time 4436779771 ps
CPU time 95.63 seconds
Started Oct 15 12:17:18 AM UTC 24
Finished Oct 15 12:18:55 AM UTC 24
Peak memory 209836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=46588493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UV
M_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.46588493
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/45.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/45.hmac_burst_wr.3879807200
Short name T439
Test name
Test status
Simulation time 237194269 ps
CPU time 8.55 seconds
Started Oct 15 12:17:22 AM UTC 24
Finished Oct 15 12:17:32 AM UTC 24
Peak memory 209716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3879807200 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.3879807200
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/45.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/45.hmac_datapath_stress.4161925395
Short name T436
Test name
Test status
Simulation time 23867475 ps
CPU time 0.93 seconds
Started Oct 15 12:17:19 AM UTC 24
Finished Oct 15 12:17:21 AM UTC 24
Peak memory 207168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4161925395 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.4161925395
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/45.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/45.hmac_error.3254139655
Short name T481
Test name
Test status
Simulation time 176545606668 ps
CPU time 207.51 seconds
Started Oct 15 12:17:30 AM UTC 24
Finished Oct 15 12:21:01 AM UTC 24
Peak memory 209704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3254139655 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.3254139655
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/45.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/45.hmac_long_msg.3089211555
Short name T465
Test name
Test status
Simulation time 16755154555 ps
CPU time 160.98 seconds
Started Oct 15 12:17:18 AM UTC 24
Finished Oct 15 12:20:01 AM UTC 24
Peak memory 209708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3089211555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.3089211555
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/45.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/45.hmac_smoke.2454797234
Short name T438
Test name
Test status
Simulation time 554966590 ps
CPU time 9.79 seconds
Started Oct 15 12:17:18 AM UTC 24
Finished Oct 15 12:17:29 AM UTC 24
Peak memory 209836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2454797234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.2454797234
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/45.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/45.hmac_stress_all.3972861947
Short name T85
Test name
Test status
Simulation time 250216688559 ps
CPU time 3220.15 seconds
Started Oct 15 12:17:33 AM UTC 24
Finished Oct 15 01:11:45 AM UTC 24
Peak memory 815660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3972861947 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.3972861947
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/45.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/45.hmac_wipe_secret.2994943164
Short name T101
Test name
Test status
Simulation time 16561956114 ps
CPU time 76.63 seconds
Started Oct 15 12:17:30 AM UTC 24
Finished Oct 15 12:18:49 AM UTC 24
Peak memory 209760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2994943164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.2994943164
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/45.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/46.hmac_alert_test.3868800094
Short name T451
Test name
Test status
Simulation time 47926584 ps
CPU time 0.84 seconds
Started Oct 15 12:18:47 AM UTC 24
Finished Oct 15 12:18:49 AM UTC 24
Peak memory 206316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3868800094 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.3868800094
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/46.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/46.hmac_back_pressure.158301655
Short name T455
Test name
Test status
Simulation time 764589897 ps
CPU time 49.48 seconds
Started Oct 15 12:18:13 AM UTC 24
Finished Oct 15 12:19:04 AM UTC 24
Peak memory 209552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=158301655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.158301655
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/46.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/46.hmac_burst_wr.2957440971
Short name T449
Test name
Test status
Simulation time 391661384 ps
CPU time 27.73 seconds
Started Oct 15 12:18:17 AM UTC 24
Finished Oct 15 12:18:46 AM UTC 24
Peak memory 209636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2957440971 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.2957440971
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/46.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/46.hmac_datapath_stress.1073758238
Short name T508
Test name
Test status
Simulation time 5025662780 ps
CPU time 970.35 seconds
Started Oct 15 12:18:13 AM UTC 24
Finished Oct 15 12:34:34 AM UTC 24
Peak memory 700864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1073758238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.1073758238
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/46.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/46.hmac_error.234830341
Short name T486
Test name
Test status
Simulation time 56974355959 ps
CPU time 254.32 seconds
Started Oct 15 12:18:17 AM UTC 24
Finished Oct 15 12:22:36 AM UTC 24
Peak memory 209700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234830341 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.234830341
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/46.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/46.hmac_long_msg.1646829761
Short name T483
Test name
Test status
Simulation time 40938167233 ps
CPU time 231.79 seconds
Started Oct 15 12:17:49 AM UTC 24
Finished Oct 15 12:21:45 AM UTC 24
Peak memory 218352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1646829761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.1646829761
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/46.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/46.hmac_smoke.3319556427
Short name T442
Test name
Test status
Simulation time 3361531226 ps
CPU time 9.83 seconds
Started Oct 15 12:17:37 AM UTC 24
Finished Oct 15 12:17:48 AM UTC 24
Peak memory 209908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3319556427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.3319556427
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/46.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/46.hmac_stress_all.903721468
Short name T527
Test name
Test status
Simulation time 410485635999 ps
CPU time 2876.83 seconds
Started Oct 15 12:18:46 AM UTC 24
Finished Oct 15 01:07:13 AM UTC 24
Peak memory 750144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=903721468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.903721468
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/46.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/46.hmac_wipe_secret.2572038668
Short name T463
Test name
Test status
Simulation time 7038811479 ps
CPU time 88.5 seconds
Started Oct 15 12:18:18 AM UTC 24
Finished Oct 15 12:19:48 AM UTC 24
Peak memory 209760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572038668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.2572038668
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/46.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/47.hmac_alert_test.651731362
Short name T459
Test name
Test status
Simulation time 17384762 ps
CPU time 0.73 seconds
Started Oct 15 12:19:19 AM UTC 24
Finished Oct 15 12:19:21 AM UTC 24
Peak memory 206376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=651731362 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.651731362
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/47.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/47.hmac_back_pressure.2997771540
Short name T467
Test name
Test status
Simulation time 1331209705 ps
CPU time 74.41 seconds
Started Oct 15 12:18:50 AM UTC 24
Finished Oct 15 12:20:07 AM UTC 24
Peak memory 209644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2997771540 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.2997771540
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/47.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/47.hmac_burst_wr.4116882897
Short name T458
Test name
Test status
Simulation time 3330908316 ps
CPU time 18.58 seconds
Started Oct 15 12:18:58 AM UTC 24
Finished Oct 15 12:19:18 AM UTC 24
Peak memory 209840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116882897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.4116882897
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/47.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/47.hmac_datapath_stress.2922984214
Short name T491
Test name
Test status
Simulation time 2100171770 ps
CPU time 356.13 seconds
Started Oct 15 12:18:53 AM UTC 24
Finished Oct 15 12:24:54 AM UTC 24
Peak memory 645684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2922984214 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.2922984214
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/47.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/47.hmac_error.181402344
Short name T456
Test name
Test status
Simulation time 4192598187 ps
CPU time 14.3 seconds
Started Oct 15 12:18:59 AM UTC 24
Finished Oct 15 12:19:15 AM UTC 24
Peak memory 209756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=181402344 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.181402344
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/47.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/47.hmac_long_msg.3501843960
Short name T478
Test name
Test status
Simulation time 6486690203 ps
CPU time 121.29 seconds
Started Oct 15 12:18:50 AM UTC 24
Finished Oct 15 12:20:54 AM UTC 24
Peak memory 209908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501843960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.3501843960
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/47.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/47.hmac_smoke.1596328155
Short name T454
Test name
Test status
Simulation time 1493982410 ps
CPU time 6.65 seconds
Started Oct 15 12:18:50 AM UTC 24
Finished Oct 15 12:18:58 AM UTC 24
Peak memory 209644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596328155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.1596328155
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/47.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/47.hmac_stress_all.679661567
Short name T525
Test name
Test status
Simulation time 264781906396 ps
CPU time 2351.47 seconds
Started Oct 15 12:19:16 AM UTC 24
Finished Oct 15 12:58:50 AM UTC 24
Peak memory 760312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=679661567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.679661567
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/47.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/47.hmac_wipe_secret.2010233383
Short name T464
Test name
Test status
Simulation time 7696875006 ps
CPU time 42.46 seconds
Started Oct 15 12:19:06 AM UTC 24
Finished Oct 15 12:19:50 AM UTC 24
Peak memory 209836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010233383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.2010233383
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/47.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/48.hmac_alert_test.3780578947
Short name T469
Test name
Test status
Simulation time 63191496 ps
CPU time 0.89 seconds
Started Oct 15 12:20:09 AM UTC 24
Finished Oct 15 12:20:10 AM UTC 24
Peak memory 206316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3780578947 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.3780578947
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/48.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/48.hmac_back_pressure.2792704545
Short name T475
Test name
Test status
Simulation time 11746293831 ps
CPU time 83.47 seconds
Started Oct 15 12:19:24 AM UTC 24
Finished Oct 15 12:20:49 AM UTC 24
Peak memory 209828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2792704545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.2792704545
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/48.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/48.hmac_burst_wr.3033337762
Short name T470
Test name
Test status
Simulation time 1013662916 ps
CPU time 56.44 seconds
Started Oct 15 12:19:30 AM UTC 24
Finished Oct 15 12:20:28 AM UTC 24
Peak memory 209776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033337762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.3033337762
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/48.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/48.hmac_datapath_stress.3729180945
Short name T480
Test name
Test status
Simulation time 857361391 ps
CPU time 91.4 seconds
Started Oct 15 12:19:24 AM UTC 24
Finished Oct 15 12:20:58 AM UTC 24
Peak memory 397788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3729180945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.3729180945
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/48.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/48.hmac_error.4167233175
Short name T473
Test name
Test status
Simulation time 26395892603 ps
CPU time 52.74 seconds
Started Oct 15 12:19:50 AM UTC 24
Finished Oct 15 12:20:44 AM UTC 24
Peak memory 209888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167233175 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.4167233175
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/48.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/48.hmac_long_msg.3990657430
Short name T487
Test name
Test status
Simulation time 2782827986 ps
CPU time 196.79 seconds
Started Oct 15 12:19:22 AM UTC 24
Finished Oct 15 12:22:42 AM UTC 24
Peak memory 209760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3990657430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.3990657430
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/48.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/48.hmac_smoke.4161271137
Short name T461
Test name
Test status
Simulation time 90286736 ps
CPU time 2.67 seconds
Started Oct 15 12:19:19 AM UTC 24
Finished Oct 15 12:19:23 AM UTC 24
Peak memory 209700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4161271137 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.4161271137
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/48.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/48.hmac_stress_all.1300525418
Short name T496
Test name
Test status
Simulation time 11844716520 ps
CPU time 425.36 seconds
Started Oct 15 12:20:03 AM UTC 24
Finished Oct 15 12:27:13 AM UTC 24
Peak memory 766712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1300525418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.1300525418
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/48.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/48.hmac_wipe_secret.4152015802
Short name T479
Test name
Test status
Simulation time 3561845558 ps
CPU time 64.76 seconds
Started Oct 15 12:19:51 AM UTC 24
Finished Oct 15 12:20:57 AM UTC 24
Peak memory 209700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152015802 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.4152015802
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/48.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/49.hmac_alert_test.2315782728
Short name T477
Test name
Test status
Simulation time 54513586 ps
CPU time 0.85 seconds
Started Oct 15 12:20:52 AM UTC 24
Finished Oct 15 12:20:54 AM UTC 24
Peak memory 206316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315782728 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.2315782728
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/49.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/49.hmac_back_pressure.3041339647
Short name T476
Test name
Test status
Simulation time 2354300336 ps
CPU time 37.1 seconds
Started Oct 15 12:20:12 AM UTC 24
Finished Oct 15 12:20:51 AM UTC 24
Peak memory 209836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041339647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.3041339647
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/49.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/49.hmac_burst_wr.2660149763
Short name T474
Test name
Test status
Simulation time 840125327 ps
CPU time 8.03 seconds
Started Oct 15 12:20:39 AM UTC 24
Finished Oct 15 12:20:48 AM UTC 24
Peak memory 209692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2660149763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.2660149763
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/49.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/49.hmac_datapath_stress.4122969639
Short name T517
Test name
Test status
Simulation time 5461886875 ps
CPU time 1111.86 seconds
Started Oct 15 12:20:29 AM UTC 24
Finished Oct 15 12:39:14 AM UTC 24
Peak memory 764424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4122969639 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.4122969639
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/49.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/49.hmac_error.2460466071
Short name T488
Test name
Test status
Simulation time 8615059262 ps
CPU time 127.32 seconds
Started Oct 15 12:20:41 AM UTC 24
Finished Oct 15 12:22:51 AM UTC 24
Peak memory 209768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460466071 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.2460466071
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/49.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/49.hmac_long_msg.267471658
Short name T472
Test name
Test status
Simulation time 1276974262 ps
CPU time 26.85 seconds
Started Oct 15 12:20:12 AM UTC 24
Finished Oct 15 12:20:40 AM UTC 24
Peak memory 209632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=267471658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.267471658
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/49.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/49.hmac_smoke.4139795884
Short name T468
Test name
Test status
Simulation time 41047404 ps
CPU time 0.87 seconds
Started Oct 15 12:20:09 AM UTC 24
Finished Oct 15 12:20:10 AM UTC 24
Peak memory 206320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4139795884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.4139795884
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/49.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/49.hmac_stress_all.1348104936
Short name T504
Test name
Test status
Simulation time 33160604077 ps
CPU time 733.93 seconds
Started Oct 15 12:20:48 AM UTC 24
Finished Oct 15 12:33:11 AM UTC 24
Peak memory 444944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348104936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.1348104936
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/49.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/49.hmac_wipe_secret.2743620553
Short name T482
Test name
Test status
Simulation time 4693103614 ps
CPU time 55.85 seconds
Started Oct 15 12:20:45 AM UTC 24
Finished Oct 15 12:21:43 AM UTC 24
Peak memory 209740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2743620553 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.2743620553
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/49.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/5.hmac_alert_test.3132836013
Short name T172
Test name
Test status
Simulation time 13191469 ps
CPU time 0.91 seconds
Started Oct 14 11:54:45 PM UTC 24
Finished Oct 14 11:54:47 PM UTC 24
Peak memory 206376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3132836013 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.3132836013
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/5.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/5.hmac_back_pressure.119244349
Short name T92
Test name
Test status
Simulation time 10412729117 ps
CPU time 56.94 seconds
Started Oct 14 11:54:30 PM UTC 24
Finished Oct 14 11:55:28 PM UTC 24
Peak memory 209696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119244349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.119244349
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/5.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/5.hmac_burst_wr.434679083
Short name T49
Test name
Test status
Simulation time 2246151713 ps
CPU time 29.96 seconds
Started Oct 14 11:54:31 PM UTC 24
Finished Oct 14 11:55:03 PM UTC 24
Peak memory 209760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=434679083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.434679083
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/5.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/5.hmac_datapath_stress.3319291704
Short name T227
Test name
Test status
Simulation time 3831890631 ps
CPU time 358.02 seconds
Started Oct 14 11:54:31 PM UTC 24
Finished Oct 15 12:00:34 AM UTC 24
Peak memory 719472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3319291704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.3319291704
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/5.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/5.hmac_error.3256371171
Short name T123
Test name
Test status
Simulation time 1357333436 ps
CPU time 68.08 seconds
Started Oct 14 11:54:38 PM UTC 24
Finished Oct 14 11:55:48 PM UTC 24
Peak memory 209636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3256371171 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.3256371171
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/5.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/5.hmac_long_msg.2458698226
Short name T91
Test name
Test status
Simulation time 2899454018 ps
CPU time 55.76 seconds
Started Oct 14 11:54:29 PM UTC 24
Finished Oct 14 11:55:27 PM UTC 24
Peak memory 209952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2458698226 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.2458698226
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/5.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/5.hmac_smoke.1182445713
Short name T133
Test name
Test status
Simulation time 100597182 ps
CPU time 6.54 seconds
Started Oct 14 11:54:28 PM UTC 24
Finished Oct 14 11:54:36 PM UTC 24
Peak memory 209776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1182445713 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.1182445713
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/5.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/5.hmac_stress_all.3533554816
Short name T524
Test name
Test status
Simulation time 36179640587 ps
CPU time 3681.29 seconds
Started Oct 14 11:54:44 PM UTC 24
Finished Oct 15 12:56:43 AM UTC 24
Peak memory 819880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533554816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.3533554816
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/5.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/5.hmac_stress_all_with_rand_reset.3205419352
Short name T21
Test name
Test status
Simulation time 21816993835 ps
CPU time 326.18 seconds
Started Oct 14 11:54:45 PM UTC 24
Finished Oct 15 12:00:16 AM UTC 24
Peak memory 220444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32054193
52 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all_with_rand_reset.3205419352
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/5.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/5.hmac_wipe_secret.2058060113
Short name T96
Test name
Test status
Simulation time 9140590510 ps
CPU time 62.44 seconds
Started Oct 14 11:54:38 PM UTC 24
Finished Oct 14 11:55:42 PM UTC 24
Peak memory 209704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2058060113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.2058060113
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/5.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/6.hmac_alert_test.571210361
Short name T178
Test name
Test status
Simulation time 11447164 ps
CPU time 0.88 seconds
Started Oct 14 11:55:06 PM UTC 24
Finished Oct 14 11:55:08 PM UTC 24
Peak memory 204328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=571210361 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.571210361
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/6.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/6.hmac_back_pressure.1629448422
Short name T176
Test name
Test status
Simulation time 84277116 ps
CPU time 3.66 seconds
Started Oct 14 11:54:52 PM UTC 24
Finished Oct 14 11:54:56 PM UTC 24
Peak memory 209628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629448422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.1629448422
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/6.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/6.hmac_burst_wr.1681542135
Short name T88
Test name
Test status
Simulation time 1882890755 ps
CPU time 26.14 seconds
Started Oct 14 11:54:56 PM UTC 24
Finished Oct 14 11:55:24 PM UTC 24
Peak memory 209772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1681542135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.1681542135
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/6.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/6.hmac_datapath_stress.1137367081
Short name T252
Test name
Test status
Simulation time 2028985922 ps
CPU time 464.8 seconds
Started Oct 14 11:54:55 PM UTC 24
Finished Oct 15 12:02:45 AM UTC 24
Peak memory 715244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137367081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.1137367081
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/6.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/6.hmac_error.1691359221
Short name T38
Test name
Test status
Simulation time 11670159792 ps
CPU time 161.04 seconds
Started Oct 14 11:54:57 PM UTC 24
Finished Oct 14 11:57:40 PM UTC 24
Peak memory 209824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1691359221 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.1691359221
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/6.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/6.hmac_long_msg.2149982057
Short name T165
Test name
Test status
Simulation time 1117021977 ps
CPU time 21.17 seconds
Started Oct 14 11:54:48 PM UTC 24
Finished Oct 14 11:55:11 PM UTC 24
Peak memory 209636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2149982057 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.2149982057
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/6.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/6.hmac_smoke.2575823797
Short name T174
Test name
Test status
Simulation time 406994999 ps
CPU time 4.61 seconds
Started Oct 14 11:54:48 PM UTC 24
Finished Oct 14 11:54:54 PM UTC 24
Peak memory 209840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2575823797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.2575823797
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/6.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/6.hmac_wipe_secret.2658840768
Short name T179
Test name
Test status
Simulation time 6444808470 ps
CPU time 18.43 seconds
Started Oct 14 11:54:58 PM UTC 24
Finished Oct 14 11:55:17 PM UTC 24
Peak memory 209692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2658840768 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.2658840768
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/6.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/7.hmac_alert_test.161763491
Short name T87
Test name
Test status
Simulation time 11537826 ps
CPU time 0.87 seconds
Started Oct 14 11:55:20 PM UTC 24
Finished Oct 14 11:55:22 PM UTC 24
Peak memory 206316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=161763491 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.161763491
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/7.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/7.hmac_back_pressure.371988707
Short name T70
Test name
Test status
Simulation time 1054318110 ps
CPU time 68.26 seconds
Started Oct 14 11:55:08 PM UTC 24
Finished Oct 14 11:56:18 PM UTC 24
Peak memory 209672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371988707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.371988707
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/7.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/7.hmac_burst_wr.3108725551
Short name T46
Test name
Test status
Simulation time 3136989761 ps
CPU time 50.78 seconds
Started Oct 14 11:55:10 PM UTC 24
Finished Oct 14 11:56:02 PM UTC 24
Peak memory 209972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108725551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.3108725551
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/7.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/7.hmac_datapath_stress.1134308484
Short name T228
Test name
Test status
Simulation time 1622109486 ps
CPU time 321.11 seconds
Started Oct 14 11:55:10 PM UTC 24
Finished Oct 15 12:00:35 AM UTC 24
Peak memory 688620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1134308484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.1134308484
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/7.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/7.hmac_error.3584198189
Short name T191
Test name
Test status
Simulation time 62151711733 ps
CPU time 124.94 seconds
Started Oct 14 11:55:11 PM UTC 24
Finished Oct 14 11:57:19 PM UTC 24
Peak memory 209632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3584198189 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.3584198189
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/7.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/7.hmac_long_msg.1140738080
Short name T210
Test name
Test status
Simulation time 43640295339 ps
CPU time 210.74 seconds
Started Oct 14 11:55:08 PM UTC 24
Finished Oct 14 11:58:42 PM UTC 24
Peak memory 218536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140738080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.1140738080
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/7.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/7.hmac_smoke.3607436921
Short name T19
Test name
Test status
Simulation time 628486618 ps
CPU time 7.64 seconds
Started Oct 14 11:55:06 PM UTC 24
Finished Oct 14 11:55:15 PM UTC 24
Peak memory 209724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3607436921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.3607436921
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/7.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/7.hmac_stress_all.2912063344
Short name T89
Test name
Test status
Simulation time 250946670 ps
CPU time 7.23 seconds
Started Oct 14 11:55:16 PM UTC 24
Finished Oct 14 11:55:24 PM UTC 24
Peak memory 209696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912063344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.2912063344
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/7.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/7.hmac_stress_all_with_rand_reset.2747728021
Short name T23
Test name
Test status
Simulation time 3231582862 ps
CPU time 75.92 seconds
Started Oct 14 11:55:20 PM UTC 24
Finished Oct 14 11:56:38 PM UTC 24
Peak memory 220428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27477280
21 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all_with_rand_reset.2747728021
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/7.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/7.hmac_wipe_secret.1471451038
Short name T75
Test name
Test status
Simulation time 3964456608 ps
CPU time 74.24 seconds
Started Oct 14 11:55:11 PM UTC 24
Finished Oct 14 11:56:27 PM UTC 24
Peak memory 209704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1471451038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.1471451038
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/7.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/8.hmac_alert_test.2620232057
Short name T94
Test name
Test status
Simulation time 18680774 ps
CPU time 0.91 seconds
Started Oct 14 11:55:34 PM UTC 24
Finished Oct 14 11:55:36 PM UTC 24
Peak memory 206376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620232057 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.2620232057
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/8.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/8.hmac_burst_wr.4267981325
Short name T129
Test name
Test status
Simulation time 5642138391 ps
CPU time 41.09 seconds
Started Oct 14 11:55:25 PM UTC 24
Finished Oct 14 11:56:07 PM UTC 24
Peak memory 218512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4267981325 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.4267981325
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/8.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/8.hmac_datapath_stress.3738343655
Short name T344
Test name
Test status
Simulation time 4475494472 ps
CPU time 853 seconds
Started Oct 14 11:55:25 PM UTC 24
Finished Oct 15 12:09:47 AM UTC 24
Peak memory 664112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738343655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.3738343655
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/8.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/8.hmac_error.2068856268
Short name T73
Test name
Test status
Simulation time 12480857572 ps
CPU time 54.87 seconds
Started Oct 14 11:55:25 PM UTC 24
Finished Oct 14 11:56:21 PM UTC 24
Peak memory 209952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068856268 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.2068856268
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/8.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/8.hmac_long_msg.735698311
Short name T93
Test name
Test status
Simulation time 569430046 ps
CPU time 8.9 seconds
Started Oct 14 11:55:23 PM UTC 24
Finished Oct 14 11:55:34 PM UTC 24
Peak memory 209576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=735698311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.735698311
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/8.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/8.hmac_smoke.1865581527
Short name T90
Test name
Test status
Simulation time 2196513576 ps
CPU time 4.13 seconds
Started Oct 14 11:55:20 PM UTC 24
Finished Oct 14 11:55:25 PM UTC 24
Peak memory 209764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865581527 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.1865581527
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/8.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/8.hmac_stress_all.1667848312
Short name T71
Test name
Test status
Simulation time 5240029688 ps
CPU time 49.1 seconds
Started Oct 14 11:55:28 PM UTC 24
Finished Oct 14 11:56:19 PM UTC 24
Peak memory 209700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1667848312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.1667848312
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/8.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/8.hmac_stress_all_with_rand_reset.78351508
Short name T22
Test name
Test status
Simulation time 17264277519 ps
CPU time 50.55 seconds
Started Oct 14 11:55:30 PM UTC 24
Finished Oct 14 11:56:22 PM UTC 24
Peak memory 220560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78351508
-assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all_with_rand_reset.78351508
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/8.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/8.hmac_wipe_secret.3021605237
Short name T97
Test name
Test status
Simulation time 57611990598 ps
CPU time 113.89 seconds
Started Oct 14 11:55:26 PM UTC 24
Finished Oct 14 11:57:22 PM UTC 24
Peak memory 209704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021605237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.3021605237
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/8.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/9.hmac_alert_test.2020232222
Short name T127
Test name
Test status
Simulation time 14821977 ps
CPU time 0.94 seconds
Started Oct 14 11:55:52 PM UTC 24
Finished Oct 14 11:55:54 PM UTC 24
Peak memory 206376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2020232222 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.2020232222
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/9.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/9.hmac_back_pressure.1055380898
Short name T128
Test name
Test status
Simulation time 210482679 ps
CPU time 15.38 seconds
Started Oct 14 11:55:39 PM UTC 24
Finished Oct 14 11:55:55 PM UTC 24
Peak memory 209572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1055380898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.1055380898
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/9.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/9.hmac_burst_wr.2296493049
Short name T125
Test name
Test status
Simulation time 87183238 ps
CPU time 6.36 seconds
Started Oct 14 11:55:41 PM UTC 24
Finished Oct 14 11:55:49 PM UTC 24
Peak memory 209772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296493049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.2296493049
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/9.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/9.hmac_datapath_stress.3175124610
Short name T457
Test name
Test status
Simulation time 30024327198 ps
CPU time 1400.42 seconds
Started Oct 14 11:55:41 PM UTC 24
Finished Oct 15 12:19:16 AM UTC 24
Peak memory 750128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175124610 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.3175124610
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/9.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/9.hmac_error.3116885136
Short name T183
Test name
Test status
Simulation time 5936376632 ps
CPU time 51.17 seconds
Started Oct 14 11:55:44 PM UTC 24
Finished Oct 14 11:56:36 PM UTC 24
Peak memory 209896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3116885136 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.3116885136
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/9.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/9.hmac_long_msg.1548853491
Short name T194
Test name
Test status
Simulation time 9828618977 ps
CPU time 149.14 seconds
Started Oct 14 11:55:37 PM UTC 24
Finished Oct 14 11:58:09 PM UTC 24
Peak memory 209708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1548853491 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.1548853491
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/9.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/9.hmac_smoke.2088583621
Short name T126
Test name
Test status
Simulation time 1153413602 ps
CPU time 15.44 seconds
Started Oct 14 11:55:34 PM UTC 24
Finished Oct 14 11:55:51 PM UTC 24
Peak memory 209960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2088583621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.2088583621
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/9.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/9.hmac_stress_all.2381494079
Short name T423
Test name
Test status
Simulation time 9364069592 ps
CPU time 1214.22 seconds
Started Oct 14 11:55:50 PM UTC 24
Finished Oct 15 12:16:18 AM UTC 24
Peak memory 733736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2381494079 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.2381494079
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/9.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/9.hmac_stress_all_with_rand_reset.1569422954
Short name T31
Test name
Test status
Simulation time 22029916791 ps
CPU time 153.08 seconds
Started Oct 14 11:55:50 PM UTC 24
Finished Oct 14 11:58:26 PM UTC 24
Peak memory 467548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15694229
54 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all_with_rand_reset.1569422954
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/9.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/default/9.hmac_wipe_secret.3668724340
Short name T195
Test name
Test status
Simulation time 10315815813 ps
CPU time 136.75 seconds
Started Oct 14 11:55:50 PM UTC 24
Finished Oct 14 11:58:09 PM UTC 24
Peak memory 209736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3668724340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.3668724340
Directory /workspaces/repo/scratch/os_regression_2024_10_14/hmac-sim-vcs/9.hmac_wipe_secret/latest
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