Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
79.75	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	16	44	73.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	16	44	73.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	4284570	1			T28	5		T33	5		T35	5
all_values[1]	4284570	1			T28	5		T33	5		T35	5
all_values[2]	4284570	1			T28	5		T33	5		T35	5
all_values[3]	4284570	1			T28	5		T33	5		T35	5
all_values[4]	4284570	1			T28	5		T33	5		T35	5
all_values[5]	4284570	1			T28	5		T33	5		T35	5
all_values[6]	4284570	1			T28	5		T33	5		T35	5
all_values[7]	4284570	1			T28	5		T33	5		T35	5
all_values[8]	4284570	1			T28	5		T33	5		T35	5
all_values[9]	4284570	1			T28	5		T33	5		T35	5
all_values[10]	4284570	1			T28	5		T33	5		T35	5
all_values[11]	4284570	1			T28	5		T33	5		T35	5
all_values[12]	4284570	1			T28	5		T33	5		T35	5
all_values[13]	4284570	1			T28	5		T33	5		T35	5
all_values[14]	4284570	1			T28	5		T33	5		T35	5

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

61703050

1

T28

55

T33

55

T35

55

auto[1]

2565500

1

T28

20

T33

20

T35

20

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

64266050

1

T28

25

T33

25

T35

25

auto[1]

2500

1

T28

50

T33

50

T35

50

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	16	44	73.33	16

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	*	--	--	2
[all_values[8] , all_values[9]]	*	[auto[1]]	--	--	4
[all_values[13]]	[auto[1]]	*	--	--	2

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[2]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[3]]	[auto[0]]	[auto[1]]	0	1	1
[all_values[4] , all_values[5]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[7]]	[auto[1]]	[auto[1]]	0	1	1
[all_values[12]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[13]]	[auto[0]]	[auto[1]]	0	1	1
[all_values[14]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	4045620	1			T32	1		T74	1		T76	1
all_values[0]	auto[0]	auto[1]	50	1			T28	1		T33	1		T35	1
all_values[0]	auto[1]	auto[0]	238700	1			T3	4		T4	30		T5	1
all_values[0]	auto[1]	auto[1]	200	1			T28	4		T33	4		T35	4
all_values[1]	auto[0]	auto[0]	4014070	1			T28	1		T33	1		T35	1
all_values[1]	auto[0]	auto[1]	150	1			T28	3		T33	3		T35	3
all_values[1]	auto[1]	auto[0]	270300	1			T3	68		T4	80		T14	1
all_values[1]	auto[1]	auto[1]	50	1			T28	1		T33	1		T35	1
all_values[2]	auto[0]	auto[0]	4284320	1			T32	1		T74	1		T76	1
all_values[2]	auto[0]	auto[1]	150	1			T28	3		T33	3		T35	3
all_values[2]	auto[1]	auto[1]	100	1			T28	2		T33	2		T35	2
all_values[3]	auto[0]	auto[0]	4284570	1			T28	5		T33	5		T35	5
all_values[4]	auto[0]	auto[0]	4284370	1			T28	1		T33	1		T35	1
all_values[4]	auto[0]	auto[1]	50	1			T28	1		T33	1		T35	1
all_values[4]	auto[1]	auto[1]	150	1			T28	3		T33	3		T35	3
all_values[5]	auto[0]	auto[0]	4284320	1			T32	1		T74	1		T76	1
all_values[5]	auto[0]	auto[1]	200	1			T28	4		T33	4		T35	4
all_values[5]	auto[1]	auto[1]	50	1			T28	1		T33	1		T35	1
all_values[6]	auto[0]	auto[0]	3997770	1			T32	1		T74	1		T76	1
all_values[6]	auto[0]	auto[1]	200	1			T28	4		T33	4		T35	4
all_values[6]	auto[1]	auto[0]	286550	1			T3	19		T4	478		T5	1
all_values[6]	auto[1]	auto[1]	50	1			T28	1		T33	1		T35	1
all_values[7]	auto[0]	auto[0]	3950920	1			T32	1		T74	1		T76	1
all_values[7]	auto[0]	auto[1]	250	1			T28	5		T33	5		T35	5
all_values[7]	auto[1]	auto[0]	333400	1			T3	1041		T4	1866		T5	1
all_values[8]	auto[0]	auto[0]	3835820	1			T28	5		T33	5		T35	5
all_values[8]	auto[1]	auto[0]	448750	1			T3	210		T4	2255		T5	1
all_values[9]	auto[0]	auto[0]	3828620	1			T28	5		T33	5		T35	5
all_values[9]	auto[1]	auto[0]	455950	1			T2	1		T3	18		T4	75
all_values[10]	auto[0]	auto[0]	4142370	1			T28	2		T33	2		T35	2
all_values[10]	auto[0]	auto[1]	100	1			T28	2		T33	2		T35	2
all_values[10]	auto[1]	auto[0]	142050	1			T18	2841		T23	2841		T98	2841
all_values[10]	auto[1]	auto[1]	50	1			T28	1		T33	1		T35	1
all_values[11]	auto[0]	auto[0]	3895520	1			T32	1		T74	1		T76	1
all_values[11]	auto[0]	auto[1]	100	1			T28	2		T33	2		T35	2
all_values[11]	auto[1]	auto[0]	388800	1			T18	5015		T11	2761		T12	2761
all_values[11]	auto[1]	auto[1]	150	1			T28	3		T33	3		T35	3
all_values[12]	auto[0]	auto[0]	4284370	1			T28	1		T33	1		T35	1
all_values[12]	auto[0]	auto[1]	100	1			T28	2		T33	2		T35	2
all_values[12]	auto[1]	auto[1]	100	1			T28	2		T33	2		T35	2
all_values[13]	auto[0]	auto[0]	4284570	1			T28	5		T33	5		T35	5
all_values[14]	auto[0]	auto[0]	4284320	1			T32	1		T74	1		T76	1
all_values[14]	auto[0]	auto[1]	150	1			T28	3		T33	3		T35	3
all_values[14]	auto[1]	auto[1]	100	1			T28	2		T33	2		T35	2