Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
77.22	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	18	42	70.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	18	42	70.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	4284570	1			T28	5		T33	5		T35	5
all_pins[1]	4284570	1			T28	5		T33	5		T35	5
all_pins[2]	4284570	1			T28	5		T33	5		T35	5
all_pins[3]	4284570	1			T28	5		T33	5		T35	5
all_pins[4]	4284570	1			T28	5		T33	5		T35	5
all_pins[5]	4284570	1			T28	5		T33	5		T35	5
all_pins[6]	4284570	1			T28	5		T33	5		T35	5
all_pins[7]	4284570	1			T28	5		T33	5		T35	5
all_pins[8]	4284570	1			T28	5		T33	5		T35	5
all_pins[9]	4284570	1			T28	5		T33	5		T35	5
all_pins[10]	4284570	1			T28	5		T33	5		T35	5
all_pins[11]	4284570	1			T28	5		T33	5		T35	5
all_pins[12]	4284570	1			T28	5		T33	5		T35	5
all_pins[13]	4284570	1			T28	5		T33	5		T35	5
all_pins[14]	4284570	1			T28	5		T33	5		T35	5

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	61632000	1			T28	65		T33	65		T35	65
values[0x1]	2636550	1			T28	10		T33	10		T35	10
transitions[0x0=>0x1]	1811250	1			T28	9		T33	9		T35	9
transitions[0x1=>0x0]	1811250	1			T28	9		T33	9		T35	9

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	18	42	70.00	18

Automatically Generated Cross Bins for cp_intr_pins_all_values

Uncovered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	NUMBER	STATUS
[all_pins[2]]	[transitions[0x1=>0x0]]	0	1	1
[all_pins[3] , all_pins[4]]	[values[0x1] , transitions[0x0=>0x1] , transitions[0x1=>0x0]]	--	--	6
[all_pins[5]]	[values[0x1] , transitions[0x0=>0x1]]	--	--	2
[all_pins[11]]	[transitions[0x1=>0x0]]	0	1	1
[all_pins[12] , all_pins[13]]	[values[0x1] , transitions[0x0=>0x1] , transitions[0x1=>0x0]]	--	--	6
[all_pins[14]]	[values[0x1] , transitions[0x0=>0x1]]	--	--	2

Covered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	4045220	1			T28	1		T33	1		T35	1
all_pins[0]	values[0x1]	239350	1			T28	4		T33	4		T35	4
all_pins[0]	transitions[0x0=>0x1]	3500	1			T28	4		T33	4		T35	4
all_pins[0]	transitions[0x1=>0x0]	36950	1			T3	78		T4	92		T57	87
all_pins[1]	values[0x0]	4011770	1			T28	5		T33	5		T35	5
all_pins[1]	values[0x1]	272800	1			T3	78		T4	92		T14	1
all_pins[1]	transitions[0x0=>0x1]	272800	1			T3	78		T4	92		T14	1
all_pins[1]	transitions[0x1=>0x0]	100	1			T28	2		T33	2		T35	2
all_pins[2]	values[0x0]	4284470	1			T28	3		T33	3		T35	3
all_pins[2]	values[0x1]	100	1			T28	2		T33	2		T35	2
all_pins[2]	transitions[0x0=>0x1]	100	1			T28	2		T33	2		T35	2
all_pins[3]	values[0x0]	4284570	1			T28	5		T33	5		T35	5
all_pins[4]	values[0x0]	4284570	1			T28	5		T33	5		T35	5
all_pins[5]	values[0x0]	4284570	1			T28	5		T33	5		T35	5
all_pins[5]	transitions[0x1=>0x0]	290150	1			T3	21		T4	538		T5	1
all_pins[6]	values[0x0]	3994420	1			T28	5		T33	5		T35	5
all_pins[6]	values[0x1]	290150	1			T3	21		T4	538		T5	1
all_pins[6]	transitions[0x0=>0x1]	272350	1			T3	15		T4	396		T9	1
all_pins[6]	transitions[0x1=>0x0]	353750	1			T3	1160		T4	1909		T57	1166
all_pins[7]	values[0x0]	3913020	1			T28	5		T33	5		T35	5
all_pins[7]	values[0x1]	371550	1			T3	1166		T4	2051		T5	1
all_pins[7]	transitions[0x0=>0x1]	288400	1			T3	1040		T4	1180		T57	1057
all_pins[7]	transitions[0x1=>0x0]	391000	1			T3	110		T4	1665		T57	194
all_pins[8]	values[0x0]	3810420	1			T28	5		T33	5		T35	5
all_pins[8]	values[0x1]	474150	1			T3	236		T4	2536		T5	1
all_pins[8]	transitions[0x0=>0x1]	219950	1			T3	236		T4	2517		T57	310
all_pins[8]	transitions[0x1=>0x0]	202850	1			T2	1		T3	18		T4	68
all_pins[9]	values[0x0]	3827520	1			T28	5		T33	5		T35	5
all_pins[9]	values[0x1]	457050	1			T2	1		T3	18		T4	87
all_pins[9]	transitions[0x0=>0x1]	355700	1			T2	1		T3	18		T4	87
all_pins[9]	transitions[0x1=>0x0]	41100	1			T28	1		T33	1		T35	1
all_pins[10]	values[0x0]	4142120	1			T28	4		T33	4		T35	4
all_pins[10]	values[0x1]	142450	1			T28	1		T33	1		T35	1
all_pins[10]	transitions[0x0=>0x1]	9500	1			T18	190		T23	190		T98	190
all_pins[10]	transitions[0x1=>0x0]	256000	1			T28	2		T33	2		T35	2
all_pins[11]	values[0x0]	3895620	1			T28	2		T33	2		T35	2
all_pins[11]	values[0x1]	388950	1			T28	3		T33	3		T35	3
all_pins[11]	transitions[0x0=>0x1]	388950	1			T28	3		T33	3		T35	3
all_pins[12]	values[0x0]	4284570	1			T28	5		T33	5		T35	5
all_pins[13]	values[0x0]	4284570	1			T28	5		T33	5		T35	5
all_pins[14]	values[0x0]	4284570	1			T28	5		T33	5		T35	5
all_pins[14]	transitions[0x1=>0x0]	239350	1			T28	4		T33	4		T35	4